Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1301185	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1514994

1

T1

684

T2

534

T3

1098

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2487181	1			T1	565		T2	275		T3	869
values[0x0]	164251	1			T1	248		T2	231		T3	395
values[0x1]	164747	1			T1	224		T2	249		T3	389

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1032280	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1783899

1

T1

766

T2

586

T3

1234

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10251	1			T11	3		T4	9		T15	4
valid_sources[0x01]	7896	1			T1	3		T11	1		T15	5
valid_sources[0x02]	8356	1			T1	10		T11	3		T4	11
valid_sources[0x03]	8163	1			T1	4		T11	1		T4	6
valid_sources[0x04]	9711	1			T11	3		T15	7		T5	164
valid_sources[0x05]	7924	1			T1	2		T11	5		T15	2
valid_sources[0x06]	8429	1			T1	5		T11	3		T15	7
valid_sources[0x07]	8330	1			T1	2		T11	2		T15	2
valid_sources[0x08]	7328	1			T1	4		T11	5		T15	4
valid_sources[0x09]	8212	1			T1	1		T11	3		T4	3
valid_sources[0x0a]	44327	1			T1	2		T4	11		T15	3
valid_sources[0x0b]	7882	1			T1	1		T4	1		T15	8
valid_sources[0x0c]	9044	1			T1	4		T11	4		T4	11
valid_sources[0x0d]	18430	1			T11	1		T15	2		T5	119
valid_sources[0x0e]	9225	1			T11	3		T12	982		T5	161
valid_sources[0x0f]	7936	1			T11	4		T15	2		T5	167
valid_sources[0x10]	8215	1			T1	3		T4	1		T15	3
valid_sources[0x11]	27755	1			T1	7		T11	2		T4	2
valid_sources[0x12]	9642	1			T1	3		T11	10		T15	6
valid_sources[0x13]	66203	1			T1	2		T15	5		T5	151
valid_sources[0x14]	9497	1			T1	3		T11	3		T4	1
valid_sources[0x15]	8271	1			T1	7		T11	7		T15	6
valid_sources[0x16]	9693	1			T1	4		T3	1653		T4	4
valid_sources[0x17]	8904	1			T1	4		T4	11		T15	3
valid_sources[0x18]	8906	1			T1	9		T11	2		T4	12
valid_sources[0x19]	8276	1			T1	2		T15	7		T5	120
valid_sources[0x1a]	7957	1			T1	2		T11	1		T15	3
valid_sources[0x1b]	8528	1			T11	2		T4	9		T15	2
valid_sources[0x1c]	8739	1			T1	1		T4	5		T15	2
valid_sources[0x1d]	8082	1			T1	5		T11	11		T4	6
valid_sources[0x1e]	9533	1			T1	5		T11	1		T4	1
valid_sources[0x1f]	7749	1			T1	4		T4	7		T15	1
valid_sources[0x20]	7801	1			T1	4		T15	5		T5	147
valid_sources[0x21]	89648	1			T1	2		T11	15		T4	12
valid_sources[0x22]	9591	1			T1	2		T11	10		T15	4
valid_sources[0x23]	10927	1			T1	9		T11	1		T15	6
valid_sources[0x24]	9974	1			T1	7		T11	2		T4	3
valid_sources[0x25]	18510	1			T1	8		T11	2		T4	7
valid_sources[0x26]	8176	1			T1	5		T11	1		T4	2
valid_sources[0x27]	8154	1			T11	1		T15	2		T5	141
valid_sources[0x28]	8495	1			T1	7		T11	3		T4	2
valid_sources[0x29]	8881	1			T1	7		T11	11		T4	9
valid_sources[0x2a]	8886	1			T1	4		T11	6		T4	21
valid_sources[0x2b]	10492	1			T1	3		T11	1		T15	2
valid_sources[0x2c]	9149	1			T1	7		T11	3		T4	1
valid_sources[0x2d]	8207	1			T1	1		T11	3		T15	2
valid_sources[0x2e]	10991	1			T4	1		T15	2		T5	152
valid_sources[0x2f]	9322	1			T1	18		T11	6		T4	8
valid_sources[0x30]	7578	1			T11	3		T4	1		T5	160
valid_sources[0x31]	11217	1			T1	1		T11	7		T15	5
valid_sources[0x32]	9405	1			T1	3		T11	2		T4	14
valid_sources[0x33]	8247	1			T1	7		T15	6		T5	154
valid_sources[0x34]	9960	1			T11	2		T4	16		T15	4
valid_sources[0x35]	9227	1			T1	2		T11	1		T15	4
valid_sources[0x36]	8369	1			T1	2		T11	10		T15	5
valid_sources[0x37]	8519	1			T1	7		T11	2		T4	11
valid_sources[0x38]	8589	1			T1	7		T11	1		T4	3
valid_sources[0x39]	8178	1			T11	2		T15	1		T5	167
valid_sources[0x3a]	8681	1			T1	7		T11	4		T15	6
valid_sources[0x3b]	10062	1			T1	6		T11	2		T15	4
valid_sources[0x3c]	8467	1			T1	12		T11	10		T4	7
valid_sources[0x3d]	9579	1			T1	7		T11	3		T4	5
valid_sources[0x3e]	9023	1			T1	15		T11	14		T4	2
valid_sources[0x3f]	8697	1			T1	7		T11	6		T4	3
valid_sources[0x40]	14762	1			T11	6		T4	11		T15	3
valid_sources[0x41]	9109	1			T1	6		T4	1		T15	1
valid_sources[0x42]	8867	1			T11	1		T15	5		T5	122
valid_sources[0x43]	17908	1			T11	3		T15	3		T5	147
valid_sources[0x44]	12341	1			T1	3		T15	5		T5	141
valid_sources[0x45]	8379	1			T1	1		T11	1		T15	4
valid_sources[0x46]	30712	1			T1	8		T11	3		T4	5
valid_sources[0x47]	9703	1			T1	5		T4	9		T15	2
valid_sources[0x48]	8089	1			T1	9		T11	4		T15	3
valid_sources[0x49]	8262	1			T1	8		T11	3		T4	3
valid_sources[0x4a]	11920	1			T1	17		T15	7		T5	178
valid_sources[0x4b]	10519	1			T1	1		T11	2		T15	3
valid_sources[0x4c]	8044	1			T1	7		T11	4		T4	5
valid_sources[0x4d]	14225	1			T1	1		T11	9		T4	19
valid_sources[0x4e]	8276	1			T1	1		T11	16		T15	3
valid_sources[0x4f]	8986	1			T1	2		T11	5		T15	6
valid_sources[0x50]	8773	1			T1	5		T11	6		T4	12
valid_sources[0x51]	7904	1			T4	13		T15	4		T5	160
valid_sources[0x52]	11252	1			T1	3		T11	9		T4	10
valid_sources[0x53]	8770	1			T1	3		T4	1		T15	2
valid_sources[0x54]	8756	1			T1	12		T11	3		T15	3
valid_sources[0x55]	9843	1			T1	4		T11	9		T4	5
valid_sources[0x56]	7922	1			T4	1		T15	2		T5	131
valid_sources[0x57]	8718	1			T1	4		T15	1		T5	145
valid_sources[0x58]	8907	1			T1	8		T11	6		T15	1
valid_sources[0x59]	10118	1			T1	13		T4	1		T15	8
valid_sources[0x5a]	9018	1			T1	5		T11	16		T15	1
valid_sources[0x5b]	8468	1			T11	2		T15	2		T5	138
valid_sources[0x5c]	8101	1			T15	4		T5	152		T6	15
valid_sources[0x5d]	8170	1			T1	9		T11	2		T4	8
valid_sources[0x5e]	8315	1			T1	2		T11	1		T4	8
valid_sources[0x5f]	8618	1			T1	4		T11	1		T15	4
valid_sources[0x60]	13011	1			T1	9		T11	4		T15	3
valid_sources[0x61]	7988	1			T1	2		T11	4		T4	8
valid_sources[0x62]	8407	1			T11	4		T4	19		T15	3
valid_sources[0x63]	11556	1			T1	9		T11	1		T15	6
valid_sources[0x64]	10643	1			T1	1		T11	3		T4	5
valid_sources[0x65]	8080	1			T1	1		T11	2		T4	1
valid_sources[0x66]	8023	1			T1	3		T11	10		T4	1
valid_sources[0x67]	8702	1			T1	8		T11	8		T4	9
valid_sources[0x68]	9059	1			T1	20		T11	11		T4	4
valid_sources[0x69]	8468	1			T1	4		T4	5		T15	2
valid_sources[0x6a]	13592	1			T11	10		T4	2		T15	3
valid_sources[0x6b]	8267	1			T1	5		T11	8		T15	5
valid_sources[0x6c]	10686	1			T1	4		T4	7		T15	6
valid_sources[0x6d]	9332	1			T1	5		T11	12		T4	8
valid_sources[0x6e]	21780	1			T1	1		T11	2		T15	3
valid_sources[0x6f]	8233	1			T1	4		T11	13		T4	2
valid_sources[0x70]	13656	1			T11	2		T4	4		T15	5
valid_sources[0x71]	8511	1			T1	4		T15	6		T5	150
valid_sources[0x72]	8009	1			T1	9		T11	3		T4	4
valid_sources[0x73]	7822	1			T1	11		T15	2		T5	163
valid_sources[0x74]	9463	1			T1	4		T11	4		T15	4
valid_sources[0x75]	8164	1			T11	3		T4	1		T5	139
valid_sources[0x76]	8440	1			T1	4		T11	6		T4	14
valid_sources[0x77]	7585	1			T1	2		T11	2		T15	6
valid_sources[0x78]	8379	1			T1	1		T11	1		T4	8
valid_sources[0x79]	8460	1			T1	8		T15	4		T5	138
valid_sources[0x7a]	9715	1			T1	5		T11	2		T15	1
valid_sources[0x7b]	12996	1			T1	8		T11	4		T15	2
valid_sources[0x7c]	10648	1			T1	2		T11	5		T5	153
valid_sources[0x7d]	8044	1			T1	2		T11	5		T15	2
valid_sources[0x7e]	7983	1			T1	1		T11	5		T15	4
valid_sources[0x7f]	8441	1			T1	1		T11	2		T15	2
valid_sources[0x80]	9319	1			T1	5		T11	15		T15	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1231116

1

T1

280

T2

112

T3

417

values[0x0]

all_enables

biggest_size

142336

1

T1

209

T2

208

T3

340

values[0x1]

all_enables

biggest_size

141542

1

T1

195

T2

214

T3

341