Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	90343752	13622	0	0
claim_transition_if_regwen_rd_A	90343752	2484	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90343752	13622	0	0
T5	136401	2	0	0
T6	471239	0	0	0
T16	9039	0	0	0
T17	186037	0	0	0
T18	265822	0	0	0
T21	0	3	0	0
T24	23701	0	0	0
T25	4253	0	0	0
T51	30415	0	0	0
T53	0	1	0	0
T55	0	6	0	0
T91	5921	0	0	0
T93	1614	0	0	0
T96	0	3	0	0
T103	0	6	0	0
T116	0	2	0	0
T117	0	1	0	0
T160	0	1	0	0
T161	0	11	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90343752	2484	0	0
T117	123441	1	0	0
T120	0	38	0	0
T128	0	12	0	0
T129	0	7	0	0
T135	0	6	0	0
T162	0	12	0	0
T163	0	43	0	0
T164	0	6	0	0
T165	0	11	0	0
T166	0	43	0	0
T167	1230	0	0	0
T168	27903	0	0	0
T169	11806	0	0	0
T170	97769	0	0	0
T171	18858	0	0	0
T172	25735	0	0	0
T173	2243	0	0	0
T174	2489	0	0	0
T175	22835	0	0	0