Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1541549	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1760095

1

T1

670

T2

122

T10

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2965980	1			T1	516		T2	132		T11	355
values[0x0]	167301	1			T1	233		T2	27		T10	19
values[0x1]	168363	1			T1	263		T2	40		T10	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1224174	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2077470

1

T1

759

T2

140

T10

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9798	1			T1	2		T11	2		T15	1
valid_sources[0x01]	9411	1			T1	2		T11	4		T16	4
valid_sources[0x02]	9328	1			T1	1		T11	4		T14	1
valid_sources[0x03]	9356	1			T1	1		T11	2		T15	1
valid_sources[0x04]	9426	1			T1	4		T10	1		T11	2
valid_sources[0x05]	9444	1			T1	16		T2	2		T11	7
valid_sources[0x06]	10877	1			T1	4		T2	3		T11	5
valid_sources[0x07]	9612	1			T1	10		T10	1		T11	3
valid_sources[0x08]	9909	1			T1	4		T2	3		T11	2
valid_sources[0x09]	21527	1			T1	1		T2	1		T11	1
valid_sources[0x0a]	9346	1			T1	10		T2	1		T10	1
valid_sources[0x0b]	9366	1			T1	5		T2	1		T11	5
valid_sources[0x0c]	9945	1			T1	12		T11	7		T15	1
valid_sources[0x0d]	9717	1			T1	9		T10	2		T11	2
valid_sources[0x0e]	10281	1			T1	1		T2	3		T11	6
valid_sources[0x0f]	9665	1			T1	6		T2	1		T11	1
valid_sources[0x10]	9268	1			T1	2		T11	4		T16	3
valid_sources[0x11]	9706	1			T1	6		T11	5		T14	1
valid_sources[0x12]	9744	1			T11	2		T14	1		T16	1
valid_sources[0x13]	53342	1			T11	3		T14	4		T16	1
valid_sources[0x14]	9412	1			T1	4		T2	1		T11	2
valid_sources[0x15]	9712	1			T1	16		T11	6		T14	1
valid_sources[0x16]	19647	1			T1	3		T11	4		T14	2
valid_sources[0x17]	13624	1			T11	2		T14	1		T15	1
valid_sources[0x18]	9721	1			T1	7		T11	6		T14	3
valid_sources[0x19]	147651	1			T10	1		T11	5		T15	1
valid_sources[0x1a]	9744	1			T1	2		T11	4		T14	3
valid_sources[0x1b]	53587	1			T1	4		T2	2		T11	1
valid_sources[0x1c]	8991	1			T1	6		T11	2		T15	2
valid_sources[0x1d]	9647	1			T11	6		T14	2		T4	109
valid_sources[0x1e]	9788	1			T2	1		T11	5		T16	1
valid_sources[0x1f]	9607	1			T11	5		T15	4		T4	90
valid_sources[0x20]	9468	1			T11	1		T14	3		T15	1
valid_sources[0x21]	9396	1			T2	2		T11	2		T14	3
valid_sources[0x22]	12386	1			T1	9		T11	4		T4	110
valid_sources[0x23]	9709	1			T1	11		T10	1		T11	1
valid_sources[0x24]	9537	1			T11	6		T15	1		T16	1
valid_sources[0x25]	11117	1			T1	5		T2	2		T11	3
valid_sources[0x26]	9357	1			T2	1		T11	5		T14	1
valid_sources[0x27]	9415	1			T11	3		T15	3		T16	2
valid_sources[0x28]	9705	1			T1	6		T11	3		T14	1
valid_sources[0x29]	13469	1			T1	5		T2	4		T11	4
valid_sources[0x2a]	9699	1			T1	4		T2	1		T10	1
valid_sources[0x2b]	9764	1			T1	6		T11	3		T15	1
valid_sources[0x2c]	9514	1			T1	11		T11	2		T14	2
valid_sources[0x2d]	11216	1			T1	3		T2	3		T11	3
valid_sources[0x2e]	9645	1			T1	7		T11	9		T15	1
valid_sources[0x2f]	9598	1			T1	5		T2	2		T11	5
valid_sources[0x30]	11521	1			T1	4		T11	1		T14	1
valid_sources[0x31]	24562	1			T2	1		T11	4		T15	3
valid_sources[0x32]	9498	1			T1	3		T2	3		T11	3
valid_sources[0x33]	9874	1			T2	1		T11	4		T14	1
valid_sources[0x34]	11351	1			T1	13		T2	1		T11	2
valid_sources[0x35]	9663	1			T1	2		T11	3		T15	3
valid_sources[0x36]	9453	1			T1	3		T2	1		T11	5
valid_sources[0x37]	10255	1			T1	6		T2	1		T11	4
valid_sources[0x38]	9787	1			T2	1		T11	2		T14	1
valid_sources[0x39]	9602	1			T1	10		T11	7		T14	2
valid_sources[0x3a]	9484	1			T1	2		T2	4		T11	5
valid_sources[0x3b]	13543	1			T1	8		T2	1		T11	4
valid_sources[0x3c]	9878	1			T1	5		T2	2		T11	3
valid_sources[0x3d]	9584	1			T2	2		T14	1		T15	2
valid_sources[0x3e]	9742	1			T1	5		T11	3		T15	1
valid_sources[0x3f]	12448	1			T1	7		T10	1		T11	4
valid_sources[0x40]	9428	1			T1	1		T2	2		T11	2
valid_sources[0x41]	9869	1			T2	2		T11	2		T15	1
valid_sources[0x42]	9891	1			T1	7		T2	1		T11	6
valid_sources[0x43]	9681	1			T1	10		T11	3		T14	1
valid_sources[0x44]	10066	1			T15	2		T16	9		T4	90
valid_sources[0x45]	9937	1			T1	6		T2	1		T11	7
valid_sources[0x46]	9461	1			T1	1		T2	3		T11	8
valid_sources[0x47]	30726	1			T11	3		T14	3		T15	1
valid_sources[0x48]	12783	1			T1	4		T11	3		T14	1
valid_sources[0x49]	9435	1			T2	2		T11	5		T14	5
valid_sources[0x4a]	9689	1			T1	7		T11	8		T14	4
valid_sources[0x4b]	11154	1			T1	11		T11	5		T14	4
valid_sources[0x4c]	10025	1			T1	10		T2	3		T11	3
valid_sources[0x4d]	9444	1			T1	9		T2	2		T11	3
valid_sources[0x4e]	11336	1			T2	2		T11	4		T15	1
valid_sources[0x4f]	9937	1			T1	3		T2	1		T10	2
valid_sources[0x50]	9577	1			T1	12		T2	1		T11	2
valid_sources[0x51]	9590	1			T1	2		T2	3		T11	1
valid_sources[0x52]	84938	1			T1	1		T11	7		T15	3
valid_sources[0x53]	9561	1			T11	5		T15	3		T16	4
valid_sources[0x54]	9239	1			T1	4		T11	2		T14	1
valid_sources[0x55]	10055	1			T11	5		T14	2		T16	2
valid_sources[0x56]	9699	1			T2	1		T11	2		T14	2
valid_sources[0x57]	9560	1			T1	8		T11	5		T14	2
valid_sources[0x58]	9816	1			T2	1		T11	2		T14	1
valid_sources[0x59]	9864	1			T11	8		T14	1		T15	1
valid_sources[0x5a]	9557	1			T1	1		T2	2		T11	5
valid_sources[0x5b]	11936	1			T1	1		T11	5		T15	2
valid_sources[0x5c]	9260	1			T11	5		T15	1		T16	1
valid_sources[0x5d]	12113	1			T1	4		T11	3		T14	3
valid_sources[0x5e]	9508	1			T1	3		T11	6		T14	5
valid_sources[0x5f]	10729	1			T1	4		T2	2		T11	1
valid_sources[0x60]	10097	1			T1	8		T11	3		T15	2
valid_sources[0x61]	9581	1			T11	3		T14	6		T15	1
valid_sources[0x62]	9948	1			T11	3		T14	2		T16	2
valid_sources[0x63]	13950	1			T1	4		T2	3		T11	3
valid_sources[0x64]	9800	1			T11	6		T14	3		T4	90
valid_sources[0x65]	9557	1			T1	2		T2	1		T11	4
valid_sources[0x66]	9579	1			T1	1		T2	1		T11	3
valid_sources[0x67]	9288	1			T2	1		T11	3		T15	3
valid_sources[0x68]	9900	1			T1	3		T2	3		T11	6
valid_sources[0x69]	10234	1			T1	1		T2	4		T11	7
valid_sources[0x6a]	9385	1			T1	2		T11	2		T4	101
valid_sources[0x6b]	11880	1			T11	6		T14	2		T15	1
valid_sources[0x6c]	9692	1			T1	2		T11	6		T15	1
valid_sources[0x6d]	9116	1			T1	1		T11	10		T15	3
valid_sources[0x6e]	10894	1			T1	11		T11	1		T14	1
valid_sources[0x6f]	9150	1			T1	3		T2	1		T11	6
valid_sources[0x70]	9586	1			T1	8		T2	1		T11	8
valid_sources[0x71]	12943	1			T11	6		T14	1		T16	4
valid_sources[0x72]	9940	1			T1	8		T11	7		T15	1
valid_sources[0x73]	9843	1			T1	5		T2	1		T11	12
valid_sources[0x74]	9582	1			T10	1		T11	4		T14	2
valid_sources[0x75]	9401	1			T1	1		T11	4		T16	5
valid_sources[0x76]	9691	1			T1	2		T2	1		T11	2
valid_sources[0x77]	10097	1			T11	2		T14	2		T16	1
valid_sources[0x78]	10199	1			T1	12		T11	2		T14	4
valid_sources[0x79]	11048	1			T1	1		T11	2		T15	1
valid_sources[0x7a]	9139	1			T11	6		T14	1		T16	2
valid_sources[0x7b]	9225	1			T1	12		T11	1		T14	1
valid_sources[0x7c]	9406	1			T2	2		T11	1		T14	3
valid_sources[0x7d]	10944	1			T1	3		T2	2		T11	9
valid_sources[0x7e]	13427	1			T1	7		T2	3		T11	3
valid_sources[0x7f]	10251	1			T1	12		T11	4		T14	5
valid_sources[0x80]	11071	1			T1	5		T2	1		T11	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1471011

1

T1

246

T2

66

T11

166

values[0x0]

all_enables

biggest_size

145055

1

T1

199

T2

22

T10

6

values[0x1]

all_enables

biggest_size

144029

1

T1

225

T2

34

T10

2