Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	93186206	16308	0	0
claim_transition_if_regwen_rd_A	93186206	1734	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93186206	16308	0	0
T51	0	8	0	0
T81	5814	0	0	0
T93	227147	4	0	0
T94	0	3	0	0
T118	0	15	0	0
T158	0	2	0	0
T159	0	2	0	0
T160	0	9	0	0
T161	0	5	0	0
T162	0	4	0	0
T163	0	2	0	0
T164	1299	0	0	0
T165	57764	0	0	0
T166	3784	0	0	0
T167	27645	0	0	0
T168	21687	0	0	0
T169	43124	0	0	0
T170	4020	0	0	0
T171	7397	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93186206	1734	0	0
T46	1497	0	0	0
T94	227295	5	0	0
T121	0	19	0	0
T126	0	10	0	0
T131	0	11	0	0
T152	0	3	0	0
T158	0	3	0	0
T162	0	10	0	0
T172	0	9	0	0
T173	0	10	0	0
T174	0	9	0	0
T175	62577	0	0	0
T176	8216	0	0	0
T177	10317	0	0	0
T178	1461	0	0	0
T179	4235	0	0	0
T180	9378	0	0	0
T181	1372	0	0	0
T182	1778	0	0	0