Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1638887	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1852868

1

T1

715

T3

187

T9

1125

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3157105	1			T1	556		T3	161		T9	1011
values[0x0]	166759	1			T1	238		T3	64		T9	377
values[0x1]	167891	1			T1	234		T3	64		T9	375

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1302105	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2189650

1

T1

777

T3

211

T9

1264

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8945	1			T1	4		T4	38		T10	2
valid_sources[0x01]	9167	1			T1	4		T9	19		T4	47
valid_sources[0x02]	9033	1			T1	2		T9	8		T4	51
valid_sources[0x03]	9927	1			T1	5		T4	52		T10	2
valid_sources[0x04]	8724	1			T1	6		T9	1		T4	61
valid_sources[0x05]	9219	1			T1	5		T9	1		T4	46
valid_sources[0x06]	11678	1			T1	6		T4	84		T10	1
valid_sources[0x07]	9804	1			T1	3		T9	26		T4	68
valid_sources[0x08]	9103	1			T1	5		T4	66		T10	3
valid_sources[0x09]	8953	1			T1	3		T4	54		T10	13
valid_sources[0x0a]	12266	1			T1	9		T4	54		T10	5
valid_sources[0x0b]	8900	1			T1	2		T4	70		T10	2
valid_sources[0x0c]	9206	1			T1	3		T9	4		T4	61
valid_sources[0x0d]	10289	1			T1	4		T9	8		T4	41
valid_sources[0x0e]	9402	1			T1	5		T9	13		T4	79
valid_sources[0x0f]	12262	1			T1	10		T9	8		T4	46
valid_sources[0x10]	8745	1			T1	1		T4	81		T10	5
valid_sources[0x11]	8951	1			T1	5		T9	21		T4	54
valid_sources[0x12]	9116	1			T1	3		T9	1		T4	83
valid_sources[0x13]	9412	1			T1	2		T9	30		T4	66
valid_sources[0x14]	9472	1			T1	7		T9	18		T4	77
valid_sources[0x15]	9099	1			T1	2		T9	2		T4	69
valid_sources[0x16]	9220	1			T1	4		T9	3		T4	43
valid_sources[0x17]	28846	1			T1	4		T4	41		T10	4
valid_sources[0x18]	10288	1			T1	6		T4	54		T10	4
valid_sources[0x19]	10005	1			T1	5		T9	39		T4	63
valid_sources[0x1a]	9569	1			T1	4		T9	16		T4	58
valid_sources[0x1b]	11120	1			T1	3		T9	5		T4	83
valid_sources[0x1c]	9468	1			T1	2		T4	46		T10	3
valid_sources[0x1d]	9013	1			T1	4		T4	71		T10	2
valid_sources[0x1e]	9828	1			T1	2		T4	57		T10	7
valid_sources[0x1f]	8774	1			T1	6		T9	9		T4	64
valid_sources[0x20]	9011	1			T1	2		T4	68		T10	5
valid_sources[0x21]	11970	1			T1	1		T9	3		T4	42
valid_sources[0x22]	9176	1			T1	3		T9	3		T4	71
valid_sources[0x23]	9525	1			T1	3		T9	12		T4	69
valid_sources[0x24]	8742	1			T1	5		T9	5		T4	72
valid_sources[0x25]	10123	1			T1	6		T9	13		T4	42
valid_sources[0x26]	9022	1			T1	3		T9	5		T4	69
valid_sources[0x27]	10201	1			T1	1		T9	11		T4	68
valid_sources[0x28]	8738	1			T1	3		T4	45		T10	5
valid_sources[0x29]	10308	1			T1	1		T9	1		T4	67
valid_sources[0x2a]	9173	1			T1	3		T4	49		T12	2
valid_sources[0x2b]	28610	1			T1	4		T9	32		T4	44
valid_sources[0x2c]	8996	1			T1	1		T9	21		T4	76
valid_sources[0x2d]	8796	1			T1	2		T9	13		T4	56
valid_sources[0x2e]	9537	1			T1	1		T4	50		T10	5
valid_sources[0x2f]	13489	1			T1	7		T4	71		T10	10
valid_sources[0x30]	45589	1			T1	3		T9	8		T4	61
valid_sources[0x31]	11023	1			T1	5		T4	74		T10	10
valid_sources[0x32]	9139	1			T1	5		T9	23		T4	54
valid_sources[0x33]	72327	1			T1	6		T4	49		T10	4
valid_sources[0x34]	102883	1			T1	7		T9	30		T4	73
valid_sources[0x35]	10975	1			T1	4		T4	62		T10	1
valid_sources[0x36]	8899	1			T1	4		T9	18		T4	44
valid_sources[0x37]	35718	1			T1	2		T9	26		T4	42
valid_sources[0x38]	8837	1			T1	7		T4	41		T10	3
valid_sources[0x39]	9101	1			T1	7		T9	30		T4	41
valid_sources[0x3a]	15501	1			T1	5		T9	27		T4	67
valid_sources[0x3b]	9383	1			T1	9		T9	6		T4	65
valid_sources[0x3c]	9127	1			T1	3		T4	54		T12	3
valid_sources[0x3d]	14674	1			T9	12		T4	49		T10	3
valid_sources[0x3e]	9973	1			T1	1		T9	2		T4	47
valid_sources[0x3f]	9089	1			T1	7		T4	49		T10	3
valid_sources[0x40]	9235	1			T1	2		T9	11		T4	63
valid_sources[0x41]	16880	1			T1	3		T4	72		T10	4
valid_sources[0x42]	9050	1			T1	5		T9	12		T4	56
valid_sources[0x43]	8900	1			T1	4		T9	14		T4	83
valid_sources[0x44]	9063	1			T1	7		T4	57		T10	5
valid_sources[0x45]	10213	1			T1	9		T4	53		T12	13
valid_sources[0x46]	56410	1			T1	5		T9	12		T4	57
valid_sources[0x47]	8775	1			T1	6		T4	62		T10	6
valid_sources[0x48]	8985	1			T1	5		T9	17		T4	52
valid_sources[0x49]	8621	1			T1	3		T4	53		T10	4
valid_sources[0x4a]	66325	1			T1	6		T9	8		T4	73
valid_sources[0x4b]	8860	1			T1	3		T4	61		T10	2
valid_sources[0x4c]	9151	1			T1	4		T9	8		T4	53
valid_sources[0x4d]	9240	1			T1	5		T9	27		T4	51
valid_sources[0x4e]	8807	1			T1	3		T4	60		T10	4
valid_sources[0x4f]	13384	1			T1	5		T4	52		T10	10
valid_sources[0x50]	8875	1			T1	7		T4	82		T10	2
valid_sources[0x51]	9103	1			T1	4		T9	9		T4	60
valid_sources[0x52]	12936	1			T1	2		T4	68		T10	2
valid_sources[0x53]	9985	1			T1	9		T4	72		T10	3
valid_sources[0x54]	17770	1			T1	5		T9	8		T4	51
valid_sources[0x55]	9003	1			T1	5		T4	46		T10	7
valid_sources[0x56]	11329	1			T1	2		T4	63		T10	4
valid_sources[0x57]	22340	1			T1	1		T9	24		T4	85
valid_sources[0x58]	8966	1			T1	8		T4	82		T10	11
valid_sources[0x59]	8936	1			T1	4		T9	19		T4	64
valid_sources[0x5a]	9144	1			T1	4		T4	61		T10	11
valid_sources[0x5b]	9230	1			T1	7		T9	6		T4	75
valid_sources[0x5c]	16119	1			T1	3		T9	20		T4	64
valid_sources[0x5d]	9018	1			T1	5		T4	60		T12	6
valid_sources[0x5e]	9839	1			T1	6		T4	82		T12	9
valid_sources[0x5f]	8930	1			T1	3		T9	7		T4	53
valid_sources[0x60]	8912	1			T1	7		T9	15		T4	38
valid_sources[0x61]	9334	1			T1	4		T9	2		T4	47
valid_sources[0x62]	9946	1			T1	1		T9	2		T4	57
valid_sources[0x63]	10990	1			T1	2		T9	37		T4	60
valid_sources[0x64]	13929	1			T1	5		T9	4		T4	46
valid_sources[0x65]	9163	1			T1	2		T4	49		T10	7
valid_sources[0x66]	12328	1			T1	6		T9	1		T4	48
valid_sources[0x67]	11105	1			T1	2		T9	6		T4	83
valid_sources[0x68]	8842	1			T1	5		T4	50		T10	1
valid_sources[0x69]	8753	1			T1	2		T4	61		T10	9
valid_sources[0x6a]	8822	1			T1	2		T4	66		T10	1
valid_sources[0x6b]	9337	1			T1	4		T4	60		T10	1
valid_sources[0x6c]	23991	1			T1	3		T9	3		T4	48
valid_sources[0x6d]	10489	1			T1	4		T3	289		T9	13
valid_sources[0x6e]	9115	1			T1	6		T4	66		T10	2
valid_sources[0x6f]	8821	1			T1	6		T9	22		T4	37
valid_sources[0x70]	66226	1			T1	1		T9	16		T4	46
valid_sources[0x71]	9653	1			T1	3		T4	49		T10	12
valid_sources[0x72]	8774	1			T1	2		T4	60		T10	1
valid_sources[0x73]	9074	1			T1	3		T9	18		T4	66
valid_sources[0x74]	22326	1			T1	1		T4	61		T10	2
valid_sources[0x75]	10720	1			T1	6		T4	68		T10	11
valid_sources[0x76]	9055	1			T1	3		T9	3		T4	40
valid_sources[0x77]	8873	1			T1	1		T9	5		T4	64
valid_sources[0x78]	8993	1			T1	4		T9	22		T4	65
valid_sources[0x79]	55202	1			T1	3		T4	41		T12	5
valid_sources[0x7a]	8935	1			T4	70		T10	6		T12	3
valid_sources[0x7b]	11033	1			T1	3		T9	2		T4	72
valid_sources[0x7c]	9198	1			T1	4		T9	20		T4	50
valid_sources[0x7d]	8772	1			T1	4		T9	20		T4	51
valid_sources[0x7e]	9050	1			T1	6		T9	3		T4	52
valid_sources[0x7f]	8883	1			T1	2		T4	61		T10	8
valid_sources[0x80]	12378	1			T1	2		T9	9		T4	48

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1564612

1

T1

304

T3

80

T9

485

values[0x0]

all_enables

biggest_size

144384

1

T1

210

T3

53

T9

328

values[0x1]

all_enables

biggest_size

143872

1

T1

201

T3

54

T9

312