Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	105387106	14431	0	0
claim_transition_if_regwen_rd_A	105387106	1375	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105387106	14431	0	0
T22	47860	0	0	0
T23	36403	0	0	0
T33	1159	0	0	0
T52	844802	8	0	0
T62	31252	0	0	0
T81	0	2	0	0
T94	0	13	0	0
T97	0	4	0	0
T119	0	1	0	0
T121	0	3	0	0
T160	0	3	0	0
T161	0	10	0	0
T162	0	3	0	0
T163	0	1	0	0
T164	662168	0	0	0
T165	23898	0	0	0
T166	3730	0	0	0
T167	34745	0	0	0
T168	3069	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105387106	1375	0	0
T98	0	25	0	0
T118	0	10	0	0
T122	0	35	0	0
T129	0	18	0	0
T134	0	44	0	0
T138	0	7	0	0
T162	401687	8	0	0
T163	225409	0	0	0
T169	0	9	0	0
T170	0	6	0	0
T171	0	9	0	0
T172	11314	0	0	0
T173	4074	0	0	0
T174	59163	0	0	0
T175	29335	0	0	0
T176	23312	0	0	0
T177	32254	0	0	0
T178	13054	0	0	0
T179	33563	0	0	0