Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1949602	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2169605

1

T2

3

T3

1436

T4

876

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3780764	1			T3	1543		T4	1064		T10	157
values[0x0]	169364	1			T2	3		T3	385		T4	202
values[0x1]	169079	1			T2	7		T3	391		T4	206

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1550357	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2568850

1

T2

4

T3

1612

T4

992

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12072	1			T3	55		T10	1		T12	2
valid_sources[0x01]	12130	1			T12	1		T14	2		T16	13
valid_sources[0x02]	11976	1			T3	15		T10	1		T12	4
valid_sources[0x03]	11715	1			T3	2		T16	15		T17	1
valid_sources[0x04]	12284	1			T11	12		T12	17		T14	1
valid_sources[0x05]	12732	1			T10	7		T12	2		T16	5
valid_sources[0x06]	12175	1			T3	7		T10	1		T11	17
valid_sources[0x07]	16291	1			T3	28		T10	1		T12	2
valid_sources[0x08]	12352	1			T3	4		T10	1		T12	8
valid_sources[0x09]	12062	1			T3	4		T10	2		T12	1
valid_sources[0x0a]	18319	1			T10	1		T12	4		T13	2
valid_sources[0x0b]	48485	1			T3	9		T10	1		T12	5
valid_sources[0x0c]	11878	1			T2	2		T3	2		T10	1
valid_sources[0x0d]	12230	1			T3	13		T10	1		T12	6
valid_sources[0x0e]	12098	1			T10	1		T12	4		T13	2
valid_sources[0x0f]	11922	1			T3	9		T11	4		T12	11
valid_sources[0x10]	12045	1			T10	1		T12	15		T13	1
valid_sources[0x11]	12194	1			T3	8		T10	2		T11	5
valid_sources[0x12]	12223	1			T3	3		T10	2		T11	7
valid_sources[0x13]	12351	1			T3	34		T10	1		T11	1
valid_sources[0x14]	12366	1			T10	3		T11	8		T12	10
valid_sources[0x15]	12903	1			T3	7		T10	1		T12	4
valid_sources[0x16]	12202	1			T3	9		T10	4		T12	5
valid_sources[0x17]	11729	1			T14	1		T16	63		T18	1
valid_sources[0x18]	48089	1			T3	22		T10	1		T16	74
valid_sources[0x19]	15223	1			T11	1		T12	11		T14	1
valid_sources[0x1a]	12649	1			T10	1		T12	6		T14	1
valid_sources[0x1b]	12657	1			T3	17		T12	8		T14	1
valid_sources[0x1c]	12399	1			T3	18		T11	20		T12	6
valid_sources[0x1d]	14461	1			T3	8		T10	1		T11	2
valid_sources[0x1e]	12180	1			T12	13		T16	72		T17	2
valid_sources[0x1f]	12251	1			T12	5		T13	1		T16	29
valid_sources[0x20]	239526	1			T3	14		T10	2		T11	1
valid_sources[0x21]	12261	1			T12	13		T14	2		T16	28
valid_sources[0x22]	18781	1			T10	6		T12	6		T13	2
valid_sources[0x23]	12231	1			T10	1		T12	11		T13	1
valid_sources[0x24]	11777	1			T14	1		T16	74		T18	3
valid_sources[0x25]	15665	1			T3	10		T10	2		T11	1
valid_sources[0x26]	14887	1			T3	3		T12	11		T14	3
valid_sources[0x27]	13977	1			T3	37		T10	1		T12	2
valid_sources[0x28]	12864	1			T3	15		T10	1		T12	4
valid_sources[0x29]	11991	1			T3	3		T10	1		T12	7
valid_sources[0x2a]	14055	1			T3	29		T12	1		T16	67
valid_sources[0x2b]	11929	1			T2	1		T3	11		T10	1
valid_sources[0x2c]	13527	1			T11	5		T12	3		T14	2
valid_sources[0x2d]	13638	1			T10	3		T12	3		T14	1
valid_sources[0x2e]	12356	1			T10	1		T11	3		T12	10
valid_sources[0x2f]	11769	1			T3	16		T10	1		T12	6
valid_sources[0x30]	13125	1			T3	19		T12	8		T14	1
valid_sources[0x31]	12157	1			T3	21		T10	2		T12	12
valid_sources[0x32]	12256	1			T10	1		T12	8		T14	1
valid_sources[0x33]	12611	1			T11	3		T12	1		T14	2
valid_sources[0x34]	11821	1			T3	1		T10	1		T12	14
valid_sources[0x35]	11814	1			T3	23		T10	1		T12	2
valid_sources[0x36]	12181	1			T10	1		T11	6		T12	5
valid_sources[0x37]	12358	1			T3	16		T12	1		T14	1
valid_sources[0x38]	12350	1			T10	2		T12	7		T13	1
valid_sources[0x39]	12096	1			T3	11		T12	6		T14	3
valid_sources[0x3a]	12125	1			T10	3		T16	23		T17	3
valid_sources[0x3b]	12460	1			T3	14		T10	1		T11	2
valid_sources[0x3c]	12255	1			T3	35		T11	6		T12	7
valid_sources[0x3d]	61926	1			T3	5		T10	1		T16	130
valid_sources[0x3e]	12128	1			T3	56		T10	2		T11	9
valid_sources[0x3f]	13047	1			T3	16		T10	1		T12	2
valid_sources[0x40]	11805	1			T10	6		T11	4		T12	2
valid_sources[0x41]	12069	1			T3	24		T11	1		T12	5
valid_sources[0x42]	12353	1			T3	32		T10	1		T11	10
valid_sources[0x43]	11931	1			T12	3		T16	161		T17	4
valid_sources[0x44]	12056	1			T10	3		T12	4		T14	1
valid_sources[0x45]	11967	1			T3	5		T10	2		T12	7
valid_sources[0x46]	11836	1			T12	6		T16	51		T17	1
valid_sources[0x47]	12407	1			T3	32		T10	1		T12	6
valid_sources[0x48]	11861	1			T12	7		T13	1		T14	2
valid_sources[0x49]	12123	1			T3	3		T11	6		T12	3
valid_sources[0x4a]	11784	1			T12	6		T14	2		T16	67
valid_sources[0x4b]	11982	1			T10	3		T12	6		T14	1
valid_sources[0x4c]	13871	1			T3	5		T12	4		T14	2
valid_sources[0x4d]	12660	1			T10	2		T12	17		T16	93
valid_sources[0x4e]	12563	1			T3	16		T10	3		T12	7
valid_sources[0x4f]	17067	1			T12	7		T16	79		T49	21
valid_sources[0x50]	12269	1			T3	5		T10	2		T12	5
valid_sources[0x51]	12283	1			T2	6		T3	1		T10	1
valid_sources[0x52]	11976	1			T12	1		T16	13		T17	4
valid_sources[0x53]	11913	1			T10	4		T12	11		T14	1
valid_sources[0x54]	12325	1			T3	34		T10	1		T11	5
valid_sources[0x55]	42786	1			T10	2		T14	1		T16	61
valid_sources[0x56]	13260	1			T3	13		T11	9		T12	6
valid_sources[0x57]	12186	1			T10	1		T14	1		T16	21
valid_sources[0x58]	11952	1			T3	2		T10	1		T11	2
valid_sources[0x59]	11562	1			T3	1		T10	3		T12	4
valid_sources[0x5a]	13558	1			T3	13		T12	1		T13	1
valid_sources[0x5b]	13658	1			T3	9		T12	9		T14	1
valid_sources[0x5c]	14834	1			T14	2		T16	80		T17	1
valid_sources[0x5d]	12266	1			T10	1		T11	4		T12	2
valid_sources[0x5e]	42890	1			T3	1		T12	9		T14	2
valid_sources[0x5f]	14918	1			T3	15		T10	4		T12	6
valid_sources[0x60]	11974	1			T10	1		T12	13		T16	69
valid_sources[0x61]	12109	1			T3	9		T10	2		T12	6
valid_sources[0x62]	11698	1			T10	1		T11	11		T12	7
valid_sources[0x63]	12022	1			T3	9		T10	2		T12	5
valid_sources[0x64]	15818	1			T3	18		T10	1		T11	12
valid_sources[0x65]	12210	1			T3	2		T10	2		T12	4
valid_sources[0x66]	23472	1			T3	15		T10	2		T12	1
valid_sources[0x67]	11793	1			T10	1		T14	1		T16	57
valid_sources[0x68]	12346	1			T3	8		T10	1		T12	5
valid_sources[0x69]	18142	1			T10	2		T11	6		T12	4
valid_sources[0x6a]	12485	1			T3	1		T12	5		T14	1
valid_sources[0x6b]	12105	1			T10	1		T11	8		T12	7
valid_sources[0x6c]	12478	1			T10	1		T12	6		T15	16
valid_sources[0x6d]	12322	1			T12	15		T13	2		T14	1
valid_sources[0x6e]	12360	1			T11	1		T14	4		T16	39
valid_sources[0x6f]	12272	1			T3	7		T12	6		T15	4
valid_sources[0x70]	11567	1			T3	27		T10	2		T12	5
valid_sources[0x71]	13646	1			T3	5		T10	3		T12	14
valid_sources[0x72]	11974	1			T3	5		T10	4		T12	6
valid_sources[0x73]	15432	1			T10	1		T11	1		T12	3
valid_sources[0x74]	13328	1			T3	6		T10	2		T11	14
valid_sources[0x75]	13399	1			T10	4		T11	3		T14	4
valid_sources[0x76]	28701	1			T3	4		T10	1		T11	10
valid_sources[0x77]	13391	1			T10	2		T12	5		T13	1
valid_sources[0x78]	11763	1			T10	1		T12	8		T16	49
valid_sources[0x79]	12369	1			T10	1		T12	4		T14	1
valid_sources[0x7a]	12179	1			T10	2		T12	1		T14	2
valid_sources[0x7b]	12055	1			T3	3		T10	1		T16	62
valid_sources[0x7c]	12060	1			T3	41		T10	2		T12	11
valid_sources[0x7d]	12005	1			T10	1		T11	5		T12	9
valid_sources[0x7e]	13689	1			T3	10		T10	2		T12	8
valid_sources[0x7f]	11973	1			T3	9		T10	1		T12	9
valid_sources[0x80]	14331	1			T3	9		T11	1		T12	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1878223

1

T3

766

T4

521

T10

64

values[0x0]

all_enables

biggest_size

146730

1

T2

1

T3

334

T4

168

values[0x1]

all_enables

biggest_size

144652

1

T2

2

T3

336

T4

187