SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 91.67 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_tb.dut.u_otp_lc_data_i_rma_token_valid_if | 83.33 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_otp_lc_data_i_secrets_valid_if | 83.33 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_otp_lc_data_i_test_tokens_valid_if | 83.33 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_clk_byp_ack_i_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[0].lc_tx_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[1].lc_tx_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
false | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 234 | 1 | T72 | 8 | T73 | 1 | T48 | 2 | ||||
others[1] | 284 | 1 | T4 | 4 | T72 | 2 | T73 | 6 | ||||
others[2] | 256 | 1 | T4 | 6 | T72 | 2 | T73 | 2 | ||||
others[3] | 460 | 1 | T4 | 12 | T72 | 16 | T73 | 8 | ||||
true | 55378 | 1 | T1 | 81 | T2 | 1 | T3 | 98 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
true | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 260 | 1 | T4 | 7 | T72 | 10 | T48 | 12 | ||||
others[1] | 280 | 1 | T4 | 6 | T72 | 10 | T48 | 2 | ||||
others[2] | 268 | 1 | T4 | 2 | T72 | 4 | T73 | 4 | ||||
others[3] | 402 | 1 | T4 | 6 | T72 | 17 | T73 | 12 | ||||
false | 55405 | 1 | T1 | 81 | T2 | 1 | T3 | 98 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
false | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 248 | 1 | T4 | 4 | T72 | 6 | T73 | 4 | ||||
others[1] | 269 | 1 | T4 | 6 | T72 | 12 | T73 | 4 | ||||
others[2] | 299 | 1 | T4 | 4 | T72 | 4 | T73 | 8 | ||||
others[3] | 423 | 1 | T4 | 4 | T72 | 14 | T73 | 14 | ||||
true | 55381 | 1 | T1 | 81 | T2 | 1 | T3 | 98 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 124 | 1 | T4 | 1 | T72 | 2 | T73 | 6 | ||||
others[1] | 134 | 1 | T4 | 4 | T72 | 5 | T73 | 2 | ||||
others[2] | 140 | 1 | T4 | 2 | T72 | 10 | T73 | 2 | ||||
others[3] | 211 | 1 | T4 | 5 | T72 | 2 | T73 | 4 | ||||
false | 978388 | 1 | T1 | 11820 | T2 | 1 | T3 | 98 | ||||
true | 922292 | 1 | T1 | 11739 | T14 | 2 | T49 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 131 | 1 | T4 | 1 | T72 | 3 | T73 | 3 | ||||
others[1] | 120 | 1 | T4 | 2 | T72 | 5 | T73 | 3 | ||||
others[2] | 120 | 1 | T4 | 2 | T72 | 5 | T73 | 3 | ||||
others[3] | 238 | 1 | T4 | 4 | T72 | 5 | T73 | 4 | ||||
false | 2996676 | 1 | T1 | 7734 | T2 | 1 | T3 | 102 | ||||
true | 2940656 | 1 | T1 | 7653 | T3 | 4 | T4 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 131 | 1 | T4 | 1 | T72 | 3 | T73 | 3 | ||||
others[1] | 120 | 1 | T4 | 2 | T72 | 5 | T73 | 3 | ||||
others[2] | 120 | 1 | T4 | 2 | T72 | 5 | T73 | 3 | ||||
others[3] | 238 | 1 | T4 | 4 | T72 | 5 | T73 | 4 | ||||
false | 2996676 | 1 | T1 | 7734 | T2 | 1 | T3 | 102 | ||||
true | 2940656 | 1 | T1 | 7653 | T3 | 4 | T4 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |