Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	96859234	15638	0	0
claim_transition_if_regwen_rd_A	96859234	1665	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96859234	15638	0	0
T26	51069	0	0	0
T56	0	17	0	0
T83	1599	0	0	0
T96	151269	2	0	0
T97	139223	2	0	0
T100	936	0	0	0
T101	2067	0	0	0
T102	16144	0	0	0
T103	5534	0	0	0
T104	69538	0	0	0
T105	6254	0	0	0
T120	0	1	0	0
T124	0	14	0	0
T159	0	3	0	0
T160	0	2	0	0
T161	0	9	0	0
T162	0	6	0	0
T163	0	6	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96859234	1665	0	0
T83	1599	0	0	0
T97	139223	6	0	0
T105	6254	0	0	0
T120	0	7	0	0
T123	0	2	0	0
T128	0	11	0	0
T160	0	4	0	0
T164	0	13	0	0
T165	0	143	0	0
T166	0	25	0	0
T167	0	6	0	0
T168	0	7	0	0
T169	82876	0	0	0
T170	30213	0	0	0
T171	382936	0	0	0
T172	21755	0	0	0
T173	47333	0	0	0
T174	1139	0	0	0
T175	1658	0	0	0