Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1723344	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1935218

1

T1

587

T2

619

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3327742	1			T1	377		T2	480		T3	27
values[0x0]	165187	1			T1	226		T2	227		T3	4
values[0x1]	165633	1			T1	254		T2	245		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1370710	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2287852

1

T1

651

T2

695

T3

26

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10506	1			T1	1		T2	3		T11	4
valid_sources[0x01]	10842	1			T1	3		T2	3		T12	2
valid_sources[0x02]	12332	1			T1	4		T2	1		T13	3
valid_sources[0x03]	179871	1			T1	1		T12	1		T13	8
valid_sources[0x04]	13223	1			T1	2		T2	3		T12	1
valid_sources[0x05]	10918	1			T1	5		T2	3		T11	1
valid_sources[0x06]	10577	1			T1	3		T2	5		T3	1
valid_sources[0x07]	10391	1			T1	1		T2	1		T12	2
valid_sources[0x08]	10678	1			T1	4		T12	2		T13	1
valid_sources[0x09]	10899	1			T1	3		T12	3		T13	5
valid_sources[0x0a]	10649	1			T1	3		T2	10		T3	2
valid_sources[0x0b]	10771	1			T1	2		T2	8		T12	2
valid_sources[0x0c]	10987	1			T1	3		T2	2		T11	3
valid_sources[0x0d]	55396	1			T1	5		T2	10		T12	2
valid_sources[0x0e]	10576	1			T2	2		T11	3		T13	13
valid_sources[0x0f]	11312	1			T2	5		T11	2		T13	7
valid_sources[0x10]	10929	1			T1	4		T2	4		T11	1
valid_sources[0x11]	10921	1			T1	4		T2	8		T12	2
valid_sources[0x12]	10628	1			T1	2		T12	3		T14	7
valid_sources[0x13]	11845	1			T1	2		T2	3		T13	5
valid_sources[0x14]	12150	1			T2	10		T12	3		T13	4
valid_sources[0x15]	10763	1			T1	6		T2	11		T12	2
valid_sources[0x16]	10501	1			T1	3		T2	3		T13	2
valid_sources[0x17]	11110	1			T1	1		T2	4		T11	2
valid_sources[0x18]	10476	1			T1	1		T2	2		T12	1
valid_sources[0x19]	10807	1			T1	10		T2	1		T12	1
valid_sources[0x1a]	11042	1			T1	7		T2	1		T12	3
valid_sources[0x1b]	10710	1			T1	5		T2	4		T11	1
valid_sources[0x1c]	10863	1			T1	1		T2	11		T11	4
valid_sources[0x1d]	11010	1			T2	1		T13	14		T14	3
valid_sources[0x1e]	10901	1			T1	1		T2	4		T3	1
valid_sources[0x1f]	13534	1			T1	3		T11	2		T12	3
valid_sources[0x20]	17486	1			T1	1		T2	1		T13	29
valid_sources[0x21]	12510	1			T1	1		T2	19		T11	1
valid_sources[0x22]	10311	1			T1	5		T2	2		T3	1
valid_sources[0x23]	11223	1			T1	11		T2	2		T11	3
valid_sources[0x24]	10538	1			T1	4		T2	1		T12	3
valid_sources[0x25]	10773	1			T2	3		T11	1		T12	3
valid_sources[0x26]	10695	1			T1	2		T2	15		T13	10
valid_sources[0x27]	11308	1			T1	4		T3	1		T13	4
valid_sources[0x28]	10492	1			T1	4		T2	8		T12	1
valid_sources[0x29]	10319	1			T1	2		T2	9		T3	1
valid_sources[0x2a]	11009	1			T1	4		T2	6		T12	2
valid_sources[0x2b]	10545	1			T1	1		T2	5		T12	1
valid_sources[0x2c]	11066	1			T1	3		T2	4		T13	3
valid_sources[0x2d]	10404	1			T1	3		T2	4		T14	5
valid_sources[0x2e]	10805	1			T2	1		T12	1		T13	1
valid_sources[0x2f]	10544	1			T1	1		T2	5		T12	4
valid_sources[0x30]	11169	1			T1	3		T2	1		T12	4
valid_sources[0x31]	11228	1			T1	2		T2	8		T11	1
valid_sources[0x32]	10617	1			T2	2		T12	2		T13	17
valid_sources[0x33]	10150	1			T1	1		T2	6		T12	5
valid_sources[0x34]	10114	1			T1	3		T2	6		T12	1
valid_sources[0x35]	12108	1			T1	6		T2	12		T12	2
valid_sources[0x36]	41879	1			T1	8		T11	4		T12	1
valid_sources[0x37]	10610	1			T1	5		T2	5		T14	3
valid_sources[0x38]	13205	1			T1	4		T2	2		T12	3
valid_sources[0x39]	10824	1			T1	2		T11	1		T12	3
valid_sources[0x3a]	59281	1			T1	5		T2	4		T11	1
valid_sources[0x3b]	11120	1			T2	1		T11	1		T12	1
valid_sources[0x3c]	13721	1			T1	5		T2	6		T3	1
valid_sources[0x3d]	11569	1			T1	2		T12	2		T13	7
valid_sources[0x3e]	10043	1			T2	3		T13	10		T14	1
valid_sources[0x3f]	10732	1			T1	2		T2	2		T12	3
valid_sources[0x40]	10596	1			T1	7		T2	3		T13	2
valid_sources[0x41]	10741	1			T1	3		T2	7		T12	2
valid_sources[0x42]	10132	1			T1	6		T2	2		T3	1
valid_sources[0x43]	10774	1			T1	8		T11	1		T12	2
valid_sources[0x44]	11785	1			T1	1		T2	1		T11	1
valid_sources[0x45]	11309	1			T1	2		T2	2		T12	5
valid_sources[0x46]	11056	1			T1	4		T2	2		T3	1
valid_sources[0x47]	13415	1			T1	1		T2	2		T12	1
valid_sources[0x48]	10293	1			T1	9		T2	2		T11	1
valid_sources[0x49]	13106	1			T1	3		T12	5		T14	4
valid_sources[0x4a]	12020	1			T1	1		T2	3		T14	7
valid_sources[0x4b]	10608	1			T2	1		T12	1		T14	4
valid_sources[0x4c]	10214	1			T1	8		T2	6		T12	1
valid_sources[0x4d]	10585	1			T1	2		T2	14		T11	1
valid_sources[0x4e]	10580	1			T1	13		T3	1		T11	2
valid_sources[0x4f]	10742	1			T1	3		T2	8		T3	1
valid_sources[0x50]	12551	1			T1	1		T2	1		T3	1
valid_sources[0x51]	10726	1			T2	1		T13	11		T14	7
valid_sources[0x52]	11015	1			T1	8		T2	2		T11	1
valid_sources[0x53]	10634	1			T2	3		T11	1		T12	3
valid_sources[0x54]	10998	1			T1	5		T2	1		T12	4
valid_sources[0x55]	10692	1			T2	2		T11	1		T12	3
valid_sources[0x56]	10771	1			T1	1		T2	2		T12	3
valid_sources[0x57]	15015	1			T1	5		T2	3		T11	3
valid_sources[0x58]	10932	1			T1	2		T2	4		T11	1
valid_sources[0x59]	10501	1			T1	2		T2	2		T12	3
valid_sources[0x5a]	10901	1			T1	3		T2	10		T12	1
valid_sources[0x5b]	10860	1			T1	3		T2	2		T12	3
valid_sources[0x5c]	10696	1			T1	4		T2	14		T11	2
valid_sources[0x5d]	10617	1			T1	8		T2	2		T13	11
valid_sources[0x5e]	10691	1			T1	3		T2	3		T11	3
valid_sources[0x5f]	11157	1			T1	7		T2	7		T11	9
valid_sources[0x60]	10653	1			T1	4		T2	2		T12	2
valid_sources[0x61]	11501	1			T1	2		T2	6		T11	1
valid_sources[0x62]	10476	1			T1	3		T2	1		T11	4
valid_sources[0x63]	11634	1			T1	3		T11	2		T12	1
valid_sources[0x64]	10523	1			T1	3		T2	2		T12	1
valid_sources[0x65]	12478	1			T2	5		T11	1		T12	3
valid_sources[0x66]	10786	1			T2	3		T11	3		T13	5
valid_sources[0x67]	11283	1			T1	2		T2	4		T3	1
valid_sources[0x68]	12059	1			T1	1		T2	6		T12	3
valid_sources[0x69]	87794	1			T1	4		T2	2		T12	1
valid_sources[0x6a]	14290	1			T1	6		T2	6		T12	1
valid_sources[0x6b]	12875	1			T1	1		T2	1		T13	9
valid_sources[0x6c]	11785	1			T1	3		T2	5		T11	2
valid_sources[0x6d]	11400	1			T1	1		T11	1		T12	2
valid_sources[0x6e]	10230	1			T1	3		T2	1		T12	2
valid_sources[0x6f]	38776	1			T1	2		T2	4		T14	1
valid_sources[0x70]	11034	1			T1	6		T2	3		T12	2
valid_sources[0x71]	10800	1			T1	1		T2	7		T12	1
valid_sources[0x72]	10406	1			T1	3		T2	1		T12	1
valid_sources[0x73]	11031	1			T1	5		T2	4		T11	2
valid_sources[0x74]	10941	1			T1	8		T2	4		T12	5
valid_sources[0x75]	11821	1			T1	3		T2	4		T12	4
valid_sources[0x76]	12195	1			T1	4		T13	4		T14	4
valid_sources[0x77]	10838	1			T2	8		T12	2		T13	2
valid_sources[0x78]	10929	1			T1	2		T2	10		T13	6
valid_sources[0x79]	11039	1			T1	2		T2	3		T12	1
valid_sources[0x7a]	11743	1			T1	2		T2	4		T11	1
valid_sources[0x7b]	11043	1			T1	4		T2	2		T12	3
valid_sources[0x7c]	10388	1			T1	8		T2	4		T13	4
valid_sources[0x7d]	11369	1			T1	2		T2	2		T12	2
valid_sources[0x7e]	10918	1			T2	5		T11	2		T12	1
valid_sources[0x7f]	11544	1			T1	3		T2	6		T11	1
valid_sources[0x80]	13216	1			T1	2		T2	3		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1650465

1

T1

164

T2

213

T3

11

values[0x0]

all_enables

biggest_size

143037

1

T1

207

T2

198

T3

3

values[0x1]

all_enables

biggest_size

141716

1

T1

216

T2

208

T3

4