Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	106524092	14584	0	0
claim_transition_if_regwen_rd_A	106524092	1512	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106524092	14584	0	0
T8	13973	0	0	0
T38	192050	14	0	0
T39	19195	0	0	0
T45	249915	9	0	0
T51	0	4	0	0
T55	323108	15	0	0
T57	0	15	0	0
T67	2904	0	0	0
T93	0	3	0	0
T96	0	2	0	0
T109	0	6	0	0
T147	0	11	0	0
T148	0	1	0	0
T149	38273	0	0	0
T150	23234	0	0	0
T151	2510	0	0	0
T152	26311	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106524092	1512	0	0
T51	314063	8	0	0
T70	1853	0	0	0
T89	11226	0	0	0
T96	0	16	0	0
T103	1229	0	0	0
T148	0	12	0	0
T153	0	11	0	0
T154	0	7	0	0
T155	0	4	0	0
T156	0	100	0	0
T157	0	11	0	0
T158	0	17	0	0
T159	0	52	0	0
T160	259316	0	0	0
T161	1881	0	0	0
T162	13662	0	0	0
T163	29345	0	0	0
T164	40964	0	0	0
T165	3227	0	0	0