Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1773566	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1999118

1

T1

14

T2

12

T4

1501

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3417808	1			T1	5		T2	393		T4	1786
values[0x0]	176826	1			T1	7		T2	12		T4	347
values[0x1]	178050	1			T1	8		T2	4		T4	381

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1408641	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2364043

1

T1

15

T2

143

T4

1740

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10004	1			T4	3		T5	3		T11	5
valid_sources[0x01]	10227	1			T4	15		T5	3		T11	12
valid_sources[0x02]	10260	1			T4	4		T11	14		T13	55
valid_sources[0x03]	10478	1			T4	5		T5	1		T11	15
valid_sources[0x04]	10066	1			T11	16		T13	55		T14	5
valid_sources[0x05]	10151	1			T4	1		T5	4		T11	14
valid_sources[0x06]	13951	1			T4	5		T5	1		T11	11
valid_sources[0x07]	10376	1			T4	6		T11	10		T13	41
valid_sources[0x08]	11687	1			T4	29		T11	7		T12	1
valid_sources[0x09]	9947	1			T4	32		T5	2		T11	10
valid_sources[0x0a]	38896	1			T4	12		T5	2		T11	13
valid_sources[0x0b]	21664	1			T4	12		T5	2		T11	5
valid_sources[0x0c]	12297	1			T4	14		T5	3		T11	7
valid_sources[0x0d]	11521	1			T4	13		T11	9		T13	69
valid_sources[0x0e]	10329	1			T4	16		T11	5		T13	68
valid_sources[0x0f]	10310	1			T4	1		T5	2		T11	16
valid_sources[0x10]	9827	1			T4	7		T5	1		T11	7
valid_sources[0x11]	16936	1			T4	11		T11	12		T13	56
valid_sources[0x12]	11254	1			T4	6		T5	1		T11	11
valid_sources[0x13]	10413	1			T4	29		T5	3		T11	11
valid_sources[0x14]	10112	1			T4	7		T5	1		T11	6
valid_sources[0x15]	10213	1			T4	27		T11	12		T13	32
valid_sources[0x16]	10020	1			T4	10		T5	2		T11	8
valid_sources[0x17]	99299	1			T4	44		T5	3		T11	7
valid_sources[0x18]	12121	1			T4	13		T5	2		T11	11
valid_sources[0x19]	10108	1			T4	29		T5	2		T11	11
valid_sources[0x1a]	10014	1			T4	9		T5	6		T11	9
valid_sources[0x1b]	10190	1			T4	9		T5	3		T11	9
valid_sources[0x1c]	9796	1			T4	4		T5	1		T11	14
valid_sources[0x1d]	10176	1			T2	68		T4	2		T5	1
valid_sources[0x1e]	11869	1			T4	5		T5	1		T11	16
valid_sources[0x1f]	9734	1			T4	7		T5	1		T11	13
valid_sources[0x20]	9929	1			T4	10		T5	2		T11	12
valid_sources[0x21]	23703	1			T4	9		T5	2		T11	8
valid_sources[0x22]	10024	1			T4	18		T5	4		T11	16
valid_sources[0x23]	11544	1			T4	11		T11	9		T12	1
valid_sources[0x24]	10323	1			T4	4		T5	1		T11	8
valid_sources[0x25]	12395	1			T4	14		T5	3		T11	13
valid_sources[0x26]	9969	1			T4	12		T5	2		T11	7
valid_sources[0x27]	10204	1			T4	3		T5	1		T11	14
valid_sources[0x28]	10327	1			T5	4		T11	15		T13	56
valid_sources[0x29]	10334	1			T4	27		T5	1		T11	12
valid_sources[0x2a]	9976	1			T4	6		T5	1		T11	13
valid_sources[0x2b]	10210	1			T4	8		T5	2		T11	17
valid_sources[0x2c]	11620	1			T4	3		T5	2		T11	15
valid_sources[0x2d]	10692	1			T4	6		T5	4		T11	7
valid_sources[0x2e]	9900	1			T4	1		T5	3		T11	2
valid_sources[0x2f]	12750	1			T4	3		T5	1		T11	11
valid_sources[0x30]	10937	1			T4	10		T5	2		T11	8
valid_sources[0x31]	31532	1			T4	15		T5	1		T11	9
valid_sources[0x32]	9603	1			T2	72		T5	2		T11	7
valid_sources[0x33]	9940	1			T4	4		T5	2		T11	13
valid_sources[0x34]	10220	1			T4	11		T5	2		T11	10
valid_sources[0x35]	10206	1			T4	30		T5	1		T11	11
valid_sources[0x36]	11102	1			T2	110		T11	12		T13	34
valid_sources[0x37]	10316	1			T4	15		T5	1		T11	5
valid_sources[0x38]	10990	1			T4	24		T5	3		T11	6
valid_sources[0x39]	10268	1			T4	13		T5	4		T11	11
valid_sources[0x3a]	10089	1			T11	10		T12	1		T13	49
valid_sources[0x3b]	9877	1			T4	10		T11	6		T13	70
valid_sources[0x3c]	20463	1			T4	28		T5	2		T11	8
valid_sources[0x3d]	11354	1			T4	4		T5	1		T11	10
valid_sources[0x3e]	50946	1			T4	6		T5	1		T11	12
valid_sources[0x3f]	10274	1			T4	11		T11	8		T13	46
valid_sources[0x40]	10168	1			T2	3		T4	4		T5	3
valid_sources[0x41]	11625	1			T4	6		T5	5		T11	7
valid_sources[0x42]	11583	1			T4	13		T5	2		T11	12
valid_sources[0x43]	10450	1			T4	7		T5	1		T11	9
valid_sources[0x44]	9940	1			T4	12		T5	1		T11	12
valid_sources[0x45]	10097	1			T5	2		T11	6		T13	47
valid_sources[0x46]	10234	1			T4	7		T5	1		T11	13
valid_sources[0x47]	75005	1			T5	1		T11	13		T13	45
valid_sources[0x48]	68147	1			T4	2		T11	12		T13	26
valid_sources[0x49]	11394	1			T4	7		T11	8		T13	38
valid_sources[0x4a]	24051	1			T4	9		T11	11		T13	50
valid_sources[0x4b]	14586	1			T4	16		T5	1		T11	6
valid_sources[0x4c]	26645	1			T4	3		T11	12		T12	1
valid_sources[0x4d]	66463	1			T4	17		T5	2		T11	10
valid_sources[0x4e]	10599	1			T4	11		T5	2		T11	5
valid_sources[0x4f]	19251	1			T5	2		T11	11		T13	61
valid_sources[0x50]	9930	1			T4	8		T11	6		T13	34
valid_sources[0x51]	10462	1			T4	21		T5	1		T11	9
valid_sources[0x52]	9859	1			T4	1		T5	3		T11	5
valid_sources[0x53]	15504	1			T2	20		T4	13		T5	1
valid_sources[0x54]	13407	1			T4	8		T5	1		T11	14
valid_sources[0x55]	10108	1			T4	1		T5	1		T11	12
valid_sources[0x56]	72006	1			T4	21		T11	8		T13	42
valid_sources[0x57]	10347	1			T4	8		T11	19		T13	42
valid_sources[0x58]	11948	1			T4	4		T5	1		T11	6
valid_sources[0x59]	11357	1			T4	1		T5	1		T11	6
valid_sources[0x5a]	9926	1			T4	17		T11	4		T13	48
valid_sources[0x5b]	12046	1			T4	8		T11	11		T13	44
valid_sources[0x5c]	11523	1			T4	31		T5	3		T11	10
valid_sources[0x5d]	11427	1			T4	13		T5	1		T11	15
valid_sources[0x5e]	10027	1			T4	10		T11	10		T13	42
valid_sources[0x5f]	9750	1			T4	7		T5	3		T11	6
valid_sources[0x60]	11477	1			T4	8		T5	2		T11	15
valid_sources[0x61]	16007	1			T4	6		T5	3		T11	7
valid_sources[0x62]	10171	1			T4	13		T5	1		T11	8
valid_sources[0x63]	10942	1			T4	11		T11	15		T13	65
valid_sources[0x64]	10230	1			T4	16		T5	2		T11	13
valid_sources[0x65]	28110	1			T4	2		T5	1		T11	20
valid_sources[0x66]	10318	1			T4	29		T5	1		T11	14
valid_sources[0x67]	14900	1			T4	19		T5	1		T11	18
valid_sources[0x68]	87372	1			T4	30		T5	1		T11	12
valid_sources[0x69]	9938	1			T4	5		T11	10		T13	36
valid_sources[0x6a]	10840	1			T4	7		T5	2		T11	13
valid_sources[0x6b]	13368	1			T4	3		T5	2		T11	11
valid_sources[0x6c]	10462	1			T4	5		T5	2		T11	8
valid_sources[0x6d]	10510	1			T4	13		T5	1		T11	12
valid_sources[0x6e]	12421	1			T4	12		T5	3		T11	8
valid_sources[0x6f]	11391	1			T4	11		T11	13		T13	61
valid_sources[0x70]	10271	1			T4	24		T5	2		T11	12
valid_sources[0x71]	10265	1			T4	29		T5	4		T11	10
valid_sources[0x72]	10228	1			T4	8		T5	3		T11	7
valid_sources[0x73]	10547	1			T4	18		T5	3		T11	13
valid_sources[0x74]	10053	1			T4	5		T5	1		T11	13
valid_sources[0x75]	9816	1			T4	9		T5	2		T11	15
valid_sources[0x76]	10366	1			T4	4		T11	14		T13	62
valid_sources[0x77]	10287	1			T4	7		T5	1		T11	16
valid_sources[0x78]	127769	1			T4	18		T5	1		T11	16
valid_sources[0x79]	10557	1			T4	7		T5	2		T11	17
valid_sources[0x7a]	10441	1			T4	5		T5	3		T11	10
valid_sources[0x7b]	10355	1			T4	16		T5	2		T11	13
valid_sources[0x7c]	10077	1			T4	11		T11	7		T13	46
valid_sources[0x7d]	9995	1			T4	14		T11	9		T13	82
valid_sources[0x7e]	10467	1			T11	5		T13	60		T14	4
valid_sources[0x7f]	18701	1			T4	2		T5	1		T11	18
valid_sources[0x80]	10229	1			T4	8		T5	2		T11	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1692938

1

T1

2

T4

866

T5

91

values[0x0]

all_enables

biggest_size

153574

1

T1

5

T2

10

T4

314

values[0x1]

all_enables

biggest_size

152606

1

T1

7

T2

2

T4

321