Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	113978813	15108	0	0
claim_transition_if_regwen_rd_A	113978813	1592	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113978813	15108	0	0
T8	42414	0	0	0
T33	45990	0	0	0
T34	8005	0	0	0
T35	215639	0	0	0
T36	675808	0	0	0
T37	36726	0	0	0
T56	0	12	0	0
T57	0	6	0	0
T68	265941	15	0	0
T69	5704	0	0	0
T70	0	6	0	0
T94	0	1	0	0
T100	195363	0	0	0
T104	0	2	0	0
T113	0	3	0	0
T131	0	22	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	34632	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113978813	1592	0	0
T57	322955	0	0	0
T104	199686	7	0	0
T105	18777	0	0	0
T106	6516	0	0	0
T107	14601	0	0	0
T108	38791	0	0	0
T109	13476	0	0	0
T110	7743	0	0	0
T111	6100	0	0	0
T112	3762	0	0	0
T134	0	54	0	0
T135	0	3	0	0
T154	0	6	0	0
T173	0	4	0	0
T174	0	7	0	0
T175	0	3	0	0
T176	0	10	0	0
T177	0	14	0	0
T178	0	432	0	0