Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1408234	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1610270

1

T1

9

T2

11

T3

741

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2700875	1			T2	5		T3	764		T4	766
values[0x0]	158276	1			T1	16		T2	8		T3	212
values[0x1]	159353	1			T1	22		T2	7		T3	220

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1118191	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1900313

1

T1

15

T2

13

T3

845

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11518	1			T3	12		T4	4		T5	1
valid_sources[0x01]	10218	1			T3	4		T4	4		T5	2
valid_sources[0x02]	9537	1			T4	7		T12	4		T14	2
valid_sources[0x03]	10918	1			T3	10		T4	3		T5	2
valid_sources[0x04]	10963	1			T3	3		T4	1		T5	1
valid_sources[0x05]	10520	1			T3	11		T4	3		T5	6
valid_sources[0x06]	40108	1			T3	1		T4	6		T12	12
valid_sources[0x07]	10083	1			T4	5		T12	9		T14	4
valid_sources[0x08]	12322	1			T3	2		T4	6		T5	3
valid_sources[0x09]	12619	1			T4	9		T12	2		T14	6
valid_sources[0x0a]	11589	1			T3	7		T4	8		T5	3
valid_sources[0x0b]	74591	1			T3	3		T4	3		T5	5
valid_sources[0x0c]	9665	1			T3	2		T4	9		T12	11
valid_sources[0x0d]	9729	1			T4	6		T12	9		T14	3
valid_sources[0x0e]	10162	1			T4	7		T5	2		T12	13
valid_sources[0x0f]	10134	1			T4	4		T5	2		T12	6
valid_sources[0x10]	9776	1			T4	2		T5	4		T12	11
valid_sources[0x11]	9830	1			T4	7		T5	1		T12	8
valid_sources[0x12]	9748	1			T3	2		T4	9		T12	3
valid_sources[0x13]	9683	1			T4	3		T12	7		T14	6
valid_sources[0x14]	11996	1			T4	8		T5	5		T12	8
valid_sources[0x15]	10148	1			T4	2		T5	1		T12	19
valid_sources[0x16]	9961	1			T3	2		T4	4		T12	6
valid_sources[0x17]	11339	1			T3	5		T4	4		T12	16
valid_sources[0x18]	10102	1			T3	5		T4	5		T12	15
valid_sources[0x19]	9407	1			T4	6		T5	1		T12	5
valid_sources[0x1a]	10363	1			T3	4		T4	1		T12	12
valid_sources[0x1b]	9669	1			T4	6		T5	3		T12	3
valid_sources[0x1c]	12240	1			T3	2		T4	4		T5	1
valid_sources[0x1d]	9970	1			T3	1		T4	3		T12	5
valid_sources[0x1e]	12262	1			T1	1		T4	8		T5	2
valid_sources[0x1f]	17954	1			T3	4		T4	4		T12	9
valid_sources[0x20]	10135	1			T4	9		T5	1		T12	11
valid_sources[0x21]	9660	1			T3	4		T4	8		T5	3
valid_sources[0x22]	10039	1			T4	4		T5	4		T12	9
valid_sources[0x23]	9616	1			T3	36		T4	3		T5	6
valid_sources[0x24]	11279	1			T4	3		T12	19		T14	1
valid_sources[0x25]	9608	1			T3	6		T4	3		T5	1
valid_sources[0x26]	9641	1			T3	6		T4	10		T12	12
valid_sources[0x27]	11257	1			T3	10		T4	7		T5	4
valid_sources[0x28]	11243	1			T3	25		T4	4		T5	2
valid_sources[0x29]	10181	1			T4	2		T12	3		T14	8
valid_sources[0x2a]	9738	1			T4	5		T5	2		T12	5
valid_sources[0x2b]	11231	1			T4	4		T12	7		T14	4
valid_sources[0x2c]	9581	1			T1	1		T3	3		T4	6
valid_sources[0x2d]	10016	1			T3	8		T4	3		T12	8
valid_sources[0x2e]	9884	1			T4	7		T5	5		T12	13
valid_sources[0x2f]	12300	1			T1	2		T4	3		T5	7
valid_sources[0x30]	10269	1			T3	1		T4	8		T5	1
valid_sources[0x31]	11138	1			T3	2		T4	8		T12	18
valid_sources[0x32]	12310	1			T3	1		T4	5		T5	4
valid_sources[0x33]	10045	1			T5	2		T12	9		T14	5
valid_sources[0x34]	10199	1			T3	1		T4	10		T12	17
valid_sources[0x35]	10024	1			T3	1		T4	9		T5	1
valid_sources[0x36]	9547	1			T3	7		T4	9		T5	2
valid_sources[0x37]	9970	1			T3	5		T4	6		T12	16
valid_sources[0x38]	9824	1			T4	6		T12	5		T14	6
valid_sources[0x39]	9737	1			T3	3		T4	2		T12	5
valid_sources[0x3a]	11297	1			T12	12		T14	3		T15	3
valid_sources[0x3b]	9862	1			T3	5		T4	10		T12	20
valid_sources[0x3c]	10177	1			T3	34		T4	9		T5	2
valid_sources[0x3d]	10697	1			T4	3		T5	6		T12	9
valid_sources[0x3e]	9820	1			T1	1		T4	7		T5	1
valid_sources[0x3f]	9555	1			T4	4		T12	10		T14	6
valid_sources[0x40]	9817	1			T3	15		T4	2		T12	11
valid_sources[0x41]	9679	1			T3	8		T4	2		T5	3
valid_sources[0x42]	11261	1			T4	10		T12	6		T14	3
valid_sources[0x43]	10650	1			T4	5		T12	7		T14	3
valid_sources[0x44]	40289	1			T4	2		T12	5		T14	4
valid_sources[0x45]	9889	1			T1	1		T4	3		T5	2
valid_sources[0x46]	10024	1			T4	6		T5	1		T12	11
valid_sources[0x47]	9654	1			T3	10		T4	7		T5	2
valid_sources[0x48]	10295	1			T3	1		T4	6		T12	9
valid_sources[0x49]	10161	1			T1	3		T4	4		T5	2
valid_sources[0x4a]	10269	1			T4	7		T5	1		T12	10
valid_sources[0x4b]	10222	1			T3	10		T4	4		T5	1
valid_sources[0x4c]	10328	1			T3	7		T4	8		T12	20
valid_sources[0x4d]	9567	1			T3	4		T4	6		T5	3
valid_sources[0x4e]	9877	1			T4	2		T12	8		T14	7
valid_sources[0x4f]	10989	1			T3	1		T4	3		T12	19
valid_sources[0x50]	9791	1			T4	6		T5	6		T12	8
valid_sources[0x51]	11008	1			T3	2		T4	10		T5	8
valid_sources[0x52]	11132	1			T3	1		T4	9		T12	14
valid_sources[0x53]	10159	1			T3	1		T4	6		T12	4
valid_sources[0x54]	10307	1			T3	4		T4	6		T5	4
valid_sources[0x55]	9673	1			T4	7		T5	2		T12	10
valid_sources[0x56]	9773	1			T4	1		T5	4		T12	20
valid_sources[0x57]	10147	1			T3	7		T4	7		T5	1
valid_sources[0x58]	10945	1			T4	7		T12	8		T14	4
valid_sources[0x59]	10000	1			T4	3		T12	6		T14	6
valid_sources[0x5a]	10445	1			T3	1		T4	3		T12	1
valid_sources[0x5b]	10890	1			T2	20		T3	5		T4	3
valid_sources[0x5c]	9846	1			T3	9		T4	1		T5	2
valid_sources[0x5d]	9722	1			T3	1		T4	6		T12	6
valid_sources[0x5e]	9815	1			T3	20		T4	1		T5	1
valid_sources[0x5f]	11988	1			T3	14		T4	8		T12	13
valid_sources[0x60]	9863	1			T4	3		T12	8		T14	2
valid_sources[0x61]	12808	1			T3	13		T4	6		T12	9
valid_sources[0x62]	11672	1			T3	9		T4	5		T5	4
valid_sources[0x63]	12915	1			T3	25		T4	7		T12	16
valid_sources[0x64]	9421	1			T4	10		T5	4		T12	7
valid_sources[0x65]	9215	1			T4	5		T5	3		T12	8
valid_sources[0x66]	10083	1			T4	4		T5	1		T12	6
valid_sources[0x67]	9867	1			T4	1		T5	3		T12	2
valid_sources[0x68]	10015	1			T1	1		T3	9		T4	5
valid_sources[0x69]	9919	1			T4	6		T5	2		T12	6
valid_sources[0x6a]	10064	1			T3	1		T4	4		T5	1
valid_sources[0x6b]	9529	1			T1	2		T3	8		T4	4
valid_sources[0x6c]	12007	1			T3	7		T4	3		T12	8
valid_sources[0x6d]	10076	1			T3	17		T4	6		T5	2
valid_sources[0x6e]	9955	1			T3	13		T4	10		T5	3
valid_sources[0x6f]	9924	1			T3	6		T4	4		T5	4
valid_sources[0x70]	80644	1			T4	9		T12	5		T14	5
valid_sources[0x71]	10244	1			T4	4		T5	1		T12	10
valid_sources[0x72]	12449	1			T3	28		T4	9		T5	2
valid_sources[0x73]	9540	1			T1	1		T3	11		T4	4
valid_sources[0x74]	11353	1			T4	7		T5	6		T12	4
valid_sources[0x75]	10309	1			T4	10		T5	2		T12	7
valid_sources[0x76]	10633	1			T3	7		T4	6		T5	2
valid_sources[0x77]	11486	1			T3	8		T4	6		T12	5
valid_sources[0x78]	10114	1			T3	2		T4	4		T5	5
valid_sources[0x79]	10388	1			T3	1		T4	6		T5	1
valid_sources[0x7a]	9776	1			T4	5		T5	5		T12	3
valid_sources[0x7b]	11406	1			T1	3		T3	6		T4	5
valid_sources[0x7c]	12184	1			T3	2		T5	5		T12	7
valid_sources[0x7d]	10297	1			T1	3		T4	1		T5	1
valid_sources[0x7e]	10043	1			T3	9		T4	8		T12	13
valid_sources[0x7f]	9979	1			T1	1		T3	3		T4	7
valid_sources[0x80]	9654	1			T4	2		T5	10		T12	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1337017

1

T2

1

T3

372

T4

376

values[0x0]

all_enables

biggest_size

137102

1

T1

5

T2

6

T3

183

values[0x1]

all_enables

biggest_size

136151

1

T1

4

T2

4

T3

186