Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	86287850	13184	0	0
claim_transition_if_regwen_rd_A	86287850	1196	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86287850	13184	0	0
T24	176029	1	0	0
T48	250699	11	0	0
T57	0	8	0	0
T58	65396	0	0	0
T59	71145	0	0	0
T77	3491	0	0	0
T96	0	2	0	0
T97	0	4	0	0
T111	31205	0	0	0
T154	0	2	0	0
T155	0	16	0	0
T156	0	7	0	0
T157	0	15	0	0
T158	0	9	0	0
T159	19330	0	0	0
T160	26053	0	0	0
T161	227400	0	0	0
T162	113779	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86287850	1196	0	0
T112	0	54	0	0
T115	0	12	0	0
T118	0	9	0	0
T124	0	16	0	0
T129	0	26	0	0
T163	180423	32	0	0
T164	0	7	0	0
T165	0	6	0	0
T166	0	19	0	0
T167	0	16	0	0
T168	34957	0	0	0
T169	6444	0	0	0
T170	3023	0	0	0
T171	122601	0	0	0
T172	1099	0	0	0
T173	22529	0	0	0
T174	568264	0	0	0
T175	81436	0	0	0
T176	392233	0	0	0