Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1519928	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1742790

1

T1

21

T2

1

T3

1350

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2919507	1			T1	26		T3	1546		T5	11
values[0x0]	171456	1			T1	4		T2	2		T3	343
values[0x1]	171755	1			T1	4		T2	4		T3	337

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1206686	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2056032

1

T1

27

T2

2

T3

1544

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10202	1			T3	2		T14	1		T16	2
valid_sources[0x01]	11909	1			T3	12		T6	14		T16	22
valid_sources[0x02]	10098	1			T3	11		T6	20		T14	8
valid_sources[0x03]	10564	1			T3	8		T14	2		T17	7
valid_sources[0x04]	12803	1			T3	9		T16	5		T17	10
valid_sources[0x05]	48261	1			T3	16		T11	1		T14	2
valid_sources[0x06]	11017	1			T3	6		T12	26		T14	1
valid_sources[0x07]	10150	1			T3	5		T12	2		T14	2
valid_sources[0x08]	11712	1			T3	13		T14	3		T16	1
valid_sources[0x09]	11323	1			T3	4		T12	8		T6	1
valid_sources[0x0a]	10274	1			T3	7		T14	3		T15	6
valid_sources[0x0b]	10663	1			T3	9		T14	2		T16	5
valid_sources[0x0c]	10435	1			T3	5		T12	13		T14	4
valid_sources[0x0d]	10146	1			T3	17		T14	3		T17	3
valid_sources[0x0e]	10206	1			T3	6		T14	4		T17	6
valid_sources[0x0f]	10159	1			T3	6		T11	1		T14	6
valid_sources[0x10]	11282	1			T3	3		T12	8		T14	3
valid_sources[0x11]	10813	1			T3	7		T11	1		T14	1
valid_sources[0x12]	11975	1			T3	7		T14	2		T15	33
valid_sources[0x13]	11834	1			T3	8		T14	3		T16	3
valid_sources[0x14]	10005	1			T3	5		T11	1		T12	2
valid_sources[0x15]	12744	1			T3	4		T6	10		T14	2
valid_sources[0x16]	9888	1			T3	8		T14	3		T16	1
valid_sources[0x17]	10438	1			T3	15		T14	5		T17	3
valid_sources[0x18]	10123	1			T3	10		T14	2		T16	5
valid_sources[0x19]	10145	1			T3	6		T14	5		T16	4
valid_sources[0x1a]	14369	1			T3	9		T14	3		T16	6
valid_sources[0x1b]	11233	1			T3	9		T14	3		T17	6
valid_sources[0x1c]	12334	1			T3	8		T14	1		T16	5
valid_sources[0x1d]	13861	1			T3	8		T12	2		T14	3
valid_sources[0x1e]	10229	1			T3	8		T14	2		T17	7
valid_sources[0x1f]	9969	1			T3	11		T11	1		T14	1
valid_sources[0x20]	10065	1			T3	10		T14	3		T16	14
valid_sources[0x21]	10557	1			T3	11		T14	2		T17	8
valid_sources[0x22]	10378	1			T3	10		T14	8		T15	19
valid_sources[0x23]	12527	1			T3	8		T11	1		T14	4
valid_sources[0x24]	11885	1			T3	6		T14	7		T16	18
valid_sources[0x25]	10058	1			T3	4		T14	5		T16	2
valid_sources[0x26]	14221	1			T3	8		T11	1		T14	3
valid_sources[0x27]	10001	1			T3	7		T12	6		T14	4
valid_sources[0x28]	10004	1			T3	11		T14	4		T16	6
valid_sources[0x29]	11233	1			T3	11		T14	4		T16	10
valid_sources[0x2a]	42254	1			T3	3		T14	1		T16	1
valid_sources[0x2b]	10386	1			T3	12		T14	3		T16	6
valid_sources[0x2c]	10782	1			T3	12		T11	1		T16	11
valid_sources[0x2d]	10260	1			T3	8		T5	7		T14	5
valid_sources[0x2e]	10319	1			T3	8		T15	192		T17	4
valid_sources[0x2f]	10270	1			T3	8		T14	2		T15	23
valid_sources[0x30]	10507	1			T3	6		T16	15		T17	10
valid_sources[0x31]	11781	1			T3	7		T14	2		T16	13
valid_sources[0x32]	12631	1			T3	6		T14	7		T16	1
valid_sources[0x33]	13059	1			T3	7		T14	3		T16	4
valid_sources[0x34]	10009	1			T3	6		T14	6		T16	2
valid_sources[0x35]	10759	1			T3	5		T14	2		T16	14
valid_sources[0x36]	10504	1			T3	7		T14	2		T16	2
valid_sources[0x37]	10002	1			T3	5		T14	2		T17	2
valid_sources[0x38]	10005	1			T3	9		T11	1		T6	21
valid_sources[0x39]	10029	1			T3	13		T14	2		T16	2
valid_sources[0x3a]	9918	1			T3	4		T17	6		T30	7
valid_sources[0x3b]	11739	1			T3	11		T11	1		T14	8
valid_sources[0x3c]	10562	1			T3	3		T14	2		T17	12
valid_sources[0x3d]	10591	1			T3	13		T14	1		T17	9
valid_sources[0x3e]	10474	1			T3	10		T14	3		T17	7
valid_sources[0x3f]	17018	1			T3	7		T14	3		T16	6
valid_sources[0x40]	11912	1			T3	8		T14	1		T15	132
valid_sources[0x41]	10428	1			T3	4		T14	4		T16	1
valid_sources[0x42]	13174	1			T3	7		T14	8		T17	5
valid_sources[0x43]	10171	1			T3	11		T12	21		T14	3
valid_sources[0x44]	10387	1			T3	13		T12	2		T14	1
valid_sources[0x45]	11398	1			T3	9		T14	1		T16	1
valid_sources[0x46]	10121	1			T3	7		T11	1		T15	2
valid_sources[0x47]	12670	1			T3	4		T14	1		T17	12
valid_sources[0x48]	10270	1			T3	10		T11	1		T14	3
valid_sources[0x49]	11764	1			T3	10		T14	2		T17	5
valid_sources[0x4a]	9718	1			T3	10		T11	1		T14	2
valid_sources[0x4b]	9916	1			T3	10		T17	6		T30	1
valid_sources[0x4c]	9896	1			T3	14		T6	1		T14	4
valid_sources[0x4d]	10395	1			T3	10		T14	4		T16	2
valid_sources[0x4e]	10113	1			T3	10		T14	1		T15	38
valid_sources[0x4f]	10059	1			T3	4		T14	2		T16	5
valid_sources[0x50]	10027	1			T3	12		T11	1		T12	15
valid_sources[0x51]	9952	1			T3	6		T14	1		T16	6
valid_sources[0x52]	9866	1			T3	11		T14	5		T16	8
valid_sources[0x53]	10284	1			T3	15		T14	5		T16	6
valid_sources[0x54]	11542	1			T3	6		T14	5		T17	9
valid_sources[0x55]	10525	1			T3	8		T14	5		T17	4
valid_sources[0x56]	10396	1			T3	7		T11	1		T14	5
valid_sources[0x57]	10002	1			T3	7		T14	1		T16	7
valid_sources[0x58]	9761	1			T3	12		T14	1		T16	5
valid_sources[0x59]	14144	1			T3	8		T14	2		T16	6
valid_sources[0x5a]	10088	1			T3	10		T14	2		T16	29
valid_sources[0x5b]	103132	1			T3	5		T14	2		T16	7
valid_sources[0x5c]	10048	1			T3	8		T14	1		T16	1
valid_sources[0x5d]	10236	1			T3	11		T12	8		T14	3
valid_sources[0x5e]	10264	1			T3	11		T14	3		T16	1
valid_sources[0x5f]	10155	1			T3	12		T11	1		T12	7
valid_sources[0x60]	10014	1			T3	12		T14	5		T16	4
valid_sources[0x61]	9982	1			T3	8		T14	6		T16	4
valid_sources[0x62]	10163	1			T3	8		T14	4		T17	8
valid_sources[0x63]	9760	1			T3	11		T17	5		T7	1
valid_sources[0x64]	12809	1			T3	9		T14	1		T16	2
valid_sources[0x65]	10555	1			T3	9		T11	1		T16	8
valid_sources[0x66]	10842	1			T3	5		T14	1		T16	7
valid_sources[0x67]	13123	1			T3	18		T6	11		T14	7
valid_sources[0x68]	17629	1			T3	8		T14	4		T16	1
valid_sources[0x69]	10250	1			T3	10		T14	2		T16	7
valid_sources[0x6a]	10006	1			T3	10		T14	4		T16	18
valid_sources[0x6b]	9720	1			T3	7		T14	1		T16	3
valid_sources[0x6c]	9861	1			T3	7		T11	2		T12	5
valid_sources[0x6d]	10101	1			T3	8		T14	1		T16	1
valid_sources[0x6e]	9882	1			T3	6		T14	3		T16	7
valid_sources[0x6f]	10602	1			T3	8		T14	3		T16	3
valid_sources[0x70]	11074	1			T3	13		T14	1		T17	6
valid_sources[0x71]	10422	1			T3	9		T14	4		T16	30
valid_sources[0x72]	10016	1			T3	5		T12	4		T14	3
valid_sources[0x73]	10157	1			T3	7		T14	7		T16	3
valid_sources[0x74]	10179	1			T3	11		T14	2		T16	4
valid_sources[0x75]	10034	1			T3	12		T14	5		T17	7
valid_sources[0x76]	10179	1			T3	5		T17	3		T30	6
valid_sources[0x77]	9567	1			T3	6		T16	9		T17	7
valid_sources[0x78]	10469	1			T3	9		T6	8		T14	2
valid_sources[0x79]	10095	1			T3	15		T14	2		T17	12
valid_sources[0x7a]	10138	1			T3	8		T14	5		T17	5
valid_sources[0x7b]	10271	1			T3	9		T11	1		T14	2
valid_sources[0x7c]	11159	1			T3	14		T12	24		T14	6
valid_sources[0x7d]	10213	1			T3	12		T12	2		T14	3
valid_sources[0x7e]	10054	1			T3	10		T14	1		T17	7
valid_sources[0x7f]	14952	1			T3	11		T14	5		T16	12
valid_sources[0x80]	10462	1			T3	2		T11	1		T14	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1446972

1

T1

14

T3

760

T5

4

values[0x0]

all_enables

biggest_size

148724

1

T1

4

T2

1

T3

295

values[0x1]

all_enables

biggest_size

147094

1

T1

3

T3

295

T10

2