Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	99836816	15322	0	0
claim_transition_if_regwen_rd_A	99836816	1614	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99836816	15322	0	0
T46	0	13	0	0
T83	78421	0	0	0
T84	598642	1	0	0
T99	633457	7	0	0
T105	0	2	0	0
T153	0	13	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	3	0	0
T157	0	3	0	0
T158	0	2	0	0
T159	27135	0	0	0
T160	30779	0	0	0
T161	1460	0	0	0
T162	28630	0	0	0
T163	8832	0	0	0
T164	4762	0	0	0
T165	34293	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99836816	1614	0	0
T26	38664	0	0	0
T84	598642	8	0	0
T116	0	37	0	0
T118	0	5	0	0
T119	0	8	0	0
T122	0	2	0	0
T156	0	7	0	0
T166	0	7	0	0
T167	0	3	0	0
T168	0	4	0	0
T169	0	13	0	0
T170	1186	0	0	0
T171	133379	0	0	0
T172	870	0	0	0
T173	23428	0	0	0
T174	173960	0	0	0
T175	25696	0	0	0
T176	17465	0	0	0
T177	20748	0	0	0