Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1843105	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2060336

1

T2

67285

T7

301

T8

620

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3565498	1			T2	127575		T7	423		T8	447
values[0x0]	168829	1			T2	2211		T7	56		T8	228
values[0x1]	169114	1			T2	2187		T7	56		T8	212

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1465902	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2437539

1

T2

80339

T7

350

T8

672

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10756	1			T2	496		T9	12		T10	6
valid_sources[0x01]	12253	1			T2	553		T7	3		T9	4
valid_sources[0x02]	10484	1			T2	477		T7	16		T9	6
valid_sources[0x03]	10939	1			T2	546		T9	7		T10	1
valid_sources[0x04]	14664	1			T2	521		T9	5		T10	4
valid_sources[0x05]	234841	1			T2	575		T9	1		T10	2
valid_sources[0x06]	10939	1			T2	513		T10	6		T12	12
valid_sources[0x07]	11339	1			T2	527		T7	2		T9	8
valid_sources[0x08]	11425	1			T2	502		T7	10		T9	2
valid_sources[0x09]	11309	1			T2	549		T9	5		T10	1
valid_sources[0x0a]	10802	1			T2	514		T9	12		T10	1
valid_sources[0x0b]	11068	1			T2	521		T7	5		T9	4
valid_sources[0x0c]	10675	1			T2	499		T9	11		T12	16
valid_sources[0x0d]	11022	1			T2	536		T7	3		T9	4
valid_sources[0x0e]	10897	1			T2	537		T7	5		T9	5
valid_sources[0x0f]	11858	1			T2	533		T7	1		T9	12
valid_sources[0x10]	10638	1			T2	527		T7	4		T9	9
valid_sources[0x11]	11383	1			T2	497		T7	3		T9	4
valid_sources[0x12]	11013	1			T2	517		T7	1		T9	12
valid_sources[0x13]	11706	1			T2	513		T7	2		T9	3
valid_sources[0x14]	11318	1			T2	509		T9	3		T10	3
valid_sources[0x15]	10783	1			T2	526		T9	5		T10	6
valid_sources[0x16]	10469	1			T2	537		T7	9		T9	12
valid_sources[0x17]	11246	1			T2	555		T7	2		T9	8
valid_sources[0x18]	11346	1			T2	525		T9	8		T10	7
valid_sources[0x19]	11004	1			T2	506		T9	6		T10	2
valid_sources[0x1a]	11844	1			T2	514		T7	3		T9	4
valid_sources[0x1b]	12151	1			T2	509		T7	1		T9	7
valid_sources[0x1c]	11510	1			T2	526		T7	2		T9	1
valid_sources[0x1d]	11692	1			T2	524		T9	9		T10	8
valid_sources[0x1e]	13588	1			T2	537		T9	10		T10	6
valid_sources[0x1f]	13216	1			T2	494		T7	4		T9	11
valid_sources[0x20]	10912	1			T2	479		T7	8		T9	13
valid_sources[0x21]	11344	1			T2	514		T9	5		T10	2
valid_sources[0x22]	11130	1			T2	497		T7	1		T9	13
valid_sources[0x23]	11439	1			T2	522		T7	8		T9	5
valid_sources[0x24]	13794	1			T2	519		T9	5		T10	4
valid_sources[0x25]	10493	1			T2	510		T7	5		T9	10
valid_sources[0x26]	10945	1			T2	532		T9	3		T10	4
valid_sources[0x27]	12530	1			T2	497		T9	5		T10	4
valid_sources[0x28]	13629	1			T2	553		T9	8		T10	5
valid_sources[0x29]	11055	1			T2	475		T7	3		T9	16
valid_sources[0x2a]	12702	1			T2	512		T9	8		T10	3
valid_sources[0x2b]	11814	1			T2	508		T7	4		T9	1
valid_sources[0x2c]	12638	1			T2	489		T9	4		T10	1
valid_sources[0x2d]	23180	1			T2	472		T9	5		T10	5
valid_sources[0x2e]	14999	1			T2	559		T7	1		T9	9
valid_sources[0x2f]	11266	1			T2	573		T7	2		T9	5
valid_sources[0x30]	10957	1			T2	514		T9	4		T10	9
valid_sources[0x31]	10669	1			T2	535		T7	2		T9	6
valid_sources[0x32]	10952	1			T2	515		T7	1		T9	8
valid_sources[0x33]	30548	1			T2	511		T7	4		T9	5
valid_sources[0x34]	11564	1			T2	486		T7	1		T9	8
valid_sources[0x35]	12911	1			T2	491		T7	2		T9	8
valid_sources[0x36]	10780	1			T2	544		T9	3		T10	4
valid_sources[0x37]	10673	1			T2	545		T7	1		T9	5
valid_sources[0x38]	11061	1			T2	514		T9	14		T10	4
valid_sources[0x39]	11073	1			T2	502		T9	10		T10	2
valid_sources[0x3a]	20962	1			T2	529		T7	1		T9	5
valid_sources[0x3b]	12403	1			T2	527		T7	8		T9	9
valid_sources[0x3c]	28945	1			T2	546		T7	1		T9	8
valid_sources[0x3d]	11157	1			T2	586		T7	2		T9	5
valid_sources[0x3e]	10978	1			T2	518		T9	7		T10	3
valid_sources[0x3f]	11085	1			T2	506		T7	2		T9	3
valid_sources[0x40]	11114	1			T2	494		T7	4		T9	13
valid_sources[0x41]	11034	1			T2	530		T7	2		T9	11
valid_sources[0x42]	10912	1			T2	502		T9	1		T10	5
valid_sources[0x43]	11111	1			T2	515		T9	10		T10	8
valid_sources[0x44]	38254	1			T2	528		T7	2		T9	7
valid_sources[0x45]	11030	1			T2	479		T7	4		T9	7
valid_sources[0x46]	10814	1			T2	577		T9	5		T10	3
valid_sources[0x47]	11083	1			T2	511		T7	6		T9	2
valid_sources[0x48]	41756	1			T2	507		T9	6		T10	7
valid_sources[0x49]	12226	1			T2	492		T7	3		T9	7
valid_sources[0x4a]	11281	1			T2	583		T7	1		T9	5
valid_sources[0x4b]	11346	1			T2	534		T7	3		T9	4
valid_sources[0x4c]	11956	1			T2	540		T7	1		T9	9
valid_sources[0x4d]	11205	1			T2	469		T7	5		T9	3
valid_sources[0x4e]	11212	1			T2	494		T7	2		T9	12
valid_sources[0x4f]	11402	1			T2	510		T7	4		T9	3
valid_sources[0x50]	10825	1			T2	501		T9	10		T10	6
valid_sources[0x51]	11367	1			T2	513		T7	2		T9	8
valid_sources[0x52]	11484	1			T2	501		T9	6		T12	15
valid_sources[0x53]	24413	1			T2	502		T9	5		T10	1
valid_sources[0x54]	16940	1			T2	508		T7	2		T9	4
valid_sources[0x55]	14147	1			T2	532		T7	1		T9	4
valid_sources[0x56]	11005	1			T2	508		T7	1		T9	4
valid_sources[0x57]	10569	1			T2	494		T9	10		T10	1
valid_sources[0x58]	11369	1			T2	492		T7	1		T9	12
valid_sources[0x59]	11541	1			T2	522		T9	3		T10	6
valid_sources[0x5a]	11369	1			T2	482		T7	1		T9	6
valid_sources[0x5b]	11382	1			T2	477		T7	3		T9	4
valid_sources[0x5c]	97830	1			T2	507		T7	1		T9	10
valid_sources[0x5d]	11348	1			T2	506		T9	6		T10	5
valid_sources[0x5e]	10977	1			T2	522		T9	4		T12	15
valid_sources[0x5f]	11566	1			T2	501		T7	4		T9	9
valid_sources[0x60]	11158	1			T2	483		T7	4		T9	5
valid_sources[0x61]	11460	1			T2	524		T7	1		T9	6
valid_sources[0x62]	11571	1			T2	525		T9	7		T10	1
valid_sources[0x63]	12551	1			T2	512		T7	1		T9	11
valid_sources[0x64]	39747	1			T2	497		T9	6		T10	4
valid_sources[0x65]	10608	1			T2	515		T7	4		T9	8
valid_sources[0x66]	12438	1			T2	541		T7	6		T9	8
valid_sources[0x67]	10943	1			T2	503		T7	3		T9	3
valid_sources[0x68]	12654	1			T2	516		T9	4		T10	7
valid_sources[0x69]	11701	1			T2	487		T9	4		T12	16
valid_sources[0x6a]	39131	1			T2	543		T7	4		T9	5
valid_sources[0x6b]	10942	1			T2	526		T9	4		T10	2
valid_sources[0x6c]	12657	1			T2	532		T7	2		T9	4
valid_sources[0x6d]	11026	1			T2	521		T7	3		T9	7
valid_sources[0x6e]	11154	1			T2	535		T9	3		T10	4
valid_sources[0x6f]	13265	1			T2	506		T7	1		T9	10
valid_sources[0x70]	10927	1			T2	465		T9	6		T10	3
valid_sources[0x71]	11361	1			T2	521		T7	11		T9	9
valid_sources[0x72]	76824	1			T2	548		T7	1		T9	7
valid_sources[0x73]	10936	1			T2	529		T7	8		T9	3
valid_sources[0x74]	11115	1			T2	501		T7	1		T9	7
valid_sources[0x75]	10937	1			T2	500		T7	4		T9	9
valid_sources[0x76]	10962	1			T2	538		T9	8		T10	1
valid_sources[0x77]	14479	1			T2	509		T9	7		T10	5
valid_sources[0x78]	12939	1			T2	485		T7	4		T9	4
valid_sources[0x79]	11461	1			T2	465		T9	4		T10	14
valid_sources[0x7a]	11517	1			T2	497		T7	2		T9	7
valid_sources[0x7b]	13504	1			T2	499		T9	7		T12	20
valid_sources[0x7c]	13058	1			T2	517		T7	3		T9	6
valid_sources[0x7d]	12550	1			T2	526		T7	10		T9	7
valid_sources[0x7e]	11350	1			T2	533		T7	9		T9	4
valid_sources[0x7f]	14575	1			T2	523		T7	1		T9	8
valid_sources[0x80]	11093	1			T2	550		T9	2		T10	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1769162

1

T2

63490

T7

206

T8

235

values[0x0]

all_enables

biggest_size

146320

1

T2

1909

T7

50

T8

195

values[0x1]

all_enables

biggest_size

144854

1

T2

1886

T7

45

T8

190