Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	102620971	13384	0	0
claim_transition_if_regwen_rd_A	102620971	1486	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102620971	13384	0	0
T2	261439	7	0	0
T3	49937	0	0	0
T7	3385	0	0	0
T8	21379	0	0	0
T9	24641	0	0	0
T10	16984	0	0	0
T11	1479	0	0	0
T12	48320	0	0	0
T13	24347	0	0	0
T14	20721	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T54	0	1	0	0
T106	0	4	0	0
T114	0	17	0	0
T152	0	1	0	0
T153	0	7	0	0
T154	0	6	0	0
T155	0	7	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102620971	1486	0	0
T41	314129	19	0	0
T43	1324	0	0	0
T54	0	6	0	0
T62	40818	0	0	0
T66	4478	0	0	0
T71	21416	0	0	0
T74	1339	0	0	0
T118	0	11	0	0
T119	0	27	0	0
T124	0	33	0	0
T152	237313	0	0	0
T156	0	11	0	0
T157	0	12	0	0
T158	0	42	0	0
T159	0	28	0	0
T160	0	7	0	0
T161	940	0	0	0
T162	866	0	0	0
T163	15144	0	0	0