Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2201820	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2425874

1

T1

302

T2

41

T3

212

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4267321	1			T1	254		T2	158		T3	195
values[0x0]	179235	1			T1	109		T3	82		T9	7
values[0x1]	181138	1			T1	107		T3	89		T9	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1751036	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2876658

1

T1

337

T2

67

T3

249

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13631	1			T10	1		T5	220		T12	1
valid_sources[0x01]	14344	1			T5	196		T12	1		T13	11
valid_sources[0x02]	14739	1			T1	1		T5	215		T13	1
valid_sources[0x03]	14254	1			T1	2		T11	3		T5	141
valid_sources[0x04]	13243	1			T1	3		T10	1		T5	143
valid_sources[0x05]	13678	1			T10	3		T5	189		T13	6
valid_sources[0x06]	20087	1			T1	2		T3	9		T9	1
valid_sources[0x07]	13992	1			T1	4		T9	1		T10	3
valid_sources[0x08]	13808	1			T1	3		T11	5		T5	233
valid_sources[0x09]	15709	1			T1	3		T10	1		T5	191
valid_sources[0x0a]	13490	1			T1	1		T10	1		T5	204
valid_sources[0x0b]	13647	1			T1	1		T3	8		T5	220
valid_sources[0x0c]	15658	1			T2	9		T5	150		T12	1
valid_sources[0x0d]	14874	1			T10	2		T5	190		T13	3
valid_sources[0x0e]	14572	1			T1	1		T10	1		T5	264
valid_sources[0x0f]	13978	1			T1	6		T10	2		T11	6
valid_sources[0x10]	14003	1			T10	1		T5	240		T13	4
valid_sources[0x11]	13865	1			T2	3		T11	5		T5	178
valid_sources[0x12]	66663	1			T10	2		T5	147		T12	1
valid_sources[0x13]	13893	1			T3	1		T5	240		T13	3
valid_sources[0x14]	298867	1			T1	1		T2	1		T10	5
valid_sources[0x15]	14007	1			T1	1		T5	227		T12	1
valid_sources[0x16]	14114	1			T1	1		T5	172		T14	16
valid_sources[0x17]	14371	1			T1	1		T10	2		T5	159
valid_sources[0x18]	13593	1			T1	1		T2	6		T3	5
valid_sources[0x19]	13413	1			T1	3		T5	188		T12	1
valid_sources[0x1a]	13508	1			T10	3		T5	236		T12	3
valid_sources[0x1b]	13659	1			T10	2		T5	168		T12	1
valid_sources[0x1c]	14129	1			T1	2		T3	2		T5	151
valid_sources[0x1d]	14768	1			T1	5		T10	1		T5	176
valid_sources[0x1e]	13877	1			T1	1		T5	172		T12	1
valid_sources[0x1f]	14643	1			T1	1		T10	4		T5	174
valid_sources[0x20]	16132	1			T1	2		T5	165		T13	4
valid_sources[0x21]	13753	1			T1	2		T2	1		T10	2
valid_sources[0x22]	47386	1			T1	2		T2	1		T11	3
valid_sources[0x23]	30944	1			T10	2		T5	165		T12	1
valid_sources[0x24]	14391	1			T1	1		T10	1		T5	203
valid_sources[0x25]	14141	1			T5	200		T13	2		T14	3
valid_sources[0x26]	15662	1			T1	2		T11	4		T5	208
valid_sources[0x27]	23018	1			T10	4		T5	175		T12	1
valid_sources[0x28]	13521	1			T1	4		T10	3		T5	207
valid_sources[0x29]	15673	1			T1	4		T5	197		T12	2
valid_sources[0x2a]	13658	1			T1	1		T10	2		T5	208
valid_sources[0x2b]	14218	1			T1	1		T10	1		T5	211
valid_sources[0x2c]	74753	1			T1	1		T3	48		T5	129
valid_sources[0x2d]	13712	1			T1	5		T10	2		T11	18
valid_sources[0x2e]	14248	1			T1	3		T3	40		T10	3
valid_sources[0x2f]	14306	1			T1	2		T10	2		T5	202
valid_sources[0x30]	13087	1			T1	3		T3	5		T10	4
valid_sources[0x31]	13773	1			T1	3		T10	1		T5	233
valid_sources[0x32]	14469	1			T1	2		T2	1		T5	259
valid_sources[0x33]	13679	1			T2	5		T3	1		T10	4
valid_sources[0x34]	14268	1			T1	1		T3	3		T9	1
valid_sources[0x35]	14851	1			T1	2		T10	1		T5	226
valid_sources[0x36]	13522	1			T1	1		T10	1		T5	192
valid_sources[0x37]	14981	1			T10	1		T11	8		T5	161
valid_sources[0x38]	14555	1			T11	6		T5	195		T12	3
valid_sources[0x39]	14440	1			T1	2		T10	1		T11	1
valid_sources[0x3a]	13346	1			T1	2		T10	1		T11	13
valid_sources[0x3b]	13467	1			T2	7		T10	3		T11	4
valid_sources[0x3c]	18766	1			T1	1		T2	1		T5	184
valid_sources[0x3d]	14360	1			T1	5		T10	1		T5	233
valid_sources[0x3e]	13921	1			T1	1		T5	197		T12	1
valid_sources[0x3f]	15829	1			T1	2		T2	2		T3	5
valid_sources[0x40]	13669	1			T10	3		T5	146		T13	3
valid_sources[0x41]	13316	1			T1	4		T10	4		T5	170
valid_sources[0x42]	13425	1			T5	169		T14	1		T8	116
valid_sources[0x43]	13292	1			T1	2		T2	8		T10	2
valid_sources[0x44]	13464	1			T1	1		T2	9		T10	3
valid_sources[0x45]	14274	1			T1	2		T10	1		T5	270
valid_sources[0x46]	25135	1			T1	3		T2	2		T10	1
valid_sources[0x47]	13945	1			T10	1		T5	207		T12	1
valid_sources[0x48]	13936	1			T3	3		T5	193		T12	2
valid_sources[0x49]	13983	1			T10	2		T5	209		T13	1
valid_sources[0x4a]	103183	1			T1	3		T10	1		T11	12
valid_sources[0x4b]	14090	1			T1	1		T3	2		T10	1
valid_sources[0x4c]	13510	1			T1	1		T10	1		T5	238
valid_sources[0x4d]	13820	1			T1	3		T5	177		T12	1
valid_sources[0x4e]	13774	1			T1	3		T5	214		T12	2
valid_sources[0x4f]	18270	1			T10	3		T5	162		T13	4
valid_sources[0x50]	13862	1			T1	2		T3	45		T9	1
valid_sources[0x51]	14211	1			T1	5		T10	6		T11	8
valid_sources[0x52]	14807	1			T1	3		T2	5		T5	207
valid_sources[0x53]	13769	1			T2	5		T10	1		T11	7
valid_sources[0x54]	13991	1			T1	1		T2	3		T3	1
valid_sources[0x55]	14328	1			T1	2		T5	188		T12	1
valid_sources[0x56]	13350	1			T3	17		T11	2		T5	138
valid_sources[0x57]	13980	1			T1	1		T10	4		T5	184
valid_sources[0x58]	14596	1			T1	3		T10	3		T5	238
valid_sources[0x59]	14698	1			T11	4		T5	177		T12	1
valid_sources[0x5a]	15383	1			T1	1		T5	225		T13	3
valid_sources[0x5b]	14433	1			T1	2		T5	284		T13	3
valid_sources[0x5c]	13491	1			T1	3		T2	2		T5	210
valid_sources[0x5d]	13660	1			T1	1		T5	169		T13	3
valid_sources[0x5e]	14597	1			T5	241		T8	142		T62	18
valid_sources[0x5f]	13834	1			T1	2		T10	1		T5	171
valid_sources[0x60]	15608	1			T1	3		T10	1		T11	4
valid_sources[0x61]	13925	1			T10	1		T5	173		T12	1
valid_sources[0x62]	15511	1			T1	1		T9	1		T10	3
valid_sources[0x63]	13796	1			T10	1		T11	6		T5	204
valid_sources[0x64]	13947	1			T1	1		T10	2		T5	199
valid_sources[0x65]	13705	1			T1	2		T10	2		T11	1
valid_sources[0x66]	13594	1			T1	2		T10	4		T5	203
valid_sources[0x67]	15731	1			T5	178		T13	7		T8	112
valid_sources[0x68]	13520	1			T1	7		T10	6		T11	3
valid_sources[0x69]	13493	1			T10	4		T11	1		T5	218
valid_sources[0x6a]	13483	1			T1	1		T11	1		T5	261
valid_sources[0x6b]	14444	1			T2	5		T10	1		T5	202
valid_sources[0x6c]	15503	1			T1	1		T10	1		T5	193
valid_sources[0x6d]	23240	1			T1	3		T5	278		T13	6
valid_sources[0x6e]	13933	1			T1	3		T3	44		T10	2
valid_sources[0x6f]	14261	1			T2	6		T10	5		T5	177
valid_sources[0x70]	14034	1			T1	1		T10	2		T5	179
valid_sources[0x71]	13558	1			T10	2		T5	222		T12	2
valid_sources[0x72]	21825	1			T1	5		T10	1		T11	9
valid_sources[0x73]	14267	1			T1	3		T5	171		T12	2
valid_sources[0x74]	14115	1			T1	3		T10	4		T5	234
valid_sources[0x75]	13817	1			T1	3		T2	1		T10	5
valid_sources[0x76]	13645	1			T1	3		T5	148		T13	2
valid_sources[0x77]	13678	1			T1	1		T10	2		T5	168
valid_sources[0x78]	22947	1			T1	1		T2	2		T5	141
valid_sources[0x79]	13585	1			T1	1		T3	18		T10	3
valid_sources[0x7a]	13647	1			T1	1		T11	1		T5	280
valid_sources[0x7b]	13457	1			T1	3		T2	4		T5	197
valid_sources[0x7c]	14828	1			T1	3		T9	2		T5	150
valid_sources[0x7d]	13696	1			T2	1		T10	3		T5	238
valid_sources[0x7e]	13989	1			T1	3		T5	220		T12	2
valid_sources[0x7f]	13526	1			T1	2		T5	211		T12	1
valid_sources[0x80]	13749	1			T1	1		T10	1		T5	202

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2115650

1

T1

119

T2

41

T3

102

values[0x0]

all_enables

biggest_size

155274

1

T1

89

T3

56

T9

6

values[0x1]

all_enables

biggest_size

154950

1

T1

94

T3

54

T9

5