Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	108453544	14828	0	0
claim_transition_if_regwen_rd_A	108453544	1483	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108453544	14828	0	0
T6	22859	0	0	0
T7	70357	0	0	0
T15	295621	15	0	0
T16	40561	0	0	0
T17	229005	0	0	0
T18	176781	0	0	0
T19	306738	0	0	0
T28	1226	0	0	0
T31	0	14	0	0
T33	16968	0	0	0
T44	0	3	0	0
T63	6893	0	0	0
T66	0	7	0	0
T83	0	9	0	0
T84	0	12	0	0
T85	0	3	0	0
T102	0	16	0	0
T133	0	3	0	0
T134	0	1	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108453544	1483	0	0
T45	0	6	0	0
T99	0	4	0	0
T134	175149	3	0	0
T135	0	15	0	0
T136	0	3	0	0
T137	0	4	0	0
T138	0	6	0	0
T139	0	7	0	0
T140	0	7	0	0
T141	0	16	0	0
T142	2056	0	0	0
T143	24241	0	0	0
T144	778	0	0	0
T145	50543	0	0	0
T146	16437	0	0	0
T147	8920	0	0	0
T148	4946	0	0	0
T149	23082	0	0	0
T150	20793	0	0	0