Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1999718	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2213071

1

T1

4

T2

1119

T3

708

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3875537	1			T2	1000		T3	583		T4	8168
values[0x0]	168575	1			T1	6		T2	375		T3	274
values[0x1]	168677	1			T1	5		T2	353		T3	286

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1590249	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2622540

1

T1

4

T2

1271

T3

822

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12414	1			T2	5		T3	9		T12	3
valid_sources[0x01]	15364	1			T2	13		T3	7		T12	7
valid_sources[0x02]	13214	1			T2	13		T3	9		T12	5
valid_sources[0x03]	13223	1			T2	18		T3	9		T7	1
valid_sources[0x04]	13306	1			T1	1		T2	10		T12	8
valid_sources[0x05]	13424	1			T1	1		T2	7		T3	5
valid_sources[0x06]	13189	1			T2	9		T3	2		T12	6
valid_sources[0x07]	14531	1			T1	1		T2	1		T3	6
valid_sources[0x08]	14419	1			T2	13		T3	4		T16	1
valid_sources[0x09]	12939	1			T3	5		T12	6		T16	9
valid_sources[0x0a]	14382	1			T2	1		T3	2		T12	5
valid_sources[0x0b]	20188	1			T2	3		T3	7		T12	19
valid_sources[0x0c]	13809	1			T2	3		T3	4		T12	2
valid_sources[0x0d]	14036	1			T2	12		T3	1		T12	5
valid_sources[0x0e]	13055	1			T2	2		T3	3		T12	6
valid_sources[0x0f]	16750	1			T2	3		T3	3		T12	7
valid_sources[0x10]	12785	1			T2	3		T3	1		T12	2
valid_sources[0x11]	13448	1			T2	6		T3	10		T13	1
valid_sources[0x12]	13062	1			T2	10		T3	5		T12	1
valid_sources[0x13]	16231	1			T2	1		T3	3		T23	1
valid_sources[0x14]	12909	1			T1	2		T2	7		T3	6
valid_sources[0x15]	13009	1			T2	6		T3	7		T12	2
valid_sources[0x16]	13231	1			T2	6		T3	5		T12	1
valid_sources[0x17]	13269	1			T2	5		T3	1		T12	18
valid_sources[0x18]	13002	1			T2	7		T3	2		T16	1
valid_sources[0x19]	12914	1			T3	10		T16	3		T18	1
valid_sources[0x1a]	12819	1			T2	9		T3	1		T12	9
valid_sources[0x1b]	13373	1			T3	4		T12	19		T15	1
valid_sources[0x1c]	12751	1			T2	1		T3	2		T12	5
valid_sources[0x1d]	13753	1			T2	10		T3	9		T12	4
valid_sources[0x1e]	12881	1			T3	6		T23	1		T16	1
valid_sources[0x1f]	14575	1			T3	6		T12	11		T7	1
valid_sources[0x20]	15477	1			T2	6		T3	2		T12	7
valid_sources[0x21]	35921	1			T2	12		T3	3		T12	7
valid_sources[0x22]	13868	1			T2	8		T3	2		T12	2
valid_sources[0x23]	26099	1			T2	9		T3	3		T15	1
valid_sources[0x24]	13623	1			T2	9		T3	3		T12	2
valid_sources[0x25]	21143	1			T3	3		T12	17		T16	5
valid_sources[0x26]	14689	1			T2	2		T3	6		T7	1
valid_sources[0x27]	13243	1			T2	5		T3	6		T12	2
valid_sources[0x28]	12808	1			T2	17		T3	3		T12	4
valid_sources[0x29]	12896	1			T2	10		T3	4		T23	1
valid_sources[0x2a]	13473	1			T2	11		T3	2		T23	2
valid_sources[0x2b]	12940	1			T2	6		T3	2		T7	1
valid_sources[0x2c]	14020	1			T2	10		T3	2		T12	10
valid_sources[0x2d]	15474	1			T2	8		T3	3		T12	1
valid_sources[0x2e]	12788	1			T2	21		T3	4		T12	11
valid_sources[0x2f]	13251	1			T2	11		T3	11		T23	1
valid_sources[0x30]	12955	1			T2	5		T3	14		T12	3
valid_sources[0x31]	14920	1			T3	4		T16	1		T17	1
valid_sources[0x32]	12963	1			T2	4		T3	4		T12	1
valid_sources[0x33]	12725	1			T2	4		T3	7		T16	7
valid_sources[0x34]	13330	1			T3	5		T12	10		T16	4
valid_sources[0x35]	13221	1			T2	10		T3	2		T12	3
valid_sources[0x36]	12827	1			T2	9		T3	4		T12	1
valid_sources[0x37]	12649	1			T2	1		T3	2		T12	7
valid_sources[0x38]	19279	1			T3	8		T13	1		T16	4
valid_sources[0x39]	13041	1			T2	7		T3	4		T12	5
valid_sources[0x3a]	13537	1			T3	9		T12	8		T25	2
valid_sources[0x3b]	13616	1			T2	13		T3	4		T12	20
valid_sources[0x3c]	68761	1			T3	2		T12	7		T15	2
valid_sources[0x3d]	18746	1			T3	7		T7	1		T16	6
valid_sources[0x3e]	13392	1			T2	20		T3	2		T7	2
valid_sources[0x3f]	25991	1			T2	4		T3	8		T12	2
valid_sources[0x40]	14380	1			T2	2		T3	5		T12	1
valid_sources[0x41]	12512	1			T2	4		T12	4		T23	1
valid_sources[0x42]	13055	1			T3	3		T12	10		T16	4
valid_sources[0x43]	12701	1			T2	12		T3	5		T12	19
valid_sources[0x44]	18144	1			T2	2		T3	4		T17	1
valid_sources[0x45]	13254	1			T2	18		T3	2		T12	10
valid_sources[0x46]	13382	1			T2	3		T3	4		T12	1
valid_sources[0x47]	12573	1			T2	3		T3	5		T12	9
valid_sources[0x48]	13167	1			T2	7		T3	1		T12	3
valid_sources[0x49]	13231	1			T2	8		T3	6		T12	11
valid_sources[0x4a]	14522	1			T3	1		T7	3		T16	5
valid_sources[0x4b]	13277	1			T2	1		T12	2		T7	1
valid_sources[0x4c]	13096	1			T2	9		T3	1		T12	3
valid_sources[0x4d]	13078	1			T2	15		T3	3		T12	26
valid_sources[0x4e]	14459	1			T2	4		T3	5		T7	1
valid_sources[0x4f]	15053	1			T2	6		T3	13		T12	14
valid_sources[0x50]	13164	1			T2	14		T3	3		T12	8
valid_sources[0x51]	18247	1			T3	1		T15	1		T23	1
valid_sources[0x52]	13288	1			T2	4		T3	6		T17	1
valid_sources[0x53]	13447	1			T2	20		T3	5		T7	1
valid_sources[0x54]	12576	1			T2	4		T3	5		T12	9
valid_sources[0x55]	13094	1			T2	9		T3	6		T16	2
valid_sources[0x56]	13429	1			T3	5		T12	8		T16	5
valid_sources[0x57]	14006	1			T2	9		T12	8		T23	1
valid_sources[0x58]	12993	1			T2	2		T3	4		T7	1
valid_sources[0x59]	13054	1			T2	7		T3	6		T12	9
valid_sources[0x5a]	12790	1			T2	24		T3	2		T7	1
valid_sources[0x5b]	13282	1			T2	4		T3	7		T12	15
valid_sources[0x5c]	16899	1			T3	6		T15	1		T16	2
valid_sources[0x5d]	13417	1			T2	18		T3	4		T12	1
valid_sources[0x5e]	14730	1			T2	20		T3	5		T12	3
valid_sources[0x5f]	13000	1			T2	6		T3	4		T12	8
valid_sources[0x60]	13584	1			T2	2		T3	6		T25	1
valid_sources[0x61]	12764	1			T3	5		T12	1		T18	2
valid_sources[0x62]	23525	1			T2	34		T3	3		T7	1
valid_sources[0x63]	12694	1			T2	3		T3	2		T12	30
valid_sources[0x64]	14918	1			T1	1		T2	1		T3	3
valid_sources[0x65]	13003	1			T2	2		T3	7		T16	2
valid_sources[0x66]	12880	1			T2	17		T3	2		T12	6
valid_sources[0x67]	13002	1			T2	9		T3	3		T16	6
valid_sources[0x68]	13307	1			T2	7		T3	7		T12	15
valid_sources[0x69]	15452	1			T3	4		T16	5		T17	1
valid_sources[0x6a]	13223	1			T2	18		T3	7		T12	17
valid_sources[0x6b]	13227	1			T2	4		T3	5		T7	1
valid_sources[0x6c]	12927	1			T2	20		T3	5		T16	1
valid_sources[0x6d]	12973	1			T2	13		T3	6		T12	15
valid_sources[0x6e]	13061	1			T2	8		T3	3		T16	7
valid_sources[0x6f]	12546	1			T2	3		T3	1		T12	19
valid_sources[0x70]	12896	1			T2	3		T3	4		T12	5
valid_sources[0x71]	12891	1			T2	16		T3	5		T12	5
valid_sources[0x72]	14582	1			T2	4		T23	1		T16	2
valid_sources[0x73]	14028	1			T2	20		T3	6		T12	2
valid_sources[0x74]	14292	1			T2	7		T3	6		T12	11
valid_sources[0x75]	13655	1			T2	9		T3	3		T12	16
valid_sources[0x76]	13913	1			T2	3		T3	3		T12	3
valid_sources[0x77]	13135	1			T2	5		T3	8		T12	3
valid_sources[0x78]	13133	1			T3	6		T12	2		T16	1
valid_sources[0x79]	13583	1			T2	12		T3	6		T12	2
valid_sources[0x7a]	13695	1			T1	1		T3	9		T12	3
valid_sources[0x7b]	13395	1			T2	7		T3	1		T15	1
valid_sources[0x7c]	13140	1			T2	17		T3	5		T12	6
valid_sources[0x7d]	13551	1			T2	2		T3	4		T7	1
valid_sources[0x7e]	13326	1			T1	1		T2	3		T3	2
valid_sources[0x7f]	13637	1			T2	1		T3	1		T12	13
valid_sources[0x80]	13760	1			T2	2		T3	3		T12	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1922583

1

T2

499

T3

221

T4

4096

values[0x0]

all_enables

biggest_size

146253

1

T1

2

T2

327

T3

239

values[0x1]

all_enables

biggest_size

144235

1

T1

2

T2

293

T3

248