Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	115314891	15025	0	0
claim_transition_if_regwen_rd_A	115314891	1619	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115314891	15025	0	0
T20	194719	1	0	0
T21	3169	0	0	0
T22	15140	0	0	0
T27	152982	0	0	0
T42	33684	0	0	0
T43	0	3	0	0
T62	137703	0	0	0
T65	0	8	0	0
T66	2130	0	0	0
T91	144913	0	0	0
T92	0	1	0	0
T162	0	6	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	2	0	0
T166	0	1	0	0
T167	0	5	0	0
T168	2293	0	0	0
T169	34712	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115314891	1619	0	0
T20	194719	7	0	0
T21	3169	0	0	0
T22	15140	0	0	0
T27	152982	0	0	0
T42	33684	0	0	0
T62	137703	0	0	0
T66	2130	0	0	0
T91	144913	0	0	0
T126	0	93	0	0
T133	0	98	0	0
T137	0	7	0	0
T147	0	67	0	0
T150	0	30	0	0
T165	0	9	0	0
T167	0	6	0	0
T168	2293	0	0	0
T169	34712	0	0	0
T170	0	3	0	0
T171	0	17	0	0