Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1581792	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1800791

1

T1

151772

T2

2046

T8

96

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3036427	1			T1	287840		T2	2953		T8	91
values[0x0]	172684	1			T1	4913		T2	337		T8	33
values[0x1]	173472	1			T1	4972		T2	303		T8	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1256150	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2126433

1

T1

181528

T2

2368

T8

108

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11298	1			T1	1186		T9	8		T11	2
valid_sources[0x01]	13368	1			T1	1148		T9	1		T11	13
valid_sources[0x02]	11225	1			T1	1146		T5	47		T9	1
valid_sources[0x03]	11330	1			T1	1161		T11	17		T12	254
valid_sources[0x04]	12255	1			T1	1153		T9	2		T6	1
valid_sources[0x05]	11385	1			T1	1166		T6	1		T11	11
valid_sources[0x06]	11127	1			T1	1242		T6	1		T11	3
valid_sources[0x07]	11227	1			T1	1081		T9	2		T11	11
valid_sources[0x08]	11680	1			T1	1171		T6	1		T11	1
valid_sources[0x09]	11818	1			T1	1210		T6	5		T11	5
valid_sources[0x0a]	11198	1			T1	1182		T9	1		T6	12
valid_sources[0x0b]	10971	1			T1	1131		T9	2		T6	1
valid_sources[0x0c]	15108	1			T1	1125		T9	1		T6	2
valid_sources[0x0d]	11013	1			T1	1172		T9	1		T6	4
valid_sources[0x0e]	11044	1			T1	1140		T6	3		T11	1
valid_sources[0x0f]	12729	1			T1	1148		T11	9		T12	202
valid_sources[0x10]	12027	1			T1	1133		T11	11		T12	232
valid_sources[0x11]	11244	1			T1	1168		T9	4		T11	10
valid_sources[0x12]	12892	1			T1	1074		T11	4		T12	206
valid_sources[0x13]	12856	1			T1	1175		T12	234		T25	4
valid_sources[0x14]	15731	1			T1	1179		T4	56		T6	1
valid_sources[0x15]	12913	1			T1	1182		T4	73		T9	4
valid_sources[0x16]	11810	1			T1	1110		T5	8		T6	3
valid_sources[0x17]	11409	1			T1	1191		T6	7		T11	3
valid_sources[0x18]	12393	1			T1	1161		T4	22		T11	14
valid_sources[0x19]	63031	1			T1	1206		T11	6		T12	236
valid_sources[0x1a]	13870	1			T1	1173		T11	8		T12	208
valid_sources[0x1b]	45863	1			T1	1141		T6	5		T11	6
valid_sources[0x1c]	10558	1			T1	1058		T9	1		T11	11
valid_sources[0x1d]	12415	1			T1	1205		T9	4		T6	2
valid_sources[0x1e]	10559	1			T1	1221		T6	1		T12	228
valid_sources[0x1f]	11022	1			T1	1191		T9	8		T6	9
valid_sources[0x20]	11165	1			T1	1168		T9	1		T6	5
valid_sources[0x21]	10969	1			T1	1132		T9	2		T6	1
valid_sources[0x22]	14649	1			T1	1170		T6	1		T11	9
valid_sources[0x23]	10759	1			T1	1193		T9	3		T6	3
valid_sources[0x24]	10693	1			T1	1158		T4	7		T9	1
valid_sources[0x25]	11119	1			T1	1264		T6	2		T11	1
valid_sources[0x26]	26491	1			T1	1096		T11	7		T12	242
valid_sources[0x27]	11367	1			T1	1194		T9	3		T11	8
valid_sources[0x28]	11017	1			T1	1140		T4	47		T9	4
valid_sources[0x29]	11264	1			T1	1246		T6	4		T11	7
valid_sources[0x2a]	10878	1			T1	1158		T9	2		T6	4
valid_sources[0x2b]	26784	1			T1	1115		T9	2		T6	3
valid_sources[0x2c]	10641	1			T1	1156		T4	31		T6	1
valid_sources[0x2d]	10696	1			T1	1069		T9	2		T6	1
valid_sources[0x2e]	12403	1			T1	1182		T9	4		T6	1
valid_sources[0x2f]	10613	1			T1	1191		T9	3		T11	6
valid_sources[0x30]	11028	1			T1	1177		T9	3		T6	8
valid_sources[0x31]	10679	1			T1	1172		T9	3		T11	3
valid_sources[0x32]	12193	1			T1	1156		T11	7		T12	238
valid_sources[0x33]	11004	1			T1	1153		T4	4		T6	4
valid_sources[0x34]	11317	1			T1	1179		T5	3		T6	1
valid_sources[0x35]	12185	1			T1	1273		T11	5		T12	251
valid_sources[0x36]	11973	1			T1	1189		T9	3		T11	8
valid_sources[0x37]	10859	1			T1	1140		T9	4		T6	2
valid_sources[0x38]	10964	1			T1	1211		T9	2		T11	1
valid_sources[0x39]	11756	1			T1	1177		T11	5		T12	190
valid_sources[0x3a]	11332	1			T1	1150		T11	8		T12	238
valid_sources[0x3b]	10859	1			T1	1219		T9	2		T11	1
valid_sources[0x3c]	12209	1			T1	1191		T9	5		T11	3
valid_sources[0x3d]	11099	1			T1	1177		T11	9		T12	215
valid_sources[0x3e]	11837	1			T1	1212		T11	19		T12	241
valid_sources[0x3f]	12764	1			T1	1057		T9	5		T11	3
valid_sources[0x40]	14013	1			T1	1143		T11	8		T12	252
valid_sources[0x41]	11851	1			T1	1097		T9	2		T11	11
valid_sources[0x42]	11243	1			T1	1137		T9	1		T12	235
valid_sources[0x43]	12233	1			T1	1138		T11	1		T12	193
valid_sources[0x44]	12238	1			T1	1145		T6	14		T11	2
valid_sources[0x45]	12629	1			T1	1118		T4	2		T11	3
valid_sources[0x46]	11954	1			T1	1114		T6	5		T11	10
valid_sources[0x47]	13568	1			T1	1155		T9	3		T11	1
valid_sources[0x48]	11075	1			T1	1182		T11	10		T12	226
valid_sources[0x49]	11250	1			T1	1090		T11	10		T12	229
valid_sources[0x4a]	11834	1			T1	1190		T9	1		T11	8
valid_sources[0x4b]	11003	1			T1	1165		T4	11		T9	1
valid_sources[0x4c]	11273	1			T1	1131		T9	1		T6	2
valid_sources[0x4d]	12911	1			T1	1155		T9	4		T11	2
valid_sources[0x4e]	10857	1			T1	1228		T9	3		T11	8
valid_sources[0x4f]	11328	1			T1	1179		T9	2		T6	3
valid_sources[0x50]	10806	1			T1	1129		T9	1		T11	2
valid_sources[0x51]	11895	1			T1	1188		T11	5		T12	219
valid_sources[0x52]	10743	1			T1	1113		T9	3		T11	4
valid_sources[0x53]	10779	1			T1	1110		T9	2		T11	7
valid_sources[0x54]	10651	1			T1	1125		T9	1		T11	6
valid_sources[0x55]	10819	1			T1	1132		T9	3		T11	3
valid_sources[0x56]	11191	1			T1	1162		T6	3		T11	8
valid_sources[0x57]	11161	1			T1	1139		T4	1		T9	2
valid_sources[0x58]	11153	1			T1	1131		T11	2		T12	242
valid_sources[0x59]	11165	1			T1	1139		T11	6		T12	229
valid_sources[0x5a]	13670	1			T1	1217		T4	8		T9	4
valid_sources[0x5b]	11088	1			T1	1166		T9	2		T11	7
valid_sources[0x5c]	10881	1			T1	1147		T9	3		T6	1
valid_sources[0x5d]	11778	1			T1	1102		T5	11		T11	6
valid_sources[0x5e]	11059	1			T1	1153		T9	2		T6	1
valid_sources[0x5f]	12202	1			T1	1257		T11	5		T12	258
valid_sources[0x60]	13037	1			T1	1179		T11	4		T12	215
valid_sources[0x61]	10908	1			T1	1224		T4	19		T9	5
valid_sources[0x62]	18868	1			T1	1155		T9	8		T11	13
valid_sources[0x63]	10866	1			T1	1133		T11	10		T12	242
valid_sources[0x64]	13327	1			T1	1142		T11	5		T12	202
valid_sources[0x65]	12823	1			T1	1161		T4	11		T9	1
valid_sources[0x66]	14602	1			T1	1153		T4	51		T9	4
valid_sources[0x67]	10814	1			T1	1163		T9	1		T11	8
valid_sources[0x68]	10788	1			T1	1169		T11	9		T12	211
valid_sources[0x69]	10963	1			T1	1174		T6	6		T11	6
valid_sources[0x6a]	11115	1			T1	1157		T9	1		T6	2
valid_sources[0x6b]	15159	1			T1	1157		T9	8		T11	4
valid_sources[0x6c]	13004	1			T1	1165		T6	6		T11	11
valid_sources[0x6d]	11834	1			T1	1188		T6	3		T11	7
valid_sources[0x6e]	11957	1			T1	1207		T6	1		T11	4
valid_sources[0x6f]	10926	1			T1	1150		T8	163		T9	2
valid_sources[0x70]	49500	1			T1	1153		T11	4		T12	235
valid_sources[0x71]	14861	1			T1	1141		T11	2		T12	261
valid_sources[0x72]	10972	1			T1	1212		T9	2		T11	11
valid_sources[0x73]	11336	1			T1	1144		T9	1		T6	10
valid_sources[0x74]	12056	1			T1	1184		T9	3		T6	1
valid_sources[0x75]	11229	1			T1	1136		T9	7		T6	2
valid_sources[0x76]	10980	1			T1	1130		T11	9		T12	261
valid_sources[0x77]	10997	1			T1	1160		T9	1		T11	5
valid_sources[0x78]	11745	1			T1	1150		T9	5		T6	2
valid_sources[0x79]	12413	1			T1	1143		T11	9		T12	236
valid_sources[0x7a]	11038	1			T1	1197		T9	1		T6	4
valid_sources[0x7b]	12659	1			T1	1198		T11	2		T12	222
valid_sources[0x7c]	10776	1			T1	1176		T11	4		T12	297
valid_sources[0x7d]	11063	1			T1	1167		T9	1		T6	1
valid_sources[0x7e]	19436	1			T1	1182		T6	3		T11	7
valid_sources[0x7f]	11257	1			T1	1179		T9	2		T11	1
valid_sources[0x80]	10766	1			T1	1171		T9	1		T11	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1502883

1

T1

143211

T2

1492

T8

36

values[0x0]

all_enables

biggest_size

149568

1

T1

4273

T2

294

T8

27

values[0x1]

all_enables

biggest_size

148340

1

T1

4288

T2

260

T8

33