Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	107161696	13584	0	0
claim_transition_if_regwen_rd_A	107161696	1099	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107161696	13584	0	0
T1	385279	16	0	0
T2	74517	0	0	0
T3	113923	0	0	0
T4	163653	0	0	0
T5	17250	0	0	0
T6	64556	0	0	0
T8	4828	0	0	0
T9	5473	0	0	0
T10	1463	0	0	0
T11	38247	0	0	0
T12	0	7	0	0
T13	0	1	0	0
T34	0	5	0	0
T37	0	3	0	0
T137	0	3	0	0
T138	0	6	0	0
T139	0	1	0	0
T140	0	10	0	0
T141	0	7	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107161696	1099	0	0
T7	85550	0	0	0
T13	169928	1	0	0
T14	42216	0	0	0
T15	40277	0	0	0
T25	38839	0	0	0
T26	784	0	0	0
T29	66510	0	0	0
T31	33266	0	0	0
T36	50616	0	0	0
T37	0	4	0	0
T56	22010	0	0	0
T107	0	30	0	0
T113	0	4	0	0
T137	0	12	0	0
T142	0	9	0	0
T143	0	8	0	0
T144	0	8	0	0
T145	0	6	0	0
T146	0	14	0	0