Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2173103	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2390550

1

T1

1812

T2

367

T9

4960

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4223535	1			T1	2881		T2	353		T9	8819
values[0x0]	170066	1			T1	256		T2	143		T9	347
values[0x1]	170052	1			T1	224		T2	137		T9	341

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1728928	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2834725

1

T1

2113

T2

432

T9

5899

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15171	1			T1	2		T9	49		T5	131
valid_sources[0x01]	14055	1			T1	18		T9	38		T10	1
valid_sources[0x02]	42593	1			T1	22		T9	32		T5	124
valid_sources[0x03]	12890	1			T1	6		T9	51		T4	17
valid_sources[0x04]	13236	1			T1	3		T9	51		T10	10
valid_sources[0x05]	13303	1			T1	14		T9	47		T10	17
valid_sources[0x06]	85910	1			T1	3		T9	36		T5	172
valid_sources[0x07]	12794	1			T1	23		T9	35		T5	134
valid_sources[0x08]	12804	1			T1	13		T9	32		T10	3
valid_sources[0x09]	12760	1			T1	6		T9	34		T4	17
valid_sources[0x0a]	15688	1			T1	5		T9	26		T10	9
valid_sources[0x0b]	12520	1			T1	26		T9	43		T5	157
valid_sources[0x0c]	12873	1			T1	27		T9	41		T10	2
valid_sources[0x0d]	14964	1			T1	10		T9	51		T10	8
valid_sources[0x0e]	17956	1			T1	17		T9	24		T5	145
valid_sources[0x0f]	13826	1			T1	19		T9	39		T5	123
valid_sources[0x10]	14927	1			T1	15		T9	34		T4	17
valid_sources[0x11]	16674	1			T1	9		T9	46		T4	3946
valid_sources[0x12]	13129	1			T1	15		T9	33		T10	13
valid_sources[0x13]	12698	1			T1	20		T9	29		T5	119
valid_sources[0x14]	12611	1			T1	10		T9	33		T10	10
valid_sources[0x15]	13254	1			T1	19		T9	37		T5	99
valid_sources[0x16]	43597	1			T1	5		T9	42		T4	17
valid_sources[0x17]	12687	1			T1	8		T9	44		T5	125
valid_sources[0x18]	13044	1			T1	11		T9	47		T10	2
valid_sources[0x19]	14082	1			T1	22		T9	40		T5	126
valid_sources[0x1a]	12620	1			T1	26		T9	30		T10	13
valid_sources[0x1b]	12898	1			T1	9		T9	30		T5	149
valid_sources[0x1c]	13298	1			T1	15		T9	38		T4	3
valid_sources[0x1d]	12795	1			T1	8		T9	34		T10	3
valid_sources[0x1e]	13147	1			T1	36		T9	37		T10	3
valid_sources[0x1f]	15591	1			T1	26		T9	32		T4	17
valid_sources[0x20]	13656	1			T1	18		T9	28		T5	155
valid_sources[0x21]	12686	1			T1	21		T9	27		T5	204
valid_sources[0x22]	12772	1			T1	21		T9	36		T10	5
valid_sources[0x23]	60077	1			T1	15		T9	41		T5	164
valid_sources[0x24]	14181	1			T1	28		T9	43		T5	182
valid_sources[0x25]	13151	1			T1	5		T9	29		T10	12
valid_sources[0x26]	13184	1			T1	31		T9	52		T5	165
valid_sources[0x27]	15376	1			T1	18		T9	48		T10	5
valid_sources[0x28]	12749	1			T1	6		T9	56		T5	102
valid_sources[0x29]	13296	1			T1	6		T9	35		T10	9
valid_sources[0x2a]	12786	1			T1	11		T9	39		T10	12
valid_sources[0x2b]	13169	1			T1	11		T9	39		T10	20
valid_sources[0x2c]	13588	1			T1	16		T9	26		T10	12
valid_sources[0x2d]	15234	1			T1	17		T9	39		T4	17
valid_sources[0x2e]	13143	1			T1	15		T9	43		T10	3
valid_sources[0x2f]	13079	1			T1	9		T9	34		T5	109
valid_sources[0x30]	16978	1			T1	21		T9	34		T10	1
valid_sources[0x31]	12782	1			T1	8		T9	31		T10	20
valid_sources[0x32]	12902	1			T1	20		T9	42		T4	2
valid_sources[0x33]	12395	1			T1	12		T9	30		T5	108
valid_sources[0x34]	19883	1			T1	18		T9	27		T10	4
valid_sources[0x35]	12964	1			T1	10		T9	31		T10	3
valid_sources[0x36]	14100	1			T1	20		T9	45		T4	17
valid_sources[0x37]	12793	1			T1	11		T9	34		T5	90
valid_sources[0x38]	13643	1			T1	13		T9	30		T5	160
valid_sources[0x39]	56386	1			T1	17		T9	36		T10	11
valid_sources[0x3a]	12693	1			T1	12		T9	35		T10	4
valid_sources[0x3b]	13161	1			T1	13		T9	42		T10	4
valid_sources[0x3c]	13650	1			T1	13		T9	35		T4	17
valid_sources[0x3d]	18113	1			T1	2		T9	33		T10	7
valid_sources[0x3e]	12765	1			T1	11		T9	36		T4	53
valid_sources[0x3f]	13475	1			T1	7		T9	28		T10	4
valid_sources[0x40]	14253	1			T1	13		T9	45		T5	164
valid_sources[0x41]	12894	1			T1	7		T9	45		T10	3
valid_sources[0x42]	13021	1			T1	2		T9	33		T10	55
valid_sources[0x43]	38445	1			T1	23		T9	41		T10	2
valid_sources[0x44]	14631	1			T1	7		T9	32		T4	17
valid_sources[0x45]	12903	1			T1	9		T9	29		T5	112
valid_sources[0x46]	12715	1			T1	21		T9	34		T10	5
valid_sources[0x47]	12553	1			T1	21		T9	24		T10	11
valid_sources[0x48]	15063	1			T1	12		T9	36		T10	8
valid_sources[0x49]	12810	1			T1	4		T9	40		T10	6
valid_sources[0x4a]	12962	1			T1	16		T9	32		T10	14
valid_sources[0x4b]	13281	1			T1	4		T9	54		T10	3
valid_sources[0x4c]	21471	1			T1	17		T9	48		T10	6
valid_sources[0x4d]	12692	1			T1	8		T9	39		T10	6
valid_sources[0x4e]	12915	1			T1	11		T9	31		T5	142
valid_sources[0x4f]	14643	1			T1	12		T9	24		T10	2
valid_sources[0x50]	12949	1			T1	18		T9	27		T5	186
valid_sources[0x51]	12838	1			T1	4		T9	49		T5	131
valid_sources[0x52]	15654	1			T1	7		T9	36		T5	106
valid_sources[0x53]	13961	1			T1	10		T9	42		T5	140
valid_sources[0x54]	13968	1			T1	16		T9	36		T10	9
valid_sources[0x55]	12791	1			T1	15		T9	30		T10	8
valid_sources[0x56]	13373	1			T1	6		T9	48		T4	17
valid_sources[0x57]	12880	1			T1	13		T9	47		T10	4
valid_sources[0x58]	13197	1			T1	19		T9	50		T10	2
valid_sources[0x59]	12494	1			T1	12		T9	33		T5	120
valid_sources[0x5a]	18716	1			T1	22		T9	28		T10	1
valid_sources[0x5b]	18856	1			T1	23		T9	38		T10	3
valid_sources[0x5c]	13068	1			T1	3		T2	633		T9	32
valid_sources[0x5d]	13036	1			T1	20		T9	47		T10	3
valid_sources[0x5e]	12707	1			T1	3		T9	31		T10	8
valid_sources[0x5f]	68390	1			T1	1		T9	36		T10	4
valid_sources[0x60]	13240	1			T1	9		T9	46		T5	136
valid_sources[0x61]	14437	1			T1	15		T9	38		T10	9
valid_sources[0x62]	14336	1			T1	10		T9	41		T10	6
valid_sources[0x63]	12990	1			T1	12		T9	35		T5	109
valid_sources[0x64]	13251	1			T1	24		T9	43		T10	2
valid_sources[0x65]	13147	1			T1	11		T9	49		T10	6
valid_sources[0x66]	12784	1			T1	29		T9	29		T10	7
valid_sources[0x67]	13500	1			T1	19		T9	38		T10	18
valid_sources[0x68]	12930	1			T1	6		T9	43		T5	100
valid_sources[0x69]	14533	1			T1	13		T9	48		T10	5
valid_sources[0x6a]	12691	1			T1	13		T9	37		T10	12
valid_sources[0x6b]	12943	1			T1	22		T9	33		T5	124
valid_sources[0x6c]	13695	1			T1	13		T9	28		T10	3
valid_sources[0x6d]	13241	1			T1	7		T9	32		T5	105
valid_sources[0x6e]	13102	1			T1	9		T9	34		T10	25
valid_sources[0x6f]	13347	1			T1	15		T9	37		T5	129
valid_sources[0x70]	12879	1			T1	14		T9	37		T10	26
valid_sources[0x71]	30821	1			T1	8		T9	36		T4	17
valid_sources[0x72]	15092	1			T1	27		T9	36		T5	112
valid_sources[0x73]	12905	1			T1	27		T9	25		T10	1
valid_sources[0x74]	67034	1			T1	14		T9	38		T10	3
valid_sources[0x75]	13834	1			T1	6		T9	35		T10	1
valid_sources[0x76]	12953	1			T1	11		T9	42		T10	5
valid_sources[0x77]	12595	1			T1	23		T9	31		T10	21
valid_sources[0x78]	12424	1			T1	4		T9	39		T5	151
valid_sources[0x79]	12621	1			T1	20		T9	34		T10	10
valid_sources[0x7a]	13023	1			T1	11		T9	37		T10	17
valid_sources[0x7b]	15504	1			T1	8		T9	28		T10	5
valid_sources[0x7c]	21590	1			T1	13		T9	26		T5	161
valid_sources[0x7d]	14080	1			T1	5		T9	42		T5	190
valid_sources[0x7e]	12779	1			T1	10		T9	43		T5	148
valid_sources[0x7f]	13370	1			T1	13		T9	46		T10	4
valid_sources[0x80]	15235	1			T1	14		T9	41		T10	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2097063

1

T1

1395

T2

121

T9

4361

values[0x0]

all_enables

biggest_size

147570

1

T1

222

T2

127

T9

309

values[0x1]

all_enables

biggest_size

145917

1

T1

195

T2

119

T9

290