Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	108514651	12481	0	0
claim_transition_if_regwen_rd_A	108514651	1691	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108514651	12481	0	0
T4	195974	1	0	0
T5	140900	0	0	0
T10	28686	0	0	0
T11	3605	0	0	0
T12	1346	0	0	0
T13	45616	0	0	0
T14	564653	15	0	0
T17	0	8	0	0
T20	36430	0	0	0
T58	23333	0	0	0
T59	42117	0	0	0
T76	0	6	0	0
T106	0	6	0	0
T142	0	8	0	0
T143	0	7	0	0
T144	0	6	0	0
T145	0	3	0	0
T146	0	2	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108514651	1691	0	0
T4	195974	15	0	0
T5	140900	0	0	0
T10	28686	0	0	0
T11	3605	0	0	0
T12	1346	0	0	0
T13	45616	0	0	0
T14	564653	0	0	0
T20	36430	0	0	0
T42	0	6	0	0
T45	0	5	0	0
T58	23333	0	0	0
T59	42117	0	0	0
T104	0	8	0	0
T111	0	14	0	0
T146	0	3	0	0
T147	0	7	0	0
T148	0	13	0	0
T149	0	18	0	0
T150	0	9	0	0