Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1045914	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1254894

1

T1

395

T2

139

T3

843

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1976894	1			T1	419		T2	119		T3	745
values[0x0]	161206	1			T1	185		T2	43		T3	297
values[0x1]	162708	1			T1	202		T2	53		T3	295

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	827873	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1472935

1

T1

457

T2

161

T3

954

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6288	1			T1	20		T3	26		T12	9
valid_sources[0x01]	6218	1			T1	2		T12	7		T15	6
valid_sources[0x02]	5966	1			T12	7		T15	10		T36	6
valid_sources[0x03]	6330	1			T1	6		T3	5		T12	10
valid_sources[0x04]	5679	1			T3	7		T11	2		T12	14
valid_sources[0x05]	6188	1			T1	10		T3	23		T12	14
valid_sources[0x06]	6287	1			T1	23		T3	17		T11	33
valid_sources[0x07]	7855	1			T9	199		T12	7		T15	6
valid_sources[0x08]	5982	1			T3	13		T12	8		T15	5
valid_sources[0x09]	5883	1			T1	2		T3	8		T11	7
valid_sources[0x0a]	6475	1			T3	4		T11	42		T12	10
valid_sources[0x0b]	30112	1			T1	2		T3	7		T11	5
valid_sources[0x0c]	6088	1			T1	1		T3	2		T12	10
valid_sources[0x0d]	49688	1			T1	9		T12	11		T15	8
valid_sources[0x0e]	7617	1			T3	7		T11	16		T12	9
valid_sources[0x0f]	5839	1			T3	1		T12	12		T15	5
valid_sources[0x10]	6967	1			T1	16		T3	29		T12	12
valid_sources[0x11]	6457	1			T1	9		T3	1		T11	11
valid_sources[0x12]	6177	1			T1	4		T3	12		T12	8
valid_sources[0x13]	6743	1			T3	2		T12	15		T15	5
valid_sources[0x14]	9828	1			T3	3		T11	5		T12	5
valid_sources[0x15]	6017	1			T1	4		T3	4		T11	13
valid_sources[0x16]	5774	1			T3	6		T12	10		T15	6
valid_sources[0x17]	6398	1			T3	2		T11	2		T12	9
valid_sources[0x18]	6169	1			T3	4		T12	7		T15	8
valid_sources[0x19]	12081	1			T1	3		T3	5		T12	16
valid_sources[0x1a]	5753	1			T3	1		T11	1		T12	12
valid_sources[0x1b]	5741	1			T3	3		T11	7		T12	5
valid_sources[0x1c]	11206	1			T1	5		T3	3		T12	9
valid_sources[0x1d]	6456	1			T1	3		T3	3		T12	12
valid_sources[0x1e]	7851	1			T3	24		T12	8		T15	4
valid_sources[0x1f]	5827	1			T12	12		T15	6		T36	7
valid_sources[0x20]	6116	1			T3	2		T11	12		T12	9
valid_sources[0x21]	6162	1			T1	19		T3	1		T9	29
valid_sources[0x22]	8986	1			T12	6		T15	6		T36	3
valid_sources[0x23]	6148	1			T1	6		T12	13		T15	2
valid_sources[0x24]	6489	1			T1	5		T3	5		T11	11
valid_sources[0x25]	6673	1			T1	1		T12	16		T15	6
valid_sources[0x26]	6754	1			T3	7		T11	2		T12	9
valid_sources[0x27]	6000	1			T3	2		T11	4		T12	9
valid_sources[0x28]	7506	1			T3	4		T12	12		T15	12
valid_sources[0x29]	20266	1			T1	5		T3	6		T9	21
valid_sources[0x2a]	5979	1			T3	7		T11	11		T12	18
valid_sources[0x2b]	6044	1			T3	10		T12	15		T15	5
valid_sources[0x2c]	10774	1			T1	6		T11	1		T12	8
valid_sources[0x2d]	6999	1			T1	3		T3	1		T11	18
valid_sources[0x2e]	6151	1			T3	1		T12	16		T15	4
valid_sources[0x2f]	6354	1			T1	8		T3	11		T12	11
valid_sources[0x30]	25623	1			T1	7		T3	3		T12	12
valid_sources[0x31]	6180	1			T1	3		T3	11		T11	7
valid_sources[0x32]	8034	1			T11	6		T12	9		T15	5
valid_sources[0x33]	7616	1			T9	87		T11	25		T12	6
valid_sources[0x34]	5637	1			T11	5		T12	20		T15	4
valid_sources[0x35]	39791	1			T1	4		T3	5		T11	1
valid_sources[0x36]	6155	1			T3	3		T9	118		T12	3
valid_sources[0x37]	6259	1			T3	3		T9	125		T11	4
valid_sources[0x38]	6255	1			T1	1		T11	26		T12	10
valid_sources[0x39]	8697	1			T1	3		T3	4		T12	15
valid_sources[0x3a]	18592	1			T1	1		T3	1		T12	9
valid_sources[0x3b]	5936	1			T1	1		T3	3		T11	1
valid_sources[0x3c]	6810	1			T3	2		T10	3		T12	20
valid_sources[0x3d]	7361	1			T3	13		T12	12		T15	7
valid_sources[0x3e]	6770	1			T12	8		T15	3		T36	8
valid_sources[0x3f]	34093	1			T3	1		T11	12		T12	8
valid_sources[0x40]	6136	1			T1	15		T12	11		T15	7
valid_sources[0x41]	6488	1			T1	4		T9	42		T12	11
valid_sources[0x42]	7201	1			T1	7		T12	7		T15	2
valid_sources[0x43]	8313	1			T3	16		T12	7		T15	7
valid_sources[0x44]	8467	1			T1	2		T3	9		T12	12
valid_sources[0x45]	12967	1			T1	26		T3	7		T11	4
valid_sources[0x46]	6018	1			T3	17		T12	9		T15	6
valid_sources[0x47]	6924	1			T1	3		T3	22		T11	19
valid_sources[0x48]	6081	1			T1	3		T3	3		T9	115
valid_sources[0x49]	8875	1			T3	61		T10	4		T11	21
valid_sources[0x4a]	6198	1			T3	3		T12	8		T15	6
valid_sources[0x4b]	6322	1			T1	7		T3	9		T9	12
valid_sources[0x4c]	7373	1			T11	1		T12	11		T15	7
valid_sources[0x4d]	26554	1			T1	2		T2	215		T3	9
valid_sources[0x4e]	5794	1			T1	1		T3	5		T12	12
valid_sources[0x4f]	5956	1			T12	10		T15	4		T36	4
valid_sources[0x50]	7255	1			T3	10		T11	6		T12	12
valid_sources[0x51]	6019	1			T3	13		T11	10		T12	10
valid_sources[0x52]	6289	1			T1	3		T3	7		T12	14
valid_sources[0x53]	9208	1			T3	1		T11	9		T12	9
valid_sources[0x54]	6165	1			T1	1		T11	3		T12	9
valid_sources[0x55]	31354	1			T3	4		T12	16		T15	6
valid_sources[0x56]	7563	1			T1	2		T12	11		T15	1
valid_sources[0x57]	7304	1			T3	10		T11	22		T12	5
valid_sources[0x58]	6739	1			T11	4		T12	8		T15	10
valid_sources[0x59]	5614	1			T3	28		T11	4		T12	8
valid_sources[0x5a]	6120	1			T11	8		T12	11		T15	9
valid_sources[0x5b]	6145	1			T1	4		T12	18		T15	11
valid_sources[0x5c]	9441	1			T1	2		T3	1		T12	8
valid_sources[0x5d]	6322	1			T12	8		T15	4		T36	6
valid_sources[0x5e]	6453	1			T3	1		T12	13		T15	5
valid_sources[0x5f]	5884	1			T3	4		T12	13		T15	6
valid_sources[0x60]	17570	1			T3	19		T12	20		T5	50
valid_sources[0x61]	6192	1			T1	3		T3	21		T12	16
valid_sources[0x62]	5914	1			T3	1		T12	7		T15	1
valid_sources[0x63]	6122	1			T1	13		T3	27		T11	2
valid_sources[0x64]	78051	1			T1	1		T3	12		T11	17
valid_sources[0x65]	8202	1			T12	16		T15	11		T36	3
valid_sources[0x66]	7088	1			T1	3		T3	1		T12	8
valid_sources[0x67]	5938	1			T3	27		T12	7		T15	9
valid_sources[0x68]	6066	1			T3	6		T9	127		T12	9
valid_sources[0x69]	23358	1			T1	3		T11	10		T12	12
valid_sources[0x6a]	6605	1			T1	4		T3	1		T12	6
valid_sources[0x6b]	5721	1			T3	6		T12	6		T5	17
valid_sources[0x6c]	13259	1			T3	5		T12	11		T15	8
valid_sources[0x6d]	6053	1			T3	9		T12	11		T15	1
valid_sources[0x6e]	7988	1			T9	90		T11	20		T12	15
valid_sources[0x6f]	7880	1			T3	9		T9	77		T12	11
valid_sources[0x70]	6213	1			T1	19		T12	7		T15	7
valid_sources[0x71]	7117	1			T1	1		T3	1		T12	10
valid_sources[0x72]	6046	1			T1	4		T3	1		T12	18
valid_sources[0x73]	5945	1			T3	1		T12	9		T15	4
valid_sources[0x74]	5907	1			T3	11		T10	5		T12	22
valid_sources[0x75]	6151	1			T11	8		T12	9		T15	10
valid_sources[0x76]	6184	1			T3	2		T9	12		T12	11
valid_sources[0x77]	13977	1			T3	2		T12	8		T15	4
valid_sources[0x78]	17319	1			T1	6		T3	16		T11	13
valid_sources[0x79]	5620	1			T3	2		T12	8		T15	15
valid_sources[0x7a]	6121	1			T1	9		T3	10		T12	12
valid_sources[0x7b]	11897	1			T3	10		T12	11		T15	12
valid_sources[0x7c]	60255	1			T3	2		T11	2		T12	8
valid_sources[0x7d]	6169	1			T1	4		T3	10		T9	22
valid_sources[0x7e]	5943	1			T3	17		T12	17		T15	5
valid_sources[0x7f]	6266	1			T1	3		T12	9		T15	4
valid_sources[0x80]	5899	1			T11	6		T12	12		T15	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

975121

1

T1

224

T2

60

T3

326

values[0x0]

all_enables

biggest_size

140216

1

T1

99

T2

36

T3

253

values[0x1]

all_enables

biggest_size

139557

1

T1

72

T2

43

T3

264