Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	101073978	15603	0	0
claim_transition_if_regwen_rd_A	101073978	1675	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101073978	15603	0	0
T5	295921	1	0	0
T14	57732	0	0	0
T15	26119	0	0	0
T16	8988	0	0	0
T17	117193	0	0	0
T31	0	2	0	0
T34	7171	0	0	0
T36	28368	0	0	0
T39	27588	0	0	0
T47	0	2	0	0
T48	0	4	0	0
T55	35237	0	0	0
T61	0	9	0	0
T64	7589	0	0	0
T130	0	4	0	0
T131	0	1	0	0
T132	0	8	0	0
T133	0	1	0	0
T134	0	9	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101073978	1675	0	0
T24	40979	0	0	0
T48	495021	15	0	0
T98	0	54	0	0
T100	0	85	0	0
T111	0	4	0	0
T130	0	5	0	0
T133	0	12	0	0
T135	0	5	0	0
T136	0	2	0	0
T137	0	5	0	0
T138	0	6	0	0
T139	8802	0	0	0
T140	2762	0	0	0
T141	24101	0	0	0
T142	37489	0	0	0
T143	103540	0	0	0
T144	25483	0	0	0
T145	31766	0	0	0
T146	33230	0	0	0