Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1132481	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1336945

1

T1

272

T3

191

T7

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2151737	1			T1	343		T3	190		T7	5
values[0x0]	158546	1			T1	56		T3	83		T7	9
values[0x1]	159143	1			T1	72		T3	85		T7	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	898340	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1571086

1

T1

318

T3

226

T7

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7961	1			T8	1		T10	1		T12	1
valid_sources[0x01]	7986	1			T10	1		T13	3		T29	8
valid_sources[0x02]	8140	1			T3	4		T8	8		T10	1
valid_sources[0x03]	7678	1			T13	9		T29	5		T15	20
valid_sources[0x04]	10367	1			T29	13		T15	22		T32	2
valid_sources[0x05]	8129	1			T3	9		T8	13		T10	1
valid_sources[0x06]	8117	1			T8	8		T12	3		T13	5
valid_sources[0x07]	8083	1			T11	55		T12	2		T13	5
valid_sources[0x08]	8011	1			T3	14		T8	9		T13	5
valid_sources[0x09]	8843	1			T8	2		T10	3		T29	11
valid_sources[0x0a]	9682	1			T8	9		T13	6		T29	12
valid_sources[0x0b]	7722	1			T3	1		T5	3		T8	7
valid_sources[0x0c]	11400	1			T3	10		T5	1		T8	12
valid_sources[0x0d]	8174	1			T5	4		T12	1		T13	3
valid_sources[0x0e]	7808	1			T3	6		T8	16		T13	2
valid_sources[0x0f]	8126	1			T5	1		T8	3		T13	2
valid_sources[0x10]	8222	1			T5	1		T8	2		T10	1
valid_sources[0x11]	10363	1			T5	1		T8	8		T10	1
valid_sources[0x12]	8577	1			T5	1		T12	3		T13	1
valid_sources[0x13]	7974	1			T8	1		T10	1		T12	4
valid_sources[0x14]	8334	1			T8	9		T10	1		T29	6
valid_sources[0x15]	8145	1			T10	4		T13	1		T29	7
valid_sources[0x16]	8384	1			T5	5		T8	1		T11	221
valid_sources[0x17]	8120	1			T12	6		T13	14		T29	12
valid_sources[0x18]	8176	1			T8	2		T12	8		T13	3
valid_sources[0x19]	8015	1			T5	2		T8	10		T10	1
valid_sources[0x1a]	10602	1			T8	8		T10	3		T13	1
valid_sources[0x1b]	7775	1			T8	1		T10	1		T13	9
valid_sources[0x1c]	7888	1			T5	6		T8	6		T13	8
valid_sources[0x1d]	10453	1			T10	1		T13	13		T29	9
valid_sources[0x1e]	7838	1			T3	1		T8	8		T10	2
valid_sources[0x1f]	7933	1			T10	1		T13	7		T29	6
valid_sources[0x20]	8070	1			T3	23		T8	2		T10	1
valid_sources[0x21]	8088	1			T3	12		T5	1		T8	6
valid_sources[0x22]	7736	1			T3	10		T8	20		T10	1
valid_sources[0x23]	7708	1			T3	12		T5	2		T8	1
valid_sources[0x24]	8055	1			T3	1		T10	2		T13	10
valid_sources[0x25]	7749	1			T8	11		T10	2		T13	9
valid_sources[0x26]	11376	1			T5	8		T8	7		T13	6
valid_sources[0x27]	7919	1			T8	9		T10	2		T13	13
valid_sources[0x28]	11973	1			T8	43		T13	2		T29	7
valid_sources[0x29]	9733	1			T12	7		T13	2		T29	10
valid_sources[0x2a]	7895	1			T7	18		T5	2		T8	7
valid_sources[0x2b]	7857	1			T10	1		T13	2		T29	4
valid_sources[0x2c]	7568	1			T8	8		T10	2		T13	5
valid_sources[0x2d]	8572	1			T8	14		T10	2		T13	1
valid_sources[0x2e]	7939	1			T5	3		T10	2		T13	4
valid_sources[0x2f]	8434	1			T5	1		T8	2		T10	1
valid_sources[0x30]	7756	1			T3	3		T10	1		T13	2
valid_sources[0x31]	8182	1			T5	2		T8	6		T13	2
valid_sources[0x32]	10691	1			T5	3		T8	18		T13	3
valid_sources[0x33]	8016	1			T5	4		T8	5		T10	1
valid_sources[0x34]	11388	1			T5	1		T10	1		T12	1
valid_sources[0x35]	10333	1			T5	1		T8	1		T10	2
valid_sources[0x36]	9062	1			T3	9		T5	1		T8	11
valid_sources[0x37]	7982	1			T8	4		T13	10		T29	11
valid_sources[0x38]	9079	1			T8	7		T10	1		T13	3
valid_sources[0x39]	8048	1			T7	2		T5	2		T8	1
valid_sources[0x3a]	8639	1			T5	1		T8	5		T13	3
valid_sources[0x3b]	8088	1			T8	13		T10	2		T12	1
valid_sources[0x3c]	8022	1			T10	1		T13	2		T29	6
valid_sources[0x3d]	8288	1			T8	37		T10	1		T12	1
valid_sources[0x3e]	7939	1			T8	10		T10	1		T11	1
valid_sources[0x3f]	7545	1			T8	6		T10	1		T13	1
valid_sources[0x40]	10993	1			T3	4		T10	1		T12	3
valid_sources[0x41]	8163	1			T13	2		T29	10		T15	46
valid_sources[0x42]	8039	1			T8	12		T10	1		T13	16
valid_sources[0x43]	8133	1			T8	8		T13	1		T29	10
valid_sources[0x44]	8771	1			T8	4		T29	6		T15	26
valid_sources[0x45]	9682	1			T3	1		T8	2		T10	2
valid_sources[0x46]	7799	1			T8	19		T13	4		T29	10
valid_sources[0x47]	30081	1			T5	4		T10	1		T13	8
valid_sources[0x48]	9063	1			T8	17		T13	1		T29	10
valid_sources[0x49]	7929	1			T1	46		T5	2		T8	1
valid_sources[0x4a]	7940	1			T8	2		T10	1		T13	4
valid_sources[0x4b]	7952	1			T5	3		T8	9		T10	3
valid_sources[0x4c]	7943	1			T3	2		T5	4		T8	1
valid_sources[0x4d]	7776	1			T8	12		T10	1		T13	6
valid_sources[0x4e]	7985	1			T5	2		T8	5		T12	1
valid_sources[0x4f]	7781	1			T5	2		T8	14		T10	4
valid_sources[0x50]	8308	1			T5	3		T8	9		T10	1
valid_sources[0x51]	7752	1			T8	24		T12	2		T13	4
valid_sources[0x52]	7972	1			T5	1		T10	1		T13	4
valid_sources[0x53]	8066	1			T8	16		T10	2		T12	1
valid_sources[0x54]	23545	1			T5	1		T8	12		T10	2
valid_sources[0x55]	10294	1			T5	1		T8	21		T10	2
valid_sources[0x56]	8044	1			T10	2		T13	1		T29	15
valid_sources[0x57]	7945	1			T8	5		T13	8		T29	7
valid_sources[0x58]	7885	1			T8	3		T13	2		T29	5
valid_sources[0x59]	11808	1			T8	15		T10	2		T29	7
valid_sources[0x5a]	8124	1			T3	9		T8	16		T12	3
valid_sources[0x5b]	9073	1			T8	2		T10	1		T13	4
valid_sources[0x5c]	7932	1			T10	1		T29	14		T32	4
valid_sources[0x5d]	8950	1			T29	5		T15	83		T32	6
valid_sources[0x5e]	7852	1			T8	4		T10	1		T13	6
valid_sources[0x5f]	7868	1			T3	1		T8	10		T10	1
valid_sources[0x60]	18264	1			T5	3		T8	11		T13	2
valid_sources[0x61]	10441	1			T3	2		T8	31		T10	2
valid_sources[0x62]	7729	1			T5	3		T8	30		T12	1
valid_sources[0x63]	149203	1			T8	3		T13	8		T29	7
valid_sources[0x64]	9760	1			T5	2		T13	1		T29	16
valid_sources[0x65]	8423	1			T1	38		T5	1		T8	18
valid_sources[0x66]	7586	1			T5	1		T8	16		T10	2
valid_sources[0x67]	7819	1			T8	15		T13	10		T29	8
valid_sources[0x68]	7717	1			T3	4		T13	4		T29	8
valid_sources[0x69]	10722	1			T8	5		T9	1147		T12	1
valid_sources[0x6a]	7977	1			T8	5		T13	7		T29	8
valid_sources[0x6b]	8021	1			T5	2		T8	9		T10	2
valid_sources[0x6c]	8989	1			T5	4		T13	5		T29	12
valid_sources[0x6d]	7865	1			T5	4		T8	10		T12	2
valid_sources[0x6e]	7933	1			T8	13		T12	7		T13	3
valid_sources[0x6f]	7970	1			T5	1		T8	12		T12	9
valid_sources[0x70]	7699	1			T8	2		T29	10		T32	1
valid_sources[0x71]	7880	1			T5	7		T8	21		T13	12
valid_sources[0x72]	8787	1			T5	3		T12	6		T13	2
valid_sources[0x73]	8288	1			T5	1		T10	1		T29	8
valid_sources[0x74]	9191	1			T5	1		T8	8		T10	1
valid_sources[0x75]	8843	1			T8	26		T10	3		T13	2
valid_sources[0x76]	11562	1			T1	83		T5	1		T8	2
valid_sources[0x77]	7771	1			T8	10		T12	3		T29	8
valid_sources[0x78]	8861	1			T8	1		T13	1		T29	12
valid_sources[0x79]	8223	1			T5	1		T8	2		T10	2
valid_sources[0x7a]	8340	1			T12	1		T13	10		T29	4
valid_sources[0x7b]	8602	1			T8	11		T10	2		T29	5
valid_sources[0x7c]	9770	1			T3	33		T8	29		T10	2
valid_sources[0x7d]	7942	1			T8	12		T29	15		T15	13
valid_sources[0x7e]	9591	1			T10	3		T13	3		T29	15
valid_sources[0x7f]	7892	1			T13	3		T29	9		T15	115
valid_sources[0x80]	8123	1			T13	4		T29	11		T34	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1063225

1

T1

164

T3

86

T5

65

values[0x0]

all_enables

biggest_size

137536

1

T1

44

T3

60

T7

8

values[0x1]

all_enables

biggest_size

136184

1

T1

64

T3

45

T7

5