Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	95611529	17057	0	0
claim_transition_if_regwen_rd_A	95611529	1125	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95611529	17057	0	0
T6	46755	0	0	0
T18	100291	1	0	0
T19	50360	0	0	0
T30	33084	0	0	0
T33	44780	0	0	0
T37	30294	0	0	0
T42	346513	3	0	0
T46	33769	0	0	0
T80	2138	0	0	0
T81	6800	0	0	0
T89	0	1	0	0
T99	0	1	0	0
T102	0	6	0	0
T140	0	1	0	0
T141	0	3	0	0
T142	0	1	0	0
T143	0	15	0	0
T144	0	5	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95611529	1125	0	0
T19	50360	0	0	0
T37	30294	0	0	0
T42	346513	7	0	0
T46	33769	0	0	0
T60	237636	0	0	0
T80	2138	0	0	0
T81	6800	0	0	0
T82	244094	0	0	0
T99	0	2	0	0
T103	0	13	0	0
T110	0	30	0	0
T141	0	19	0	0
T144	0	9	0	0
T145	0	7	0	0
T146	0	6	0	0
T147	0	3	0	0
T148	0	26	0	0
T149	32259	0	0	0
T150	34568	0	0	0