Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1268480	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1468015

1

T1

123

T2

2597

T3

43

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2420866	1			T1	119		T2	4020		T3	158
values[0x0]	157520	1			T1	44		T2	328		T4	513
values[0x1]	158109	1			T1	43		T2	336		T4	530

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1006744	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1729751

1

T1

136

T2

3049

T3

66

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7558	1			T2	23		T3	1		T14	4
valid_sources[0x01]	7169	1			T2	14		T11	1		T14	9
valid_sources[0x02]	7406	1			T2	24		T3	1		T14	9
valid_sources[0x03]	7165	1			T2	16		T3	4		T11	2
valid_sources[0x04]	58399	1			T2	28		T13	1		T14	5
valid_sources[0x05]	8165	1			T1	5		T2	22		T14	11
valid_sources[0x06]	7294	1			T2	8		T3	2		T11	2
valid_sources[0x07]	8549	1			T1	4		T2	10		T3	1
valid_sources[0x08]	8676	1			T1	6		T2	20		T3	1
valid_sources[0x09]	15299	1			T1	1		T2	25		T4	17
valid_sources[0x0a]	7930	1			T2	14		T3	1		T14	11
valid_sources[0x0b]	7737	1			T1	3		T2	22		T4	17
valid_sources[0x0c]	7938	1			T2	19		T14	10		T15	10
valid_sources[0x0d]	6810	1			T1	2		T2	10		T3	1
valid_sources[0x0e]	15990	1			T1	2		T2	8		T14	11
valid_sources[0x0f]	8655	1			T1	2		T2	20		T11	1
valid_sources[0x10]	11558	1			T2	17		T3	2		T11	3
valid_sources[0x11]	7766	1			T2	6		T13	1		T14	9
valid_sources[0x12]	7725	1			T1	8		T2	8		T3	1
valid_sources[0x13]	8463	1			T2	18		T13	1		T14	8
valid_sources[0x14]	7997	1			T2	25		T14	8		T15	8
valid_sources[0x15]	53832	1			T2	14		T10	5		T11	1
valid_sources[0x16]	42794	1			T1	3		T2	9		T3	1
valid_sources[0x17]	7641	1			T2	17		T3	1		T11	1
valid_sources[0x18]	7293	1			T2	13		T13	1		T14	6
valid_sources[0x19]	8065	1			T2	28		T11	1		T14	6
valid_sources[0x1a]	11261	1			T1	2		T2	20		T3	1
valid_sources[0x1b]	7385	1			T2	13		T3	1		T14	5
valid_sources[0x1c]	7353	1			T1	1		T2	23		T11	1
valid_sources[0x1d]	7401	1			T2	20		T13	1		T14	9
valid_sources[0x1e]	9151	1			T2	23		T14	6		T15	9
valid_sources[0x1f]	7668	1			T2	15		T3	1		T13	1
valid_sources[0x20]	7926	1			T1	3		T2	17		T14	5
valid_sources[0x21]	7666	1			T2	15		T3	2		T11	1
valid_sources[0x22]	7864	1			T1	1		T2	13		T14	8
valid_sources[0x23]	8453	1			T2	15		T3	1		T11	1
valid_sources[0x24]	7427	1			T2	22		T10	2		T14	7
valid_sources[0x25]	7557	1			T2	10		T11	2		T13	4
valid_sources[0x26]	7558	1			T2	20		T11	1		T14	8
valid_sources[0x27]	7632	1			T2	18		T14	10		T15	4
valid_sources[0x28]	7517	1			T1	3		T2	18		T11	2
valid_sources[0x29]	7661	1			T2	30		T11	1		T14	6
valid_sources[0x2a]	8950	1			T1	4		T2	23		T11	4
valid_sources[0x2b]	9648	1			T2	14		T14	5		T6	1
valid_sources[0x2c]	7566	1			T2	14		T14	16		T15	5
valid_sources[0x2d]	7749	1			T2	13		T3	2		T11	1
valid_sources[0x2e]	9281	1			T2	15		T3	1		T14	12
valid_sources[0x2f]	9128	1			T2	22		T3	1		T11	1
valid_sources[0x30]	7368	1			T2	31		T3	1		T14	10
valid_sources[0x31]	8010	1			T2	22		T3	1		T14	10
valid_sources[0x32]	7838	1			T1	1		T2	13		T14	10
valid_sources[0x33]	7468	1			T1	2		T2	16		T14	4
valid_sources[0x34]	7759	1			T2	20		T14	9		T15	1
valid_sources[0x35]	8193	1			T2	22		T3	1		T11	2
valid_sources[0x36]	7819	1			T1	1		T2	12		T11	1
valid_sources[0x37]	7320	1			T2	18		T11	1		T14	8
valid_sources[0x38]	7139	1			T1	1		T2	30		T13	2
valid_sources[0x39]	8191	1			T2	18		T3	1		T4	17
valid_sources[0x3a]	7729	1			T2	26		T3	1		T11	1
valid_sources[0x3b]	8567	1			T2	15		T3	1		T11	3
valid_sources[0x3c]	7621	1			T1	1		T2	15		T11	4
valid_sources[0x3d]	8125	1			T2	13		T13	2		T14	10
valid_sources[0x3e]	7713	1			T2	23		T11	5		T14	5
valid_sources[0x3f]	7504	1			T1	4		T2	9		T14	4
valid_sources[0x40]	7734	1			T2	29		T14	7		T15	1
valid_sources[0x41]	7746	1			T1	2		T2	10		T11	1
valid_sources[0x42]	61388	1			T2	15		T14	7		T15	7
valid_sources[0x43]	51145	1			T2	14		T3	1		T14	11
valid_sources[0x44]	7874	1			T2	18		T3	1		T14	6
valid_sources[0x45]	7338	1			T2	24		T12	18		T14	10
valid_sources[0x46]	7835	1			T2	19		T11	2		T14	5
valid_sources[0x47]	8011	1			T2	8		T3	2		T14	6
valid_sources[0x48]	7735	1			T2	16		T14	7		T15	4
valid_sources[0x49]	7805	1			T2	13		T11	1		T14	13
valid_sources[0x4a]	7329	1			T1	2		T2	14		T3	2
valid_sources[0x4b]	8011	1			T2	10		T3	1		T11	5
valid_sources[0x4c]	7634	1			T2	21		T11	1		T14	6
valid_sources[0x4d]	7658	1			T2	12		T3	1		T14	4
valid_sources[0x4e]	7319	1			T1	2		T2	13		T14	11
valid_sources[0x4f]	7545	1			T1	1		T2	19		T3	2
valid_sources[0x50]	41969	1			T1	1		T2	11		T3	2
valid_sources[0x51]	9064	1			T1	1		T2	24		T14	9
valid_sources[0x52]	12114	1			T2	38		T11	3		T14	3
valid_sources[0x53]	7274	1			T2	22		T14	6		T15	5
valid_sources[0x54]	7896	1			T1	1		T2	12		T11	1
valid_sources[0x55]	8021	1			T2	24		T3	1		T11	1
valid_sources[0x56]	7566	1			T2	24		T3	1		T13	1
valid_sources[0x57]	15670	1			T2	12		T3	2		T11	3
valid_sources[0x58]	13003	1			T2	27		T14	9		T15	8
valid_sources[0x59]	7480	1			T2	16		T3	1		T14	6
valid_sources[0x5a]	39903	1			T1	1		T2	16		T3	1
valid_sources[0x5b]	52867	1			T2	17		T3	2		T14	6
valid_sources[0x5c]	9365	1			T2	20		T11	1		T14	5
valid_sources[0x5d]	37015	1			T2	26		T14	11		T15	14
valid_sources[0x5e]	8092	1			T1	1		T2	20		T11	1
valid_sources[0x5f]	8193	1			T2	19		T3	3		T14	7
valid_sources[0x60]	8011	1			T1	4		T2	14		T3	2
valid_sources[0x61]	7552	1			T1	2		T2	14		T3	1
valid_sources[0x62]	7352	1			T2	22		T3	1		T13	1
valid_sources[0x63]	9419	1			T1	1		T2	23		T3	1
valid_sources[0x64]	7281	1			T2	21		T11	2		T13	4
valid_sources[0x65]	7403	1			T1	1		T2	24		T3	1
valid_sources[0x66]	8046	1			T1	1		T2	13		T11	2
valid_sources[0x67]	25742	1			T2	14		T3	1		T14	6
valid_sources[0x68]	7800	1			T2	23		T3	1		T14	9
valid_sources[0x69]	10209	1			T2	28		T11	1		T14	6
valid_sources[0x6a]	9745	1			T1	3		T2	14		T3	3
valid_sources[0x6b]	8894	1			T1	2		T2	13		T11	1
valid_sources[0x6c]	9094	1			T1	1		T2	20		T3	1
valid_sources[0x6d]	7417	1			T2	11		T3	1		T14	10
valid_sources[0x6e]	17917	1			T1	7		T2	23		T11	1
valid_sources[0x6f]	7856	1			T2	13		T3	1		T11	3
valid_sources[0x70]	7491	1			T2	11		T11	2		T12	3
valid_sources[0x71]	10250	1			T1	2		T2	12		T11	1
valid_sources[0x72]	7442	1			T2	14		T11	1		T14	7
valid_sources[0x73]	7187	1			T2	20		T13	3		T14	2
valid_sources[0x74]	7484	1			T1	1		T2	16		T11	2
valid_sources[0x75]	7344	1			T2	27		T3	1		T14	13
valid_sources[0x76]	7623	1			T2	19		T14	4		T15	4
valid_sources[0x77]	8565	1			T2	17		T11	1		T14	9
valid_sources[0x78]	10401	1			T2	19		T14	6		T15	24
valid_sources[0x79]	7816	1			T2	23		T3	2		T11	1
valid_sources[0x7a]	21513	1			T2	9		T11	3		T14	11
valid_sources[0x7b]	17823	1			T2	34		T11	1		T14	9
valid_sources[0x7c]	9647	1			T1	2		T2	18		T3	2
valid_sources[0x7d]	7565	1			T1	1		T2	20		T3	1
valid_sources[0x7e]	22976	1			T2	15		T14	5		T15	4
valid_sources[0x7f]	8610	1			T2	17		T3	2		T11	2
valid_sources[0x80]	7588	1			T1	2		T2	20		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1196610

1

T1

52

T2

2017

T3

43

values[0x0]

all_enables

biggest_size

136414

1

T1

36

T2

288

T4

453

values[0x1]

all_enables

biggest_size

134991

1

T1

35

T2

292

T4

449