Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	89945499	14569	0	0
claim_transition_if_regwen_rd_A	89945499	951	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89945499	14569	0	0
T20	128874	9	0	0
T21	8448	0	0	0
T22	93905	0	0	0
T33	3302	0	0	0
T46	0	7	0	0
T64	9974	0	0	0
T90	6936	0	0	0
T91	6506	0	0	0
T94	1223	0	0	0
T95	1627	0	0	0
T96	0	16	0	0
T97	0	1	0	0
T101	0	1	0	0
T105	0	8	0	0
T140	0	8	0	0
T141	0	4	0	0
T142	0	6	0	0
T143	0	4	0	0
T144	105732	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89945499	951	0	0
T107	0	78	0	0
T111	0	10	0	0
T112	0	78	0	0
T114	0	4	0	0
T143	382553	11	0	0
T145	0	4	0	0
T146	0	2	0	0
T147	0	14	0	0
T148	0	9	0	0
T149	0	1	0	0
T150	5788	0	0	0
T151	66489	0	0	0
T152	555159	0	0	0
T153	8178	0	0	0
T154	8745	0	0	0
T155	7859	0	0	0
T156	4927	0	0	0
T157	7044	0	0	0
T158	31610	0	0	0