Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1596181	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1796578

1

T2

3652

T3

189

T4

440

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3084286	1			T2	4781		T3	173		T4	389
values[0x0]	153895	1			T2	825		T3	67		T4	133
values[0x1]	154578	1			T2	777		T3	78		T4	147

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1268439	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2124320

1

T2

4252

T3

222

T4

495

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15235	1			T2	21		T4	1		T10	9
valid_sources[0x01]	10837	1			T2	28		T9	10		T10	3
valid_sources[0x02]	10796	1			T2	21		T4	3		T9	6
valid_sources[0x03]	10703	1			T2	20		T3	1		T4	4
valid_sources[0x04]	10771	1			T2	27		T4	1		T7	5
valid_sources[0x05]	10547	1			T2	24		T4	3		T10	5
valid_sources[0x06]	11675	1			T2	27		T3	1		T4	4
valid_sources[0x07]	10771	1			T2	15		T4	10		T10	1
valid_sources[0x08]	12165	1			T2	27		T3	4		T4	2
valid_sources[0x09]	10783	1			T2	25		T3	3		T4	2
valid_sources[0x0a]	74841	1			T2	32		T3	4		T4	1
valid_sources[0x0b]	10838	1			T2	19		T4	2		T10	8
valid_sources[0x0c]	10630	1			T2	20		T3	1		T7	1
valid_sources[0x0d]	10954	1			T2	20		T3	1		T9	6
valid_sources[0x0e]	11453	1			T2	41		T3	1		T4	8
valid_sources[0x0f]	12621	1			T2	24		T3	3		T4	10
valid_sources[0x10]	10677	1			T2	22		T4	4		T9	5
valid_sources[0x11]	10580	1			T2	30		T4	1		T9	6
valid_sources[0x12]	10427	1			T2	29		T3	1		T4	1
valid_sources[0x13]	12121	1			T2	25		T4	3		T10	1
valid_sources[0x14]	11307	1			T2	17		T3	1		T4	1
valid_sources[0x15]	11168	1			T2	23		T3	2		T4	2
valid_sources[0x16]	13557	1			T2	10		T3	1		T4	4
valid_sources[0x17]	11002	1			T2	33		T3	2		T7	1
valid_sources[0x18]	10896	1			T2	19		T4	3		T10	3
valid_sources[0x19]	12101	1			T2	36		T3	1		T4	4
valid_sources[0x1a]	10963	1			T2	19		T3	1		T4	3
valid_sources[0x1b]	13506	1			T2	35		T3	3		T4	3
valid_sources[0x1c]	10690	1			T2	18		T3	1		T4	5
valid_sources[0x1d]	10990	1			T2	36		T3	2		T4	4
valid_sources[0x1e]	13820	1			T2	37		T3	1		T4	9
valid_sources[0x1f]	10420	1			T2	24		T3	2		T10	6
valid_sources[0x20]	10705	1			T2	37		T3	3		T4	3
valid_sources[0x21]	10338	1			T2	29		T3	3		T4	2
valid_sources[0x22]	12443	1			T2	20		T3	1		T4	5
valid_sources[0x23]	10860	1			T2	20		T3	1		T4	6
valid_sources[0x24]	11045	1			T2	32		T4	14		T10	8
valid_sources[0x25]	15311	1			T2	31		T4	1		T7	2
valid_sources[0x26]	10817	1			T2	21		T3	1		T7	1
valid_sources[0x27]	10703	1			T2	26		T3	6		T4	1
valid_sources[0x28]	10633	1			T2	24		T4	4		T10	1
valid_sources[0x29]	11164	1			T2	12		T9	1		T10	5
valid_sources[0x2a]	10793	1			T2	17		T3	1		T10	5
valid_sources[0x2b]	11713	1			T2	28		T3	1		T4	1
valid_sources[0x2c]	15759	1			T2	22		T3	4		T4	6
valid_sources[0x2d]	10494	1			T2	29		T3	3		T4	7
valid_sources[0x2e]	10916	1			T2	24		T3	3		T4	3
valid_sources[0x2f]	10913	1			T2	21		T4	7		T7	1
valid_sources[0x30]	10832	1			T2	19		T4	1		T9	12
valid_sources[0x31]	11837	1			T2	30		T3	1		T4	1
valid_sources[0x32]	27491	1			T2	25		T3	4		T4	2
valid_sources[0x33]	10790	1			T2	26		T4	3		T7	1
valid_sources[0x34]	11150	1			T2	24		T3	1		T4	7
valid_sources[0x35]	10711	1			T2	35		T3	5		T4	1
valid_sources[0x36]	13108	1			T2	31		T3	3		T4	3
valid_sources[0x37]	11084	1			T2	22		T4	2		T10	3
valid_sources[0x38]	11068	1			T2	42		T7	6		T10	4
valid_sources[0x39]	10567	1			T2	29		T3	3		T10	7
valid_sources[0x3a]	15513	1			T2	36		T4	2		T10	3
valid_sources[0x3b]	10730	1			T2	20		T4	1		T7	5
valid_sources[0x3c]	12363	1			T2	24		T3	3		T4	2
valid_sources[0x3d]	10935	1			T2	20		T10	4		T12	5
valid_sources[0x3e]	10945	1			T2	28		T3	1		T4	7
valid_sources[0x3f]	12444	1			T2	28		T3	3		T10	1
valid_sources[0x40]	10584	1			T2	32		T3	1		T4	4
valid_sources[0x41]	13105	1			T2	19		T3	4		T4	2
valid_sources[0x42]	10438	1			T2	20		T3	1		T4	2
valid_sources[0x43]	11052	1			T2	19		T3	3		T4	7
valid_sources[0x44]	10819	1			T2	19		T4	2		T7	8
valid_sources[0x45]	11250	1			T2	35		T4	1		T7	2
valid_sources[0x46]	18729	1			T2	34		T3	2		T4	5
valid_sources[0x47]	10444	1			T2	22		T3	2		T4	3
valid_sources[0x48]	10795	1			T2	29		T3	1		T4	3
valid_sources[0x49]	13594	1			T2	16		T4	1		T9	1
valid_sources[0x4a]	10740	1			T2	19		T4	4		T10	4
valid_sources[0x4b]	16907	1			T2	28		T3	3		T4	1
valid_sources[0x4c]	10669	1			T2	31		T3	6		T4	3
valid_sources[0x4d]	10411	1			T2	26		T4	4		T7	2
valid_sources[0x4e]	14200	1			T2	24		T4	3		T7	2
valid_sources[0x4f]	10551	1			T2	37		T3	2		T4	12
valid_sources[0x50]	11001	1			T2	29		T4	8		T9	14
valid_sources[0x51]	10791	1			T2	26		T3	2		T4	4
valid_sources[0x52]	10999	1			T2	21		T3	4		T4	4
valid_sources[0x53]	11706	1			T2	29		T3	4		T9	6
valid_sources[0x54]	13026	1			T2	19		T3	7		T4	5
valid_sources[0x55]	11176	1			T2	22		T3	1		T4	3
valid_sources[0x56]	10769	1			T2	18		T3	2		T9	5
valid_sources[0x57]	12675	1			T2	27		T3	2		T4	1
valid_sources[0x58]	95211	1			T2	27		T3	1		T4	10
valid_sources[0x59]	10652	1			T2	31		T7	2		T9	1
valid_sources[0x5a]	11555	1			T2	22		T4	6		T10	5
valid_sources[0x5b]	10918	1			T2	28		T4	3		T10	8
valid_sources[0x5c]	11114	1			T2	22		T4	3		T7	1
valid_sources[0x5d]	37218	1			T2	26		T3	1		T10	4
valid_sources[0x5e]	10244	1			T2	30		T3	2		T7	7
valid_sources[0x5f]	13317	1			T2	11		T3	1		T4	5
valid_sources[0x60]	14193	1			T2	17		T3	3		T4	2
valid_sources[0x61]	11042	1			T2	29		T3	3		T4	1
valid_sources[0x62]	10799	1			T2	20		T4	1		T10	2
valid_sources[0x63]	11734	1			T2	35		T3	1		T4	4
valid_sources[0x64]	12541	1			T2	26		T4	1		T9	1
valid_sources[0x65]	10978	1			T2	19		T3	1		T9	1
valid_sources[0x66]	11072	1			T2	19		T4	1		T10	3
valid_sources[0x67]	10627	1			T2	26		T3	1		T7	1
valid_sources[0x68]	22930	1			T2	27		T3	2		T4	4
valid_sources[0x69]	12015	1			T2	22		T3	1		T4	1
valid_sources[0x6a]	11226	1			T2	25		T4	2		T7	1
valid_sources[0x6b]	10693	1			T2	28		T9	4		T10	11
valid_sources[0x6c]	11055	1			T2	20		T3	3		T7	1
valid_sources[0x6d]	10827	1			T2	25		T10	2		T14	5
valid_sources[0x6e]	10685	1			T2	28		T10	7		T12	1
valid_sources[0x6f]	10423	1			T2	28		T3	2		T4	2
valid_sources[0x70]	10524	1			T2	21		T3	1		T4	1
valid_sources[0x71]	14189	1			T2	30		T3	1		T7	20
valid_sources[0x72]	10840	1			T2	28		T4	2		T7	4
valid_sources[0x73]	11738	1			T2	31		T3	1		T9	3
valid_sources[0x74]	14279	1			T2	21		T4	1		T10	6
valid_sources[0x75]	10929	1			T2	17		T4	1		T7	3
valid_sources[0x76]	10548	1			T2	25		T4	2		T7	1
valid_sources[0x77]	11018	1			T2	21		T3	5		T4	8
valid_sources[0x78]	10665	1			T2	32		T4	1		T7	1
valid_sources[0x79]	11096	1			T2	27		T3	1		T4	2
valid_sources[0x7a]	12545	1			T2	17		T3	7		T4	3
valid_sources[0x7b]	14144	1			T2	19		T3	2		T4	2
valid_sources[0x7c]	10926	1			T2	20		T3	2		T12	2
valid_sources[0x7d]	10403	1			T2	20		T3	1		T10	6
valid_sources[0x7e]	10788	1			T2	26		T4	1		T9	45
valid_sources[0x7f]	12602	1			T2	23		T3	1		T4	8
valid_sources[0x80]	10935	1			T2	25		T3	2		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1531062

1

T2

2274

T3

83

T4

195

values[0x0]

all_enables

biggest_size

133359

1

T2

712

T3

49

T4

116

values[0x1]

all_enables

biggest_size

132157

1

T2

666

T3

57

T4

129