Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	101356552	13833	0	0
claim_transition_if_regwen_rd_A	101356552	1117	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101356552	13833	0	0
T17	448032	13	0	0
T18	247519	0	0	0
T19	163334	0	0	0
T29	995	0	0	0
T30	911	0	0	0
T40	35658	0	0	0
T41	0	2	0	0
T47	29299	0	0	0
T48	26942	0	0	0
T63	1506	0	0	0
T75	33979	0	0	0
T79	0	4	0	0
T94	0	3	0	0
T95	0	2	0	0
T96	0	7	0	0
T140	0	1	0	0
T141	0	14	0	0
T142	0	7	0	0
T143	0	6	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101356552	1117	0	0
T93	31476	0	0	0
T95	0	1	0	0
T97	0	8	0	0
T99	0	33	0	0
T106	0	38	0	0
T140	233880	3	0	0
T144	0	14	0	0
T145	0	10	0	0
T146	0	11	0	0
T147	0	8	0	0
T148	0	7	0	0
T149	2743	0	0	0
T150	51329	0	0	0
T151	210777	0	0	0
T152	1139	0	0	0
T153	5359	0	0	0
T154	8012	0	0	0
T155	6639	0	0	0
T156	1446	0	0	0