Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1656490	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1870965

1

T1

639

T2

36223

T3

100

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3192639	1			T1	529		T2	69229		T3	124
values[0x0]	166910	1			T1	250		T2	759		T3	35
values[0x1]	167906	1			T1	238		T2	767		T3	17

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1315633	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2211822

1

T1

725

T2

43253

T3

115

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11477	1			T1	2		T14	5		T15	4
valid_sources[0x01]	11513	1			T3	1		T14	2		T15	5
valid_sources[0x02]	13454	1			T1	1		T3	3		T10	1
valid_sources[0x03]	11323	1			T1	2		T3	1		T15	10
valid_sources[0x04]	11883	1			T1	7		T14	3		T15	6
valid_sources[0x05]	11788	1			T1	2		T3	1		T10	3
valid_sources[0x06]	12209	1			T1	5		T14	2		T15	5
valid_sources[0x07]	11511	1			T1	2		T3	1		T15	2
valid_sources[0x08]	11500	1			T14	4		T15	4		T5	128
valid_sources[0x09]	20895	1			T15	7		T5	140		T40	2
valid_sources[0x0a]	11377	1			T1	2		T15	3		T5	147
valid_sources[0x0b]	11452	1			T1	2		T15	5		T5	164
valid_sources[0x0c]	12187	1			T1	6		T3	1		T15	7
valid_sources[0x0d]	12674	1			T1	1		T14	1		T15	6
valid_sources[0x0e]	11461	1			T1	1		T3	1		T15	3
valid_sources[0x0f]	11386	1			T1	3		T15	4		T5	139
valid_sources[0x10]	12286	1			T15	4		T5	153		T40	5
valid_sources[0x11]	13198	1			T3	1		T15	9		T5	142
valid_sources[0x12]	11438	1			T1	1		T3	3		T15	6
valid_sources[0x13]	12202	1			T1	1		T15	2		T5	111
valid_sources[0x14]	11673	1			T1	11		T3	1		T13	1
valid_sources[0x15]	11812	1			T1	7		T10	1		T11	386
valid_sources[0x16]	11933	1			T1	10		T15	5		T5	166
valid_sources[0x17]	11806	1			T1	6		T15	4		T5	109
valid_sources[0x18]	11793	1			T1	1		T3	1		T15	9
valid_sources[0x19]	11427	1			T3	1		T10	2		T15	5
valid_sources[0x1a]	23992	1			T3	1		T15	5		T5	159
valid_sources[0x1b]	60500	1			T1	5		T2	47960		T15	6
valid_sources[0x1c]	11890	1			T1	3		T14	4		T15	6
valid_sources[0x1d]	11752	1			T1	10		T13	1		T15	6
valid_sources[0x1e]	18805	1			T1	3		T15	4		T5	134
valid_sources[0x1f]	12884	1			T3	2		T10	1		T15	5
valid_sources[0x20]	12180	1			T1	6		T3	1		T15	4
valid_sources[0x21]	11584	1			T1	6		T3	3		T15	4
valid_sources[0x22]	13927	1			T3	1		T15	4		T5	124
valid_sources[0x23]	12729	1			T1	6		T3	1		T14	3
valid_sources[0x24]	12512	1			T1	6		T14	2		T15	2
valid_sources[0x25]	11759	1			T1	6		T3	1		T15	5
valid_sources[0x26]	11516	1			T1	4		T3	1		T14	1
valid_sources[0x27]	12933	1			T1	7		T15	8		T5	149
valid_sources[0x28]	11606	1			T3	1		T15	5		T5	119
valid_sources[0x29]	25824	1			T1	2		T14	7		T15	4
valid_sources[0x2a]	11250	1			T1	2		T3	1		T14	2
valid_sources[0x2b]	11518	1			T1	3		T3	1		T14	2
valid_sources[0x2c]	11774	1			T3	1		T15	9		T5	119
valid_sources[0x2d]	12032	1			T1	1		T15	5		T5	126
valid_sources[0x2e]	12649	1			T1	7		T3	1		T15	6
valid_sources[0x2f]	18027	1			T1	4		T3	1		T15	3
valid_sources[0x30]	11625	1			T1	6		T3	3		T13	1
valid_sources[0x31]	15179	1			T1	5		T14	2		T15	7
valid_sources[0x32]	16869	1			T3	1		T15	3		T5	121
valid_sources[0x33]	11628	1			T3	1		T13	1		T15	4
valid_sources[0x34]	11801	1			T15	3		T5	138		T40	2
valid_sources[0x35]	11774	1			T15	3		T5	139		T40	3
valid_sources[0x36]	12027	1			T1	12		T15	8		T5	131
valid_sources[0x37]	11799	1			T1	10		T14	3		T15	5
valid_sources[0x38]	12838	1			T1	7		T15	7		T5	147
valid_sources[0x39]	11487	1			T1	4		T15	7		T5	132
valid_sources[0x3a]	14142	1			T1	5		T15	5		T5	141
valid_sources[0x3b]	11815	1			T1	3		T14	6		T15	5
valid_sources[0x3c]	11597	1			T1	5		T3	2		T15	14
valid_sources[0x3d]	11809	1			T1	1		T14	3		T15	5
valid_sources[0x3e]	11468	1			T1	5		T3	2		T15	2
valid_sources[0x3f]	11796	1			T1	10		T15	2		T5	145
valid_sources[0x40]	11880	1			T3	1		T15	10		T5	151
valid_sources[0x41]	12929	1			T1	1		T3	1		T15	6
valid_sources[0x42]	11698	1			T1	8		T13	1		T14	2
valid_sources[0x43]	32232	1			T1	4		T10	3		T15	8
valid_sources[0x44]	11387	1			T1	8		T15	5		T5	121
valid_sources[0x45]	11426	1			T3	1		T15	10		T5	134
valid_sources[0x46]	12778	1			T1	2		T3	1		T14	1
valid_sources[0x47]	11517	1			T1	11		T3	2		T5	118
valid_sources[0x48]	12518	1			T1	3		T3	1		T14	8
valid_sources[0x49]	11810	1			T1	3		T15	3		T5	138
valid_sources[0x4a]	12191	1			T1	1		T3	2		T13	1
valid_sources[0x4b]	11585	1			T1	1		T15	9		T5	147
valid_sources[0x4c]	21958	1			T1	1		T3	1		T15	3
valid_sources[0x4d]	11767	1			T14	3		T15	5		T5	145
valid_sources[0x4e]	11428	1			T1	6		T10	1		T15	6
valid_sources[0x4f]	11771	1			T1	1		T15	5		T5	139
valid_sources[0x50]	11491	1			T1	2		T3	1		T15	3
valid_sources[0x51]	11923	1			T1	2		T3	1		T13	1
valid_sources[0x52]	11604	1			T1	3		T15	11		T5	127
valid_sources[0x53]	12682	1			T1	4		T3	3		T14	4
valid_sources[0x54]	11642	1			T3	1		T15	6		T5	127
valid_sources[0x55]	11808	1			T1	5		T15	10		T5	137
valid_sources[0x56]	11614	1			T1	31		T3	2		T10	1
valid_sources[0x57]	12222	1			T3	1		T15	6		T5	151
valid_sources[0x58]	11388	1			T1	1		T15	3		T5	139
valid_sources[0x59]	11412	1			T3	2		T15	5		T5	106
valid_sources[0x5a]	11849	1			T1	1		T3	1		T15	4
valid_sources[0x5b]	13624	1			T1	3		T15	4		T5	141
valid_sources[0x5c]	11847	1			T1	5		T15	1		T5	111
valid_sources[0x5d]	23280	1			T12	2249		T15	3		T16	2099
valid_sources[0x5e]	11773	1			T1	4		T3	1		T15	5
valid_sources[0x5f]	11438	1			T1	2		T14	2		T15	2
valid_sources[0x60]	11695	1			T1	8		T15	4		T5	145
valid_sources[0x61]	12700	1			T1	14		T3	1		T15	3
valid_sources[0x62]	11178	1			T1	4		T15	11		T5	110
valid_sources[0x63]	11856	1			T1	7		T15	11		T5	129
valid_sources[0x64]	12780	1			T1	1		T15	4		T5	123
valid_sources[0x65]	23516	1			T15	2		T5	145		T40	5
valid_sources[0x66]	13369	1			T3	2		T14	4		T15	2
valid_sources[0x67]	11587	1			T1	9		T3	1		T10	1
valid_sources[0x68]	11377	1			T1	2		T15	4		T5	154
valid_sources[0x69]	11349	1			T1	21		T3	2		T15	7
valid_sources[0x6a]	12614	1			T1	5		T15	3		T5	129
valid_sources[0x6b]	11670	1			T1	3		T14	2		T15	3
valid_sources[0x6c]	11667	1			T15	6		T5	156		T40	3
valid_sources[0x6d]	12365	1			T1	2		T15	8		T5	141
valid_sources[0x6e]	11841	1			T1	6		T3	1		T15	5
valid_sources[0x6f]	11453	1			T3	1		T10	1		T15	8
valid_sources[0x70]	13690	1			T1	4		T13	1		T15	3
valid_sources[0x71]	12987	1			T1	4		T3	2		T14	4
valid_sources[0x72]	11182	1			T1	2		T3	1		T15	7
valid_sources[0x73]	11299	1			T1	14		T15	9		T5	144
valid_sources[0x74]	11679	1			T1	1		T15	6		T5	128
valid_sources[0x75]	12104	1			T1	4		T3	3		T15	4
valid_sources[0x76]	11620	1			T1	2		T3	1		T15	6
valid_sources[0x77]	11551	1			T1	4		T15	5		T5	119
valid_sources[0x78]	14172	1			T1	2		T15	7		T5	117
valid_sources[0x79]	13174	1			T1	5		T3	1		T15	6
valid_sources[0x7a]	12144	1			T1	4		T3	1		T15	4
valid_sources[0x7b]	15046	1			T1	8		T3	2		T14	11
valid_sources[0x7c]	11434	1			T1	6		T3	1		T15	13
valid_sources[0x7d]	12283	1			T1	2		T14	2		T15	3
valid_sources[0x7e]	12606	1			T1	9		T3	1		T14	2
valid_sources[0x7f]	14986	1			T1	5		T3	2		T15	2
valid_sources[0x80]	11695	1			T3	1		T14	9		T15	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1582620

1

T1

208

T2

34893

T3

57

values[0x0]

all_enables

biggest_size

144644

1

T1

218

T2

659

T3

28

values[0x1]

all_enables

biggest_size

143701

1

T1

213

T2

671

T3

15