Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	100185342	14912	0	0
claim_transition_if_regwen_rd_A	100185342	1563	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100185342	14912	0	0
T2	142186	3	0	0
T3	2910	0	0	0
T4	35114	0	0	0
T10	1817	0	0	0
T11	4945	0	0	0
T12	42084	0	0	0
T13	1696	0	0	0
T14	4065	0	0	0
T15	25347	0	0	0
T16	30213	0	0	0
T18	0	11	0	0
T19	0	11	0	0
T20	0	4	0	0
T47	0	6	0	0
T64	0	8	0	0
T95	0	1	0	0
T100	0	15	0	0
T132	0	2	0	0
T133	0	6	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100185342	1563	0	0
T95	464983	7	0	0
T98	0	63	0	0
T99	0	38	0	0
T103	0	8	0	0
T113	0	62	0	0
T134	0	4	0	0
T135	0	27	0	0
T136	0	11	0	0
T137	0	27	0	0
T138	0	6	0	0
T139	1328	0	0	0
T140	46888	0	0	0
T141	132387	0	0	0
T142	382098	0	0	0
T143	52014	0	0	0
T144	5115	0	0	0
T145	24540	0	0	0
T146	23983	0	0	0
T147	37319	0	0	0