Unified Coverage Report :: Module :: lc_ctrl_state_decode

Module : lc_ctrl_state_decode

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	100.00			96.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_decode.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_decode	98.89	100.00	100.00			96.67

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_decode

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	100.00			96.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	100.00			96.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.77	98.87	93.02		100.00	98.63	93.33	u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sec_anchor_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : lc_ctrl_state_decode

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	52	10	10	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_decode.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_decode.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	6	6
52	1	1
53	1	1
54	1	1
55	1	1
57	1	1
59	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
			MISSING_ELSE

---

Cond Coverage for Module : lc_ctrl_state_decode

	Total	Covered	Percent
Conditions	7	7	100.00
Logical	7	7	100.00
Non-Logical	0	0
Event	0	0

 LINE       143
 EXPRESSION ((lc_state_i != LcStRaw) && (lc_cnt_i == LcCnt0))
             -----------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T12,T5,T40
1	0	Covered	T1,T2,T3
1	1	Covered	T94,T95,T96

 LINE       143
 SUB-EXPRESSION (lc_state_i != LcStRaw)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       143
 SUB-EXPRESSION (lc_cnt_i == LcCnt0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T5,T40

---

Branch Coverage for Module : lc_ctrl_state_decode

	Line No.	Total	Covered	Percent
Branches		60	58	96.67
CASE	57	60	58	96.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_decode.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_decode.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	57	case (fsm_state_i)
-2-:	75	case (lc_state_i)
-3-:	101	case (lc_cnt_i)
-4-:	132	case (secrets_valid_i)
-5-:	143	if (((lc_state_i != LcStRaw) && (lc_cnt_i == LcCnt0)))
-6-:	150	if ((lc_ctrl_pkg::lc_tx_test_true_strict(secrets_valid_i) && (!(lc_state_i inside {LcStDev, LcStProd, LcStProdEnd, LcStRma, LcStScrap}))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
ResetSt	-	-	-	-	-	Covered	T1,T2,T3
EscalateSt	-	-	-	-	-	Covered	T1,T2,T11
PostTransSt	-	-	-	-	-	Covered	T2,T3,T11
InvalidSt	-	-	-	-	-	Covered	T1,T2,T11
ScrapSt	-	-	-	-	-	Covered	T2,T5,T40
default	LcStRaw	-	-	-	-	Covered	T1,T2,T3
default	LcStTestUnlocked0	-	-	-	-	Covered	T1,T2,T12
default	LcStTestLocked0	-	-	-	-	Covered	T1,T2,T12
default	LcStTestUnlocked1	-	-	-	-	Covered	T1,T2,T11
default	LcStTestLocked1	-	-	-	-	Covered	T1,T2,T12
default	LcStTestUnlocked2	-	-	-	-	Covered	T1,T2,T11
default	LcStTestLocked2	-	-	-	-	Covered	T1,T2,T4
default	LcStTestUnlocked3	-	-	-	-	Covered	T1,T2,T12
default	LcStTestLocked3	-	-	-	-	Covered	T2,T3,T12
default	LcStTestUnlocked4	-	-	-	-	Covered	T1,T2,T11
default	LcStTestLocked4	-	-	-	-	Covered	T1,T2,T3
default	LcStTestUnlocked5	-	-	-	-	Covered	T1,T2,T4
default	LcStTestLocked5	-	-	-	-	Covered	T1,T2,T4
default	LcStTestUnlocked6	-	-	-	-	Covered	T1,T2,T4
default	LcStTestLocked6	-	-	-	-	Covered	T1,T2,T12
default	LcStTestUnlocked7	-	-	-	-	Covered	T1,T2,T11
default	LcStDev	-	-	-	-	Covered	T2,T3,T4
default	LcStProd	-	-	-	-	Covered	T1,T2,T11
default	LcStProdEnd	-	-	-	-	Covered	T1,T2,T3
default	LcStRma	-	-	-	-	Covered	T1,T2,T11
default	LcStScrap	-	-	-	-	Covered	T2,T5,T40
default	default	-	-	-	-	Covered	T1,T2,T11
default	-	LcCnt0	-	-	-	Covered	T12,T5,T40
default	-	LcCnt1	-	-	-	Covered	T1,T2,T4
default	-	LcCnt2	-	-	-	Covered	T1,T2,T11
default	-	LcCnt3	-	-	-	Covered	T1,T2,T3
default	-	LcCnt4	-	-	-	Covered	T2,T4,T12
default	-	LcCnt5	-	-	-	Covered	T1,T2,T4
default	-	LcCnt6	-	-	-	Covered	T1,T2,T11
default	-	LcCnt7	-	-	-	Covered	T1,T2,T4
default	-	LcCnt8	-	-	-	Covered	T1,T2,T3
default	-	LcCnt9	-	-	-	Covered	T1,T2,T4
default	-	LcCnt10	-	-	-	Covered	T2,T11,T12
default	-	LcCnt11	-	-	-	Covered	T1,T2,T3
default	-	LcCnt12	-	-	-	Covered	T1,T2,T12
default	-	LcCnt13	-	-	-	Covered	T1,T2,T11
default	-	LcCnt14	-	-	-	Covered	T1,T2,T3
default	-	LcCnt15	-	-	-	Covered	T1,T2,T11
default	-	LcCnt16	-	-	-	Covered	T1,T2,T12
default	-	LcCnt17	-	-	-	Covered	T1,T2,T14
default	-	LcCnt18	-	-	-	Covered	T1,T2,T12
default	-	LcCnt19	-	-	-	Covered	T1,T2,T4
default	-	LcCnt20	-	-	-	Covered	T1,T2,T4
default	-	LcCnt21	-	-	-	Covered	T1,T2,T11
default	-	LcCnt22	-	-	-	Covered	T1,T2,T3
default	-	LcCnt23	-	-	-	Covered	T1,T2,T4
default	-	LcCnt24	-	-	-	Covered	T2,T5,T40
default	-	default	-	-	-	Covered	T1,T2,T11
default	-	-	Off	-	-	Covered	T1,T2,T3
default	-	-	On	-	-	Not Covered
default	-	-	default	-	-	Covered	T33,T67,T48
default	-	-	-	1	-	Covered	T94,T95,T96
default	-	-	-	0	-	Covered	T1,T2,T3
default	-	-	-	-	1	Not Covered
default	-	-	-	-	0	Covered	T1,T2,T3