Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50288 |
1 |
|
|
T1 |
53 |
|
T2 |
91 |
|
T3 |
56 |
auto[1] |
1625 |
1 |
|
|
T2 |
9 |
|
T5 |
8 |
|
T45 |
14 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51251 |
1 |
|
|
T1 |
36 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
662 |
1 |
|
|
T1 |
17 |
|
T15 |
8 |
|
T56 |
13 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50023 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
1890 |
1 |
|
|
T17 |
4 |
|
T60 |
1 |
|
T20 |
47 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50009 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
1904 |
1 |
|
|
T4 |
1 |
|
T17 |
9 |
|
T60 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50063 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
1850 |
1 |
|
|
T5 |
3 |
|
T17 |
6 |
|
T20 |
42 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
47124 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
no_err_inj |
4789 |
1 |
|
|
T4 |
8 |
|
T5 |
50 |
|
T19 |
7 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50259 |
1 |
|
|
T1 |
53 |
|
T2 |
93 |
|
T3 |
56 |
auto[1] |
1654 |
1 |
|
|
T2 |
7 |
|
T5 |
6 |
|
T45 |
4 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51247 |
1 |
|
|
T1 |
43 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
666 |
1 |
|
|
T1 |
10 |
|
T15 |
12 |
|
T56 |
10 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36399 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
15514 |
1 |
|
|
T4 |
14 |
|
T5 |
29 |
|
T6 |
2 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50100 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
1813 |
1 |
|
|
T4 |
1 |
|
T17 |
6 |
|
T60 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49923 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
1990 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T17 |
11 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50051 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
1862 |
1 |
|
|
T4 |
1 |
|
T17 |
5 |
|
T20 |
41 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50267 |
1 |
|
|
T1 |
53 |
|
T2 |
83 |
|
T3 |
56 |
auto[1] |
1646 |
1 |
|
|
T2 |
17 |
|
T5 |
10 |
|
T45 |
10 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49304 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
2609 |
1 |
|
|
T26 |
15 |
|
T20 |
20 |
|
T58 |
39 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51221 |
1 |
|
|
T1 |
45 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
692 |
1 |
|
|
T1 |
8 |
|
T15 |
9 |
|
T56 |
14 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51260 |
1 |
|
|
T1 |
43 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
653 |
1 |
|
|
T1 |
10 |
|
T15 |
11 |
|
T56 |
11 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51297 |
1 |
|
|
T1 |
45 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
616 |
1 |
|
|
T1 |
8 |
|
T15 |
10 |
|
T56 |
11 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49091 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
2822 |
1 |
|
|
T4 |
14 |
|
T5 |
12 |
|
T60 |
13 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48184 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
3729 |
1 |
|
|
T18 |
94 |
|
T50 |
72 |
|
T64 |
50 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49973 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
1940 |
1 |
|
|
T17 |
8 |
|
T60 |
1 |
|
T92 |
2 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50055 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
1858 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T17 |
16 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50017 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[1] |
1896 |
1 |
|
|
T4 |
1 |
|
T17 |
13 |
|
T60 |
1 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50195 |
1 |
|
|
T1 |
53 |
|
T2 |
87 |
|
T3 |
56 |
auto[1] |
1718 |
1 |
|
|
T2 |
13 |
|
T5 |
2 |
|
T45 |
5 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46594 |
1 |
|
|
T1 |
53 |
|
T2 |
85 |
|
T3 |
56 |
auto[1] |
5319 |
1 |
|
|
T2 |
15 |
|
T12 |
54 |
|
T5 |
5 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48354 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T12 |
54 |
auto[1] |
3559 |
1 |
|
|
T3 |
56 |
|
T62 |
98 |
|
T63 |
90 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51913 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50323 |
1 |
|
|
T1 |
53 |
|
T2 |
89 |
|
T3 |
56 |
auto[1] |
1590 |
1 |
|
|
T2 |
11 |
|
T5 |
7 |
|
T45 |
8 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50190 |
1 |
|
|
T1 |
53 |
|
T2 |
88 |
|
T3 |
56 |
auto[1] |
1723 |
1 |
|
|
T2 |
12 |
|
T5 |
3 |
|
T45 |
9 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50253 |
1 |
|
|
T1 |
53 |
|
T2 |
84 |
|
T3 |
56 |
auto[1] |
1660 |
1 |
|
|
T2 |
16 |
|
T5 |
6 |
|
T45 |
9 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
45701 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[0] |
no_err_inj |
3390 |
1 |
|
|
T5 |
43 |
|
T19 |
7 |
|
T6 |
2 |
auto[1] |
err_inj |
1423 |
1 |
|
|
T4 |
6 |
|
T5 |
5 |
|
T60 |
7 |
auto[1] |
no_err_inj |
1399 |
1 |
|
|
T4 |
8 |
|
T5 |
7 |
|
T60 |
6 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47403 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[0] |
auto[1] |
1688 |
1 |
|
|
T17 |
16 |
|
T20 |
28 |
|
T58 |
50 |
auto[1] |
auto[0] |
2652 |
1 |
|
|
T4 |
13 |
|
T5 |
11 |
|
T60 |
11 |
auto[1] |
auto[1] |
170 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T60 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47268 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[0] |
auto[1] |
1823 |
1 |
|
|
T17 |
11 |
|
T20 |
41 |
|
T58 |
53 |
auto[1] |
auto[0] |
2655 |
1 |
|
|
T4 |
13 |
|
T5 |
11 |
|
T60 |
13 |
auto[1] |
auto[1] |
167 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T92 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47341 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[0] |
auto[1] |
1750 |
1 |
|
|
T17 |
13 |
|
T20 |
37 |
|
T58 |
60 |
auto[1] |
auto[0] |
2676 |
1 |
|
|
T4 |
13 |
|
T5 |
12 |
|
T60 |
12 |
auto[1] |
auto[1] |
146 |
1 |
|
|
T4 |
1 |
|
T60 |
1 |
|
T20 |
3 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47355 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[0] |
auto[1] |
1736 |
1 |
|
|
T17 |
9 |
|
T20 |
46 |
|
T58 |
62 |
auto[1] |
auto[0] |
2654 |
1 |
|
|
T4 |
13 |
|
T5 |
12 |
|
T60 |
12 |
auto[1] |
auto[1] |
168 |
1 |
|
|
T4 |
1 |
|
T60 |
1 |
|
T92 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47386 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[0] |
auto[1] |
1705 |
1 |
|
|
T17 |
6 |
|
T20 |
38 |
|
T58 |
59 |
auto[1] |
auto[0] |
2677 |
1 |
|
|
T4 |
14 |
|
T5 |
9 |
|
T60 |
13 |
auto[1] |
auto[1] |
145 |
1 |
|
|
T5 |
3 |
|
T20 |
4 |
|
T58 |
3 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47347 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[0] |
auto[1] |
1744 |
1 |
|
|
T17 |
4 |
|
T20 |
44 |
|
T58 |
47 |
auto[1] |
auto[0] |
2676 |
1 |
|
|
T4 |
14 |
|
T5 |
12 |
|
T60 |
12 |
auto[1] |
auto[1] |
146 |
1 |
|
|
T60 |
1 |
|
T20 |
3 |
|
T24 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35465 |
1 |
|
|
T1 |
53 |
|
T2 |
91 |
|
T3 |
56 |
auto[0] |
auto[1] |
934 |
1 |
|
|
T2 |
9 |
|
T5 |
8 |
|
T45 |
14 |
auto[1] |
auto[0] |
14823 |
1 |
|
|
T4 |
14 |
|
T5 |
29 |
|
T6 |
2 |
auto[1] |
auto[1] |
691 |
1 |
|
|
T20 |
2 |
|
T21 |
9 |
|
T22 |
5 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35454 |
1 |
|
|
T1 |
53 |
|
T2 |
93 |
|
T3 |
56 |
auto[0] |
auto[1] |
945 |
1 |
|
|
T2 |
7 |
|
T5 |
6 |
|
T45 |
4 |
auto[1] |
auto[0] |
14805 |
1 |
|
|
T4 |
14 |
|
T5 |
29 |
|
T6 |
2 |
auto[1] |
auto[1] |
709 |
1 |
|
|
T20 |
6 |
|
T21 |
9 |
|
T22 |
12 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34724 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[0] |
auto[1] |
1675 |
1 |
|
|
T26 |
15 |
|
T20 |
20 |
|
T58 |
25 |
auto[1] |
auto[0] |
14580 |
1 |
|
|
T4 |
14 |
|
T5 |
29 |
|
T6 |
2 |
auto[1] |
auto[1] |
934 |
1 |
|
|
T58 |
14 |
|
T209 |
12 |
|
T41 |
19 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35519 |
1 |
|
|
T1 |
53 |
|
T2 |
83 |
|
T3 |
56 |
auto[0] |
auto[1] |
880 |
1 |
|
|
T2 |
17 |
|
T5 |
10 |
|
T45 |
10 |
auto[1] |
auto[0] |
14748 |
1 |
|
|
T4 |
14 |
|
T5 |
29 |
|
T6 |
2 |
auto[1] |
auto[1] |
766 |
1 |
|
|
T20 |
2 |
|
T21 |
10 |
|
T22 |
7 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31799 |
1 |
|
|
T1 |
53 |
|
T2 |
85 |
|
T3 |
56 |
auto[0] |
auto[1] |
4600 |
1 |
|
|
T2 |
15 |
|
T12 |
54 |
|
T5 |
5 |
auto[1] |
auto[0] |
14795 |
1 |
|
|
T4 |
14 |
|
T5 |
29 |
|
T6 |
2 |
auto[1] |
auto[1] |
719 |
1 |
|
|
T20 |
4 |
|
T21 |
19 |
|
T22 |
10 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35281 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[0] |
auto[1] |
1118 |
1 |
|
|
T5 |
1 |
|
T17 |
16 |
|
T60 |
2 |
auto[1] |
auto[0] |
14774 |
1 |
|
|
T4 |
13 |
|
T5 |
29 |
|
T6 |
2 |
auto[1] |
auto[1] |
740 |
1 |
|
|
T4 |
1 |
|
T20 |
21 |
|
T58 |
17 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35212 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[0] |
auto[1] |
1187 |
1 |
|
|
T17 |
8 |
|
T60 |
1 |
|
T92 |
2 |
auto[1] |
auto[0] |
14761 |
1 |
|
|
T4 |
14 |
|
T5 |
29 |
|
T6 |
2 |
auto[1] |
auto[1] |
753 |
1 |
|
|
T20 |
30 |
|
T23 |
1 |
|
T58 |
26 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35174 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[0] |
auto[1] |
1225 |
1 |
|
|
T5 |
1 |
|
T17 |
11 |
|
T92 |
1 |
auto[1] |
auto[0] |
14749 |
1 |
|
|
T4 |
13 |
|
T5 |
29 |
|
T6 |
2 |
auto[1] |
auto[1] |
765 |
1 |
|
|
T4 |
1 |
|
T20 |
24 |
|
T23 |
1 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35323 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[0] |
auto[1] |
1076 |
1 |
|
|
T17 |
6 |
|
T60 |
1 |
|
T92 |
3 |
auto[1] |
auto[0] |
14777 |
1 |
|
|
T4 |
13 |
|
T5 |
29 |
|
T6 |
2 |
auto[1] |
auto[1] |
737 |
1 |
|
|
T4 |
1 |
|
T20 |
26 |
|
T23 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35198 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[0] |
auto[1] |
1201 |
1 |
|
|
T17 |
9 |
|
T60 |
1 |
|
T92 |
1 |
auto[1] |
auto[0] |
14811 |
1 |
|
|
T4 |
13 |
|
T5 |
29 |
|
T6 |
2 |
auto[1] |
auto[1] |
703 |
1 |
|
|
T4 |
1 |
|
T20 |
33 |
|
T58 |
17 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35260 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[0] |
auto[1] |
1139 |
1 |
|
|
T17 |
4 |
|
T60 |
1 |
|
T20 |
21 |
auto[1] |
auto[0] |
14763 |
1 |
|
|
T4 |
14 |
|
T5 |
29 |
|
T6 |
2 |
auto[1] |
auto[1] |
751 |
1 |
|
|
T20 |
26 |
|
T24 |
2 |
|
T58 |
18 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35474 |
1 |
|
|
T1 |
53 |
|
T2 |
84 |
|
T3 |
56 |
auto[0] |
auto[1] |
925 |
1 |
|
|
T2 |
16 |
|
T5 |
6 |
|
T45 |
9 |
auto[1] |
auto[0] |
14779 |
1 |
|
|
T4 |
14 |
|
T5 |
29 |
|
T6 |
2 |
auto[1] |
auto[1] |
735 |
1 |
|
|
T20 |
8 |
|
T21 |
12 |
|
T22 |
5 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35426 |
1 |
|
|
T1 |
53 |
|
T2 |
88 |
|
T3 |
56 |
auto[0] |
auto[1] |
973 |
1 |
|
|
T2 |
12 |
|
T5 |
3 |
|
T45 |
9 |
auto[1] |
auto[0] |
14764 |
1 |
|
|
T4 |
14 |
|
T5 |
29 |
|
T6 |
2 |
auto[1] |
auto[1] |
750 |
1 |
|
|
T20 |
3 |
|
T21 |
12 |
|
T22 |
9 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34773 |
1 |
|
|
T1 |
53 |
|
T2 |
100 |
|
T3 |
56 |
auto[0] |
auto[1] |
1626 |
1 |
|
|
T5 |
12 |
|
T60 |
13 |
|
T92 |
15 |
auto[1] |
auto[0] |
14318 |
1 |
|
|
T5 |
29 |
|
T6 |
2 |
|
T20 |
257 |
auto[1] |
auto[1] |
1196 |
1 |
|
|
T4 |
14 |
|
T20 |
11 |
|
T23 |
14 |