Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96078913

1

T1

16066

T2

63870

T3

22810

auto[1]

1381777

1

T1

1386

T2

396

T4

294

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96089260

1

T1

16165

T2

63771

T3

22810

auto[1]

1371430

1

T1

1287

T2

495

T4

98

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6822749	1			T1	4993		T2	8967		T3	5218
auto[IdleSt]	21460942	1			T1	1656		T2	11908		T3	5507
auto[ClkMuxSt]	33904	1			T1	43		T2	100		T3	56
auto[CntIncrSt]	33619	1			T1	43		T2	100		T3	56
auto[CntProgSt]	1536480	1			T1	69		T2	810		T3	112
auto[TransCheckSt]	25882	1			T1	26		T2	79		T3	56
auto[TokenHashSt]	37622332	1			T1	1477		T2	22426		T3	2877
auto[FlashRmaSt]	33864	1			T1	21		T2	38		T3	105
auto[TokenCheck0St]	12160	1			T1	21		T2	24		T3	25
auto[TokenCheck1St]	9130	1			T1	11		T2	18		T3	9
auto[TransProgSt]	412138	1			T1	22		T2	231		T4	275
auto[PostTransSt]	12250174	1			T1	4943		T2	18302		T3	8789
auto[ScrapSt]	109073	1			T5	833		T18	3		T50	6
auto[EscalateSt]	6466525	1			T1	3395		T2	1263		T4	6058
auto[InvalidSt]	10629648	1			T1	732		T4	7157		T15	1596

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2070	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10629648	1			T1	732		T4	7157		T15	1596
EscalateSt	6466525	1			T1	3395		T2	1263		T4	6058
ScrapSt	109073	1			T5	833		T18	3		T50	6
PostTransSt	12250174	1			T1	4943		T2	18302		T3	8789
TransProgSt	412138	1			T1	22		T2	231		T4	275
TokenCheck1St	9130	1			T1	11		T2	18		T3	9
TokenCheck0St	12160	1			T1	21		T2	24		T3	25
FlashRmaSt	33864	1			T1	21		T2	38		T3	105
TokenHashSt	37622332	1			T1	1477		T2	22426		T3	2877
TransCheckSt	25882	1			T1	26		T2	79		T3	56
CntProgSt	1536480	1			T1	69		T2	810		T3	112
CntIncrSt	33619	1			T1	43		T2	100		T3	56
ClkMuxSt	33904	1			T1	43		T2	100		T3	56
IdleSt	21460942	1			T1	1656		T2	11908		T3	5507
ResetSt	6822749	1			T1	4993		T2	8967		T3	5218
arcs[ResetSt=>IdleSt]	52286	1			T1	54		T2	101		T3	57
arcs[IdleSt=>ScrapSt]	287	1			T5	1		T18	1		T50	2
arcs[IdleSt=>ClkMuxSt]	33686	1			T1	43		T2	100		T3	56
arcs[ClkMuxSt=>CntIncrSt]	33619	1			T1	43		T2	100		T3	56
arcs[CntIncrSt=>PostTransSt]	1726	1			T2	12		T5	3		T45	9
arcs[CntIncrSt=>CntProgSt]	31830	1			T1	43		T2	88		T3	56
arcs[CntProgSt=>PostTransSt]	4862	1			T1	17		T2	9		T15	8
arcs[CntProgSt=>TransCheckSt]	25882	1			T1	26		T2	79		T3	56
arcs[TransCheckSt=>PostTransSt]	3436	1			T2	16		T3	23		T5	6
arcs[TransCheckSt=>TokenHashSt]	22339	1			T1	26		T2	63		T3	33
arcs[TokenHashSt=>PostTransSt]	9407	1			T1	5		T2	39		T3	8
arcs[TokenHashSt=>FlashRmaSt]	12259	1			T1	21		T2	24		T3	25
arcs[FlashRmaSt=>TokenCheck0St]	12160	1			T1	21		T2	24		T3	25
arcs[TokenCheck0St=>PostTransSt]	2998	1			T1	10		T2	6		T3	16
arcs[TokenCheck0St=>TokenCheck1St]	9130	1			T1	11		T2	18		T3	9
arcs[TokenCheck1St=>PostTransSt]	632	1			T2	1		T3	9		T5	1
arcs[TransProgSt=>PostTransSt]	7630	1			T1	11		T2	17		T4	8
arcs[IdleSt=>EscalateSt]	173	1			T50	4		T64	5		T46	6
arcs[ClkMuxSt=>EscalateSt]	67	1			T18	3		T50	1		T64	2
arcs[CntIncrSt=>EscalateSt]	63	1			T50	2		T46	2		T65	2
arcs[CntProgSt=>EscalateSt]	1086	1			T18	9		T50	31		T64	16
arcs[TransCheckSt=>EscalateSt]	107	1			T18	9		T46	4		T69	1
arcs[TokenHashSt=>EscalateSt]	673	1			T18	31		T50	8		T64	7
arcs[FlashRmaSt=>EscalateSt]	99	1			T18	3		T50	2		T46	1
arcs[TokenCheck0St=>EscalateSt]	32	1			T50	1		T46	1		T65	2
arcs[TokenCheck1St=>EscalateSt]	158	1			T18	7		T50	1		T64	2
arcs[TransProgSt=>EscalateSt]	710	1			T18	9		T50	12		T64	12
arcs[PostTransSt=>EscalateSt]	5138	1			T1	17		T2	9		T15	8
arcs[InvalidSt=>EscalateSt]	13908	1			T1	10		T4	4		T15	11

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6822568	1			T1	4993		T2	8967		T3	5218
auto[0]	auto[IdleSt]	21460823	1			T1	1656		T2	11908		T3	5507
auto[0]	auto[ClkMuxSt]	33863	1			T1	43		T2	100		T3	56
auto[0]	auto[CntIncrSt]	33581	1			T1	43		T2	100		T3	56
auto[0]	auto[CntProgSt]	1535743	1			T1	69		T2	810		T3	112
auto[0]	auto[TransCheckSt]	25813	1			T1	26		T2	79		T3	56
auto[0]	auto[TokenHashSt]	37621897	1			T1	1477		T2	22426		T3	2877
auto[0]	auto[FlashRmaSt]	33799	1			T1	21		T2	38		T3	105
auto[0]	auto[TokenCheck0St]	12142	1			T1	21		T2	24		T3	25
auto[0]	auto[TokenCheck1St]	9031	1			T1	11		T2	18		T3	9
auto[0]	auto[TransProgSt]	411673	1			T1	22		T2	231		T4	275
auto[0]	auto[PostTransSt]	12247559	1			T1	4935		T2	18298		T3	8789
auto[0]	auto[ScrapSt]	109029	1			T5	833		T18	3		T50	5
auto[0]	auto[EscalateSt]	5096626	1			T1	2023		T2	871		T4	5767
auto[0]	auto[InvalidSt]	10622696	1			T1	726		T4	7154		T15	1593
auto[1]	auto[ResetSt]	181	1			T18	4		T50	4		T64	3
auto[1]	auto[IdleSt]	119	1			T50	4		T64	4		T46	5
auto[1]	auto[ClkMuxSt]	41	1			T18	2		T50	1		T64	2
auto[1]	auto[CntIncrSt]	38	1			T50	1		T46	2		T65	2
auto[1]	auto[CntProgSt]	737	1			T18	8		T50	23		T64	5
auto[1]	auto[TransCheckSt]	69	1			T18	6		T46	3		T69	1
auto[1]	auto[TokenHashSt]	435	1			T18	19		T50	4		T64	5
auto[1]	auto[FlashRmaSt]	65	1			T18	1		T50	1		T46	1
auto[1]	auto[TokenCheck0St]	18	1			T46	1		T65	2		T208	1
auto[1]	auto[TokenCheck1St]	99	1			T18	6		T50	1		T64	1
auto[1]	auto[TransProgSt]	465	1			T18	5		T50	6		T64	8
auto[1]	auto[PostTransSt]	2615	1			T1	8		T2	4		T15	3
auto[1]	auto[ScrapSt]	44	1			T50	1		T46	1		T65	1
auto[1]	auto[EscalateSt]	1369899	1			T1	1372		T2	392		T4	291
auto[1]	auto[InvalidSt]	6952	1			T1	6		T4	3		T15	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6822580	1			T1	4993		T2	8967		T3	5218
auto[0]	auto[IdleSt]	21460829	1			T1	1656		T2	11908		T3	5507
auto[0]	auto[ClkMuxSt]	33859	1			T1	43		T2	100		T3	56
auto[0]	auto[CntIncrSt]	33580	1			T1	43		T2	100		T3	56
auto[0]	auto[CntProgSt]	1535793	1			T1	69		T2	810		T3	112
auto[0]	auto[TransCheckSt]	25819	1			T1	26		T2	79		T3	56
auto[0]	auto[TokenHashSt]	37621892	1			T1	1477		T2	22426		T3	2877
auto[0]	auto[FlashRmaSt]	33803	1			T1	21		T2	38		T3	105
auto[0]	auto[TokenCheck0St]	12137	1			T1	21		T2	24		T3	25
auto[0]	auto[TokenCheck1St]	9016	1			T1	11		T2	18		T3	9
auto[0]	auto[TransProgSt]	411680	1			T1	22		T2	231		T4	275
auto[0]	auto[PostTransSt]	12247571	1			T1	4934		T2	18297		T3	8789
auto[0]	auto[ScrapSt]	109034	1			T5	833		T18	2		T50	4
auto[0]	auto[EscalateSt]	5106905	1			T1	2121		T2	773		T4	5961
auto[0]	auto[InvalidSt]	10622692	1			T1	728		T4	7156		T15	1588
auto[1]	auto[ResetSt]	169	1			T18	5		T50	1		T64	4
auto[1]	auto[IdleSt]	113	1			T50	1		T64	3		T46	3
auto[1]	auto[ClkMuxSt]	45	1			T18	2		T46	2		T65	2
auto[1]	auto[CntIncrSt]	39	1			T50	1		T65	1		T208	1
auto[1]	auto[CntProgSt]	687	1			T18	6		T50	18		T64	12
auto[1]	auto[TransCheckSt]	63	1			T18	4		T46	2		T69	1
auto[1]	auto[TokenHashSt]	440	1			T18	19		T50	6		T64	3
auto[1]	auto[FlashRmaSt]	61	1			T18	2		T50	2		T46	1
auto[1]	auto[TokenCheck0St]	23	1			T50	1		T46	1		T65	1
auto[1]	auto[TokenCheck1St]	114	1			T18	5		T50	1		T64	2
auto[1]	auto[TransProgSt]	458	1			T18	7		T50	10		T64	8
auto[1]	auto[PostTransSt]	2603	1			T1	9		T2	5		T15	5
auto[1]	auto[ScrapSt]	39	1			T18	1		T50	2		T64	1
auto[1]	auto[EscalateSt]	1359620	1			T1	1274		T2	490		T4	97
auto[1]	auto[InvalidSt]	6956	1			T1	4		T4	1		T15	8