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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.90 97.99 95.68 93.40 97.67 98.55 98.51 96.47


Total test records in report: 1000
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T817 /workspace/coverage/default/44.lc_ctrl_alert_test.2623428994 Jul 18 05:16:15 PM PDT 24 Jul 18 05:16:20 PM PDT 24 90946735 ps
T818 /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3410091031 Jul 18 05:14:33 PM PDT 24 Jul 18 05:15:01 PM PDT 24 2734363664 ps
T819 /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1161837570 Jul 18 05:13:46 PM PDT 24 Jul 18 05:14:07 PM PDT 24 973797624 ps
T820 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.27574785 Jul 18 05:13:50 PM PDT 24 Jul 18 05:14:01 PM PDT 24 1116689446 ps
T821 /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3731761663 Jul 18 05:12:50 PM PDT 24 Jul 18 05:13:01 PM PDT 24 895941225 ps
T822 /workspace/coverage/default/2.lc_ctrl_prog_failure.811261577 Jul 18 05:13:04 PM PDT 24 Jul 18 05:13:09 PM PDT 24 71505681 ps
T823 /workspace/coverage/default/24.lc_ctrl_state_failure.4041848613 Jul 18 05:14:54 PM PDT 24 Jul 18 05:15:18 PM PDT 24 347609089 ps
T824 /workspace/coverage/default/5.lc_ctrl_jtag_priority.1934591121 Jul 18 05:13:06 PM PDT 24 Jul 18 05:13:14 PM PDT 24 279342724 ps
T81 /workspace/coverage/default/24.lc_ctrl_alert_test.586292841 Jul 18 05:14:55 PM PDT 24 Jul 18 05:14:59 PM PDT 24 13390376 ps
T825 /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1229228119 Jul 18 05:14:55 PM PDT 24 Jul 18 05:15:07 PM PDT 24 376636227 ps
T826 /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2421820183 Jul 18 05:16:13 PM PDT 24 Jul 18 05:16:29 PM PDT 24 1876605261 ps
T161 /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.4169094549 Jul 18 05:15:46 PM PDT 24 Jul 18 05:21:31 PM PDT 24 31304359754 ps
T162 /workspace/coverage/default/27.lc_ctrl_stress_all.3477210870 Jul 18 05:15:06 PM PDT 24 Jul 18 05:16:26 PM PDT 24 7189019615 ps
T163 /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3547709014 Jul 18 05:14:39 PM PDT 24 Jul 18 05:14:48 PM PDT 24 213806861 ps
T164 /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2807999825 Jul 18 05:13:03 PM PDT 24 Jul 18 05:13:05 PM PDT 24 19648229 ps
T165 /workspace/coverage/default/47.lc_ctrl_errors.3595661815 Jul 18 05:16:19 PM PDT 24 Jul 18 05:16:37 PM PDT 24 656942774 ps
T166 /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3820610163 Jul 18 05:12:46 PM PDT 24 Jul 18 05:12:53 PM PDT 24 273603133 ps
T167 /workspace/coverage/default/15.lc_ctrl_state_failure.1368102945 Jul 18 05:14:05 PM PDT 24 Jul 18 05:14:37 PM PDT 24 1007598462 ps
T168 /workspace/coverage/default/3.lc_ctrl_sec_mubi.2451710510 Jul 18 05:13:11 PM PDT 24 Jul 18 05:13:32 PM PDT 24 2507777566 ps
T169 /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3928061839 Jul 18 05:14:05 PM PDT 24 Jul 18 05:15:05 PM PDT 24 2158569307 ps
T170 /workspace/coverage/default/14.lc_ctrl_stress_all.3011611363 Jul 18 05:14:01 PM PDT 24 Jul 18 05:15:34 PM PDT 24 2676093364 ps
T827 /workspace/coverage/default/18.lc_ctrl_errors.2201488665 Jul 18 05:14:33 PM PDT 24 Jul 18 05:14:44 PM PDT 24 274300298 ps
T828 /workspace/coverage/default/25.lc_ctrl_sec_token_mux.808261579 Jul 18 05:14:56 PM PDT 24 Jul 18 05:15:13 PM PDT 24 369879009 ps
T829 /workspace/coverage/default/18.lc_ctrl_jtag_errors.262317155 Jul 18 05:14:33 PM PDT 24 Jul 18 05:15:25 PM PDT 24 1564179840 ps
T830 /workspace/coverage/default/35.lc_ctrl_stress_all.3518984270 Jul 18 05:15:27 PM PDT 24 Jul 18 05:19:19 PM PDT 24 28555956355 ps
T831 /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1869791488 Jul 18 05:13:08 PM PDT 24 Jul 18 05:13:21 PM PDT 24 4091132739 ps
T832 /workspace/coverage/default/40.lc_ctrl_sec_token_mux.4250923344 Jul 18 05:15:49 PM PDT 24 Jul 18 05:15:59 PM PDT 24 1000507161 ps
T833 /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3538101674 Jul 18 05:13:12 PM PDT 24 Jul 18 05:13:16 PM PDT 24 146099777 ps
T834 /workspace/coverage/default/13.lc_ctrl_state_failure.323163131 Jul 18 05:13:47 PM PDT 24 Jul 18 05:14:13 PM PDT 24 617367913 ps
T835 /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1473810752 Jul 18 05:16:12 PM PDT 24 Jul 18 05:16:24 PM PDT 24 732889010 ps
T836 /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1559415002 Jul 18 05:14:12 PM PDT 24 Jul 18 05:14:26 PM PDT 24 393437911 ps
T837 /workspace/coverage/default/15.lc_ctrl_smoke.1572662267 Jul 18 05:14:04 PM PDT 24 Jul 18 05:14:10 PM PDT 24 33341787 ps
T838 /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3927107742 Jul 18 05:14:07 PM PDT 24 Jul 18 05:14:19 PM PDT 24 1030678400 ps
T839 /workspace/coverage/default/41.lc_ctrl_state_failure.4236383164 Jul 18 05:16:19 PM PDT 24 Jul 18 05:16:53 PM PDT 24 267886642 ps
T840 /workspace/coverage/default/0.lc_ctrl_sec_token_mux.19519283 Jul 18 05:12:48 PM PDT 24 Jul 18 05:13:04 PM PDT 24 1871101401 ps
T841 /workspace/coverage/default/45.lc_ctrl_state_post_trans.1546947509 Jul 18 05:16:15 PM PDT 24 Jul 18 05:16:24 PM PDT 24 64483432 ps
T171 /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.3537510198 Jul 18 05:14:54 PM PDT 24 Jul 18 05:23:09 PM PDT 24 81217933360 ps
T842 /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.860589571 Jul 18 05:15:43 PM PDT 24 Jul 18 05:15:46 PM PDT 24 41655040 ps
T843 /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3759359506 Jul 18 05:14:04 PM PDT 24 Jul 18 05:15:06 PM PDT 24 5997381954 ps
T844 /workspace/coverage/default/41.lc_ctrl_alert_test.956813846 Jul 18 05:16:09 PM PDT 24 Jul 18 05:16:11 PM PDT 24 13211454 ps
T845 /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1848369718 Jul 18 05:14:02 PM PDT 24 Jul 18 05:14:04 PM PDT 24 49687248 ps
T846 /workspace/coverage/default/27.lc_ctrl_jtag_access.1648312303 Jul 18 05:15:13 PM PDT 24 Jul 18 05:15:19 PM PDT 24 232693294 ps
T847 /workspace/coverage/default/29.lc_ctrl_sec_mubi.943786209 Jul 18 05:15:14 PM PDT 24 Jul 18 05:15:31 PM PDT 24 1353881882 ps
T848 /workspace/coverage/default/0.lc_ctrl_prog_failure.3271990642 Jul 18 05:12:53 PM PDT 24 Jul 18 05:12:59 PM PDT 24 64864848 ps
T849 /workspace/coverage/default/30.lc_ctrl_alert_test.620363593 Jul 18 05:15:15 PM PDT 24 Jul 18 05:15:19 PM PDT 24 62060493 ps
T850 /workspace/coverage/default/47.lc_ctrl_sec_mubi.1916915307 Jul 18 05:16:33 PM PDT 24 Jul 18 05:17:01 PM PDT 24 832382503 ps
T851 /workspace/coverage/default/31.lc_ctrl_smoke.3947692855 Jul 18 05:15:13 PM PDT 24 Jul 18 05:15:19 PM PDT 24 755545369 ps
T852 /workspace/coverage/default/5.lc_ctrl_security_escalation.723930832 Jul 18 05:13:09 PM PDT 24 Jul 18 05:13:26 PM PDT 24 325056288 ps
T853 /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.19625856 Jul 18 05:13:33 PM PDT 24 Jul 18 05:13:39 PM PDT 24 167059732 ps
T854 /workspace/coverage/default/24.lc_ctrl_security_escalation.2642240516 Jul 18 05:14:54 PM PDT 24 Jul 18 05:15:08 PM PDT 24 340018714 ps
T855 /workspace/coverage/default/44.lc_ctrl_sec_mubi.1789340223 Jul 18 05:16:11 PM PDT 24 Jul 18 05:16:25 PM PDT 24 1502338257 ps
T856 /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3077452566 Jul 18 05:15:36 PM PDT 24 Jul 18 05:15:39 PM PDT 24 12862062 ps
T857 /workspace/coverage/default/0.lc_ctrl_jtag_access.2955695397 Jul 18 05:12:47 PM PDT 24 Jul 18 05:13:00 PM PDT 24 4017658678 ps
T858 /workspace/coverage/default/41.lc_ctrl_smoke.2331483639 Jul 18 05:16:13 PM PDT 24 Jul 18 05:16:18 PM PDT 24 69917822 ps
T859 /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2971281799 Jul 18 05:13:50 PM PDT 24 Jul 18 05:14:10 PM PDT 24 418738538 ps
T860 /workspace/coverage/default/24.lc_ctrl_stress_all.3917137306 Jul 18 05:14:54 PM PDT 24 Jul 18 05:16:17 PM PDT 24 8632875371 ps
T861 /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1539824969 Jul 18 05:15:46 PM PDT 24 Jul 18 05:15:58 PM PDT 24 751783486 ps
T862 /workspace/coverage/default/45.lc_ctrl_prog_failure.2548942900 Jul 18 05:16:14 PM PDT 24 Jul 18 05:16:19 PM PDT 24 224761923 ps
T863 /workspace/coverage/default/36.lc_ctrl_state_failure.1668146980 Jul 18 05:15:30 PM PDT 24 Jul 18 05:16:03 PM PDT 24 598439544 ps
T864 /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3498472063 Jul 18 05:12:49 PM PDT 24 Jul 18 05:13:06 PM PDT 24 583535086 ps
T865 /workspace/coverage/default/4.lc_ctrl_jtag_smoke.11528016 Jul 18 05:13:06 PM PDT 24 Jul 18 05:13:12 PM PDT 24 194944534 ps
T866 /workspace/coverage/default/45.lc_ctrl_security_escalation.1890449448 Jul 18 05:16:19 PM PDT 24 Jul 18 05:16:32 PM PDT 24 283175851 ps
T867 /workspace/coverage/default/14.lc_ctrl_jtag_errors.3216458920 Jul 18 05:14:04 PM PDT 24 Jul 18 05:14:32 PM PDT 24 1560916290 ps
T868 /workspace/coverage/default/7.lc_ctrl_security_escalation.3232144454 Jul 18 05:13:21 PM PDT 24 Jul 18 05:13:33 PM PDT 24 273649292 ps
T869 /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1458032991 Jul 18 05:15:54 PM PDT 24 Jul 18 05:15:56 PM PDT 24 55181338 ps
T112 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.926683620 Jul 18 06:11:12 PM PDT 24 Jul 18 06:11:16 PM PDT 24 388726952 ps
T113 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1141705907 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:30 PM PDT 24 46554453 ps
T114 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.279685208 Jul 18 06:00:41 PM PDT 24 Jul 18 06:00:46 PM PDT 24 78484235 ps
T119 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4121207181 Jul 18 06:00:45 PM PDT 24 Jul 18 06:00:51 PM PDT 24 27402520 ps
T117 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3931158974 Jul 18 06:00:16 PM PDT 24 Jul 18 06:00:25 PM PDT 24 33395546 ps
T120 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1521093891 Jul 18 06:00:18 PM PDT 24 Jul 18 06:00:30 PM PDT 24 41777645 ps
T183 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3495675434 Jul 18 06:00:23 PM PDT 24 Jul 18 06:00:34 PM PDT 24 130431444 ps
T118 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.691092565 Jul 18 06:00:21 PM PDT 24 Jul 18 06:00:36 PM PDT 24 84834629 ps
T142 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1563131573 Jul 18 06:00:22 PM PDT 24 Jul 18 06:00:34 PM PDT 24 47411368 ps
T121 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2688970693 Jul 18 06:00:41 PM PDT 24 Jul 18 06:00:46 PM PDT 24 511337418 ps
T184 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3696821619 Jul 18 06:00:23 PM PDT 24 Jul 18 06:00:34 PM PDT 24 15513699 ps
T150 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2265589030 Jul 18 06:00:43 PM PDT 24 Jul 18 06:00:47 PM PDT 24 229980436 ps
T138 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2534272808 Jul 18 06:00:54 PM PDT 24 Jul 18 06:01:01 PM PDT 24 112087905 ps
T870 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3987607338 Jul 18 06:00:13 PM PDT 24 Jul 18 06:00:19 PM PDT 24 15076219 ps
T185 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.336945231 Jul 18 06:01:09 PM PDT 24 Jul 18 06:01:24 PM PDT 24 47203930 ps
T141 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2381964528 Jul 18 06:00:22 PM PDT 24 Jul 18 06:00:35 PM PDT 24 74140805 ps
T151 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2466402978 Jul 18 06:01:01 PM PDT 24 Jul 18 06:01:10 PM PDT 24 37855352 ps
T139 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.847236129 Jul 18 06:00:21 PM PDT 24 Jul 18 06:00:38 PM PDT 24 1273810792 ps
T123 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1941322419 Jul 18 06:00:55 PM PDT 24 Jul 18 06:01:04 PM PDT 24 170069478 ps
T140 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3470822828 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:29 PM PDT 24 463134723 ps
T871 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1406799068 Jul 18 06:00:19 PM PDT 24 Jul 18 06:00:31 PM PDT 24 23747966 ps
T872 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2576764854 Jul 18 06:01:00 PM PDT 24 Jul 18 06:01:10 PM PDT 24 254957010 ps
T115 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2981622877 Jul 18 06:01:19 PM PDT 24 Jul 18 06:01:32 PM PDT 24 721183316 ps
T197 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.435092156 Jul 18 06:00:59 PM PDT 24 Jul 18 06:01:08 PM PDT 24 172398840 ps
T873 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1389225988 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:28 PM PDT 24 69588268 ps
T874 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2589971924 Jul 18 06:00:58 PM PDT 24 Jul 18 06:01:07 PM PDT 24 16894743 ps
T198 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2351934716 Jul 18 06:00:18 PM PDT 24 Jul 18 06:00:29 PM PDT 24 57955509 ps
T875 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2144984327 Jul 18 06:00:41 PM PDT 24 Jul 18 06:00:44 PM PDT 24 97711957 ps
T876 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.4137170932 Jul 18 06:00:55 PM PDT 24 Jul 18 06:01:03 PM PDT 24 45075762 ps
T116 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.847507579 Jul 18 06:00:53 PM PDT 24 Jul 18 06:01:01 PM PDT 24 49025294 ps
T877 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1300306354 Jul 18 06:00:14 PM PDT 24 Jul 18 06:00:40 PM PDT 24 981696464 ps
T878 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1905610162 Jul 18 06:00:22 PM PDT 24 Jul 18 06:00:34 PM PDT 24 20163960 ps
T879 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2070791086 Jul 18 06:00:42 PM PDT 24 Jul 18 06:00:48 PM PDT 24 152946718 ps
T880 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1893771934 Jul 18 06:00:20 PM PDT 24 Jul 18 06:00:32 PM PDT 24 109311192 ps
T881 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4121550056 Jul 18 06:00:22 PM PDT 24 Jul 18 06:00:34 PM PDT 24 352916463 ps
T128 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3303418390 Jul 18 06:00:21 PM PDT 24 Jul 18 06:00:34 PM PDT 24 955632457 ps
T199 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2219369269 Jul 18 06:00:18 PM PDT 24 Jul 18 06:00:30 PM PDT 24 50379278 ps
T124 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3821464801 Jul 18 06:00:16 PM PDT 24 Jul 18 06:00:29 PM PDT 24 123988734 ps
T131 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2403312849 Jul 18 06:00:41 PM PDT 24 Jul 18 06:00:45 PM PDT 24 168452461 ps
T882 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1752230912 Jul 18 06:00:15 PM PDT 24 Jul 18 06:00:24 PM PDT 24 100552530 ps
T883 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.532766279 Jul 18 06:00:43 PM PDT 24 Jul 18 06:00:47 PM PDT 24 16668913 ps
T200 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2878150770 Jul 18 06:00:58 PM PDT 24 Jul 18 06:01:05 PM PDT 24 27825438 ps
T884 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3552699295 Jul 18 06:00:21 PM PDT 24 Jul 18 06:00:53 PM PDT 24 948348677 ps
T885 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2482277600 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:29 PM PDT 24 15891844 ps
T186 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3398030964 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:28 PM PDT 24 92743184 ps
T886 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3382798457 Jul 18 06:00:40 PM PDT 24 Jul 18 06:00:55 PM PDT 24 520412490 ps
T201 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1759326169 Jul 18 06:00:20 PM PDT 24 Jul 18 06:00:32 PM PDT 24 109288523 ps
T202 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3315915707 Jul 18 06:00:36 PM PDT 24 Jul 18 06:00:39 PM PDT 24 24352402 ps
T887 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.4258486406 Jul 18 06:00:21 PM PDT 24 Jul 18 06:00:33 PM PDT 24 17039253 ps
T187 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2788321580 Jul 18 06:00:19 PM PDT 24 Jul 18 06:00:31 PM PDT 24 49801462 ps
T203 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.617570006 Jul 18 06:01:06 PM PDT 24 Jul 18 06:01:19 PM PDT 24 30230031 ps
T130 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3700782972 Jul 18 06:00:19 PM PDT 24 Jul 18 06:00:31 PM PDT 24 329067515 ps
T888 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2328600675 Jul 18 06:00:41 PM PDT 24 Jul 18 06:00:44 PM PDT 24 40687704 ps
T889 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.4235477254 Jul 18 06:00:14 PM PDT 24 Jul 18 06:00:23 PM PDT 24 62568910 ps
T890 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1956510189 Jul 18 06:00:16 PM PDT 24 Jul 18 06:00:28 PM PDT 24 51244849 ps
T188 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2549326853 Jul 18 06:00:14 PM PDT 24 Jul 18 06:00:21 PM PDT 24 24646307 ps
T891 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3475687136 Jul 18 06:00:44 PM PDT 24 Jul 18 06:00:49 PM PDT 24 78207017 ps
T892 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2101592489 Jul 18 06:00:29 PM PDT 24 Jul 18 06:00:37 PM PDT 24 368908064 ps
T893 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.645759434 Jul 18 06:00:21 PM PDT 24 Jul 18 06:00:33 PM PDT 24 50795452 ps
T894 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2422784190 Jul 18 06:00:34 PM PDT 24 Jul 18 06:00:38 PM PDT 24 363154739 ps
T189 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3552296707 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:28 PM PDT 24 23551577 ps
T895 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1300626801 Jul 18 06:00:15 PM PDT 24 Jul 18 06:00:25 PM PDT 24 58117478 ps
T896 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.647131414 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:29 PM PDT 24 75856109 ps
T897 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.531065849 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:31 PM PDT 24 108246853 ps
T898 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4280336013 Jul 18 06:00:18 PM PDT 24 Jul 18 06:00:32 PM PDT 24 106057456 ps
T899 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2070016606 Jul 18 06:00:44 PM PDT 24 Jul 18 06:00:49 PM PDT 24 47560631 ps
T900 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.821129748 Jul 18 06:00:50 PM PDT 24 Jul 18 06:00:55 PM PDT 24 38763676 ps
T901 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3656204801 Jul 18 06:00:16 PM PDT 24 Jul 18 06:00:26 PM PDT 24 18810629 ps
T902 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1121319324 Jul 18 06:00:44 PM PDT 24 Jul 18 06:00:49 PM PDT 24 43698096 ps
T125 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1394508858 Jul 18 06:00:18 PM PDT 24 Jul 18 06:00:30 PM PDT 24 49676742 ps
T903 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2151875193 Jul 18 06:00:20 PM PDT 24 Jul 18 06:00:36 PM PDT 24 351962329 ps
T904 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2802280103 Jul 18 06:01:06 PM PDT 24 Jul 18 06:01:21 PM PDT 24 98289842 ps
T905 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1422514728 Jul 18 06:00:22 PM PDT 24 Jul 18 06:00:34 PM PDT 24 144158402 ps
T906 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.501047008 Jul 18 06:00:16 PM PDT 24 Jul 18 06:00:29 PM PDT 24 5829312406 ps
T907 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1309944905 Jul 18 06:00:22 PM PDT 24 Jul 18 06:00:35 PM PDT 24 177236819 ps
T908 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2960567273 Jul 18 06:00:20 PM PDT 24 Jul 18 06:00:34 PM PDT 24 1240535415 ps
T909 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1038011645 Jul 18 06:00:35 PM PDT 24 Jul 18 06:00:38 PM PDT 24 22196986 ps
T910 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.222764759 Jul 18 06:00:14 PM PDT 24 Jul 18 06:00:23 PM PDT 24 251946577 ps
T911 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1676658918 Jul 18 06:00:53 PM PDT 24 Jul 18 06:01:00 PM PDT 24 31919926 ps
T190 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.298316704 Jul 18 06:01:19 PM PDT 24 Jul 18 06:01:30 PM PDT 24 12714142 ps
T912 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.739669804 Jul 18 06:00:22 PM PDT 24 Jul 18 06:00:47 PM PDT 24 2563890671 ps
T913 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2301759328 Jul 18 06:00:15 PM PDT 24 Jul 18 06:00:25 PM PDT 24 165442828 ps
T914 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3702363344 Jul 18 06:00:19 PM PDT 24 Jul 18 06:00:49 PM PDT 24 5134012054 ps
T915 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4001843014 Jul 18 06:00:41 PM PDT 24 Jul 18 06:00:48 PM PDT 24 181471759 ps
T916 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3443593207 Jul 18 06:00:18 PM PDT 24 Jul 18 06:00:30 PM PDT 24 42974420 ps
T135 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3483411066 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:31 PM PDT 24 221995797 ps
T917 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.818789866 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:29 PM PDT 24 98722532 ps
T918 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1159536136 Jul 18 06:00:14 PM PDT 24 Jul 18 06:00:22 PM PDT 24 72526290 ps
T919 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.713869476 Jul 18 06:00:14 PM PDT 24 Jul 18 06:00:24 PM PDT 24 107334911 ps
T127 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1914919058 Jul 18 06:00:53 PM PDT 24 Jul 18 06:01:02 PM PDT 24 858716123 ps
T920 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2441200627 Jul 18 06:00:15 PM PDT 24 Jul 18 06:00:37 PM PDT 24 6092871191 ps
T921 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4233419763 Jul 18 06:00:33 PM PDT 24 Jul 18 06:00:38 PM PDT 24 116677049 ps
T922 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2618214417 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:30 PM PDT 24 38646225 ps
T923 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2557368746 Jul 18 06:00:19 PM PDT 24 Jul 18 06:00:30 PM PDT 24 20850970 ps
T924 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1030605168 Jul 18 06:00:44 PM PDT 24 Jul 18 06:01:00 PM PDT 24 1249957691 ps
T925 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.899203307 Jul 18 06:00:44 PM PDT 24 Jul 18 06:00:49 PM PDT 24 46330904 ps
T191 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2619983063 Jul 18 06:00:53 PM PDT 24 Jul 18 06:01:00 PM PDT 24 24957910 ps
T926 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2199013178 Jul 18 06:00:11 PM PDT 24 Jul 18 06:00:17 PM PDT 24 47064981 ps
T927 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4020912318 Jul 18 06:00:19 PM PDT 24 Jul 18 06:00:32 PM PDT 24 153801756 ps
T928 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1472519628 Jul 18 06:00:18 PM PDT 24 Jul 18 06:00:29 PM PDT 24 31776249 ps
T929 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3587801542 Jul 18 06:00:20 PM PDT 24 Jul 18 06:00:37 PM PDT 24 161364345 ps
T930 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3473168761 Jul 18 06:00:43 PM PDT 24 Jul 18 06:00:48 PM PDT 24 27209115 ps
T931 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.990091554 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:29 PM PDT 24 169114480 ps
T932 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.998154909 Jul 18 06:00:21 PM PDT 24 Jul 18 06:00:33 PM PDT 24 109327836 ps
T933 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3828808924 Jul 18 06:00:37 PM PDT 24 Jul 18 06:00:48 PM PDT 24 1039096128 ps
T934 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.4073812997 Jul 18 06:00:23 PM PDT 24 Jul 18 06:00:35 PM PDT 24 33369903 ps
T935 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.234519276 Jul 18 06:00:45 PM PDT 24 Jul 18 06:00:55 PM PDT 24 74687947 ps
T936 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.306167520 Jul 18 06:00:57 PM PDT 24 Jul 18 06:01:05 PM PDT 24 14859932 ps
T937 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1090496544 Jul 18 06:01:19 PM PDT 24 Jul 18 06:01:31 PM PDT 24 282573519 ps
T938 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3714237598 Jul 18 06:00:33 PM PDT 24 Jul 18 06:00:38 PM PDT 24 180476181 ps
T939 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.242927745 Jul 18 06:00:54 PM PDT 24 Jul 18 06:01:01 PM PDT 24 41536381 ps
T940 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1644271053 Jul 18 06:00:20 PM PDT 24 Jul 18 06:00:34 PM PDT 24 1099245633 ps
T941 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3240681959 Jul 18 06:00:15 PM PDT 24 Jul 18 06:00:25 PM PDT 24 36128497 ps
T942 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1323307412 Jul 18 06:00:19 PM PDT 24 Jul 18 06:00:31 PM PDT 24 42391092 ps
T943 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3135243484 Jul 18 06:00:43 PM PDT 24 Jul 18 06:00:47 PM PDT 24 53745751 ps
T944 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3826837718 Jul 18 06:00:22 PM PDT 24 Jul 18 06:00:44 PM PDT 24 962372785 ps
T945 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2885961028 Jul 18 06:01:02 PM PDT 24 Jul 18 06:01:13 PM PDT 24 24980180 ps
T946 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.235611623 Jul 18 06:00:41 PM PDT 24 Jul 18 06:00:44 PM PDT 24 67900816 ps
T192 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1990019627 Jul 18 06:00:44 PM PDT 24 Jul 18 06:00:48 PM PDT 24 18162444 ps
T947 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3426372655 Jul 18 06:00:20 PM PDT 24 Jul 18 06:00:42 PM PDT 24 899361943 ps
T948 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1971246140 Jul 18 06:00:15 PM PDT 24 Jul 18 06:00:33 PM PDT 24 830908668 ps
T949 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3858840455 Jul 18 06:01:06 PM PDT 24 Jul 18 06:01:20 PM PDT 24 22872816 ps
T122 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3024344567 Jul 18 06:00:32 PM PDT 24 Jul 18 06:00:39 PM PDT 24 155815070 ps
T950 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.325052490 Jul 18 06:00:14 PM PDT 24 Jul 18 06:00:23 PM PDT 24 391389001 ps
T134 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3857261603 Jul 18 06:00:45 PM PDT 24 Jul 18 06:00:51 PM PDT 24 199003283 ps
T951 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3125431548 Jul 18 06:00:11 PM PDT 24 Jul 18 06:00:18 PM PDT 24 187179364 ps
T194 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3057967797 Jul 18 06:00:16 PM PDT 24 Jul 18 06:00:26 PM PDT 24 27526158 ps
T952 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3922194075 Jul 18 06:00:15 PM PDT 24 Jul 18 06:00:25 PM PDT 24 287811501 ps
T953 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.631833639 Jul 18 06:00:52 PM PDT 24 Jul 18 06:00:58 PM PDT 24 14669600 ps
T954 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1426272623 Jul 18 06:00:14 PM PDT 24 Jul 18 06:00:31 PM PDT 24 417294404 ps
T955 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.979522976 Jul 18 06:00:15 PM PDT 24 Jul 18 06:00:27 PM PDT 24 215268190 ps
T956 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.270062035 Jul 18 06:00:15 PM PDT 24 Jul 18 06:00:25 PM PDT 24 39118330 ps
T957 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.296361089 Jul 18 06:00:55 PM PDT 24 Jul 18 06:01:04 PM PDT 24 58799012 ps
T129 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.853313714 Jul 18 06:00:15 PM PDT 24 Jul 18 06:00:27 PM PDT 24 289428459 ps
T958 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.894036248 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:31 PM PDT 24 76799737 ps
T959 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.622512694 Jul 18 06:00:35 PM PDT 24 Jul 18 06:00:40 PM PDT 24 136192504 ps
T960 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1629985324 Jul 18 06:00:22 PM PDT 24 Jul 18 06:00:35 PM PDT 24 161929670 ps
T961 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3715688862 Jul 18 06:00:43 PM PDT 24 Jul 18 06:00:48 PM PDT 24 62609597 ps
T133 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2061324488 Jul 18 06:00:44 PM PDT 24 Jul 18 06:00:50 PM PDT 24 493148525 ps
T962 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.778959536 Jul 18 06:00:22 PM PDT 24 Jul 18 06:00:34 PM PDT 24 29372720 ps
T963 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.493726922 Jul 18 06:00:21 PM PDT 24 Jul 18 06:00:35 PM PDT 24 463474058 ps
T964 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3474785924 Jul 18 06:00:43 PM PDT 24 Jul 18 06:00:47 PM PDT 24 37955847 ps
T965 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1541208225 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:29 PM PDT 24 41703510 ps
T966 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.326356279 Jul 18 06:00:13 PM PDT 24 Jul 18 06:00:21 PM PDT 24 186057209 ps
T967 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1805064695 Jul 18 06:00:53 PM PDT 24 Jul 18 06:01:00 PM PDT 24 349456983 ps
T968 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4042200591 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:28 PM PDT 24 78276921 ps
T969 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1585702794 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:30 PM PDT 24 123994221 ps
T137 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1392738749 Jul 18 06:01:06 PM PDT 24 Jul 18 06:01:22 PM PDT 24 108817489 ps
T970 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.977819602 Jul 18 06:00:15 PM PDT 24 Jul 18 06:00:24 PM PDT 24 41177794 ps
T136 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2693210180 Jul 18 06:01:06 PM PDT 24 Jul 18 06:01:22 PM PDT 24 662231465 ps
T971 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1379585205 Jul 18 06:00:11 PM PDT 24 Jul 18 06:00:17 PM PDT 24 18834987 ps
T972 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3426079713 Jul 18 06:00:22 PM PDT 24 Jul 18 06:00:45 PM PDT 24 1164566640 ps
T973 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3156000881 Jul 18 06:01:06 PM PDT 24 Jul 18 06:01:20 PM PDT 24 23738024 ps
T974 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4251194475 Jul 18 06:00:16 PM PDT 24 Jul 18 06:00:27 PM PDT 24 145657464 ps
T975 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2061258343 Jul 18 06:00:21 PM PDT 24 Jul 18 06:00:36 PM PDT 24 245972038 ps
T976 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1344768997 Jul 18 06:00:15 PM PDT 24 Jul 18 06:00:27 PM PDT 24 461420901 ps
T977 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1239368513 Jul 18 06:01:06 PM PDT 24 Jul 18 06:01:21 PM PDT 24 125759719 ps
T978 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3797929284 Jul 18 06:00:16 PM PDT 24 Jul 18 06:00:27 PM PDT 24 229147876 ps
T979 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4069509643 Jul 18 06:01:06 PM PDT 24 Jul 18 06:01:20 PM PDT 24 18734611 ps
T980 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3287675065 Jul 18 06:00:16 PM PDT 24 Jul 18 06:00:26 PM PDT 24 39396742 ps
T981 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2303217149 Jul 18 06:00:43 PM PDT 24 Jul 18 06:00:56 PM PDT 24 1089824567 ps
T982 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3068832719 Jul 18 06:00:22 PM PDT 24 Jul 18 06:00:34 PM PDT 24 14456413 ps
T983 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.641926301 Jul 18 06:00:22 PM PDT 24 Jul 18 06:00:34 PM PDT 24 25240723 ps
T984 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1936756150 Jul 18 06:00:15 PM PDT 24 Jul 18 06:00:30 PM PDT 24 485379883 ps
T195 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1190904135 Jul 18 06:00:36 PM PDT 24 Jul 18 06:00:39 PM PDT 24 12981286 ps
T196 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.4157047501 Jul 18 06:00:15 PM PDT 24 Jul 18 06:00:25 PM PDT 24 28113518 ps
T985 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3976750198 Jul 18 06:00:15 PM PDT 24 Jul 18 06:00:24 PM PDT 24 62537631 ps
T986 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3796057987 Jul 18 06:00:36 PM PDT 24 Jul 18 06:00:39 PM PDT 24 516540642 ps
T987 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2399028830 Jul 18 06:00:42 PM PDT 24 Jul 18 06:00:48 PM PDT 24 1499168569 ps
T988 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2720692066 Jul 18 06:01:19 PM PDT 24 Jul 18 06:01:30 PM PDT 24 22020556 ps
T989 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2811771792 Jul 18 06:00:18 PM PDT 24 Jul 18 06:00:35 PM PDT 24 1910075189 ps
T990 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.496544083 Jul 18 06:00:17 PM PDT 24 Jul 18 06:00:29 PM PDT 24 166770947 ps
T991 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1821796991 Jul 18 06:00:18 PM PDT 24 Jul 18 06:00:31 PM PDT 24 116934006 ps
T992 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4080088541 Jul 18 06:00:45 PM PDT 24 Jul 18 06:00:52 PM PDT 24 1327280715 ps
T993 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.263816433 Jul 18 06:00:33 PM PDT 24 Jul 18 06:00:38 PM PDT 24 24231256 ps
T994 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3001772583 Jul 18 06:00:58 PM PDT 24 Jul 18 06:01:05 PM PDT 24 141694228 ps
T132 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3969081280 Jul 18 06:01:06 PM PDT 24 Jul 18 06:01:22 PM PDT 24 202794042 ps
T995 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3310406814 Jul 18 06:00:14 PM PDT 24 Jul 18 06:00:24 PM PDT 24 82353889 ps
T996 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1156812837 Jul 18 06:00:36 PM PDT 24 Jul 18 06:00:39 PM PDT 24 95354430 ps
T997 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2167191947 Jul 18 06:00:44 PM PDT 24 Jul 18 06:00:48 PM PDT 24 24951735 ps
T193 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.747102523 Jul 18 06:00:15 PM PDT 24 Jul 18 06:00:25 PM PDT 24 23766506 ps
T126 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1581444467 Jul 18 06:00:41 PM PDT 24 Jul 18 06:00:46 PM PDT 24 336651492 ps
T998 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.133273311 Jul 18 06:00:45 PM PDT 24 Jul 18 06:00:52 PM PDT 24 207528496 ps
T999 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.206906796 Jul 18 06:00:22 PM PDT 24 Jul 18 06:00:34 PM PDT 24 233629349 ps
T1000 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2137415968 Jul 18 06:00:41 PM PDT 24 Jul 18 06:00:46 PM PDT 24 31961994 ps

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.3414143721
Short name T5
Test name
Test status
Simulation time 17498869063 ps
CPU time 141.5 seconds
Started Jul 18 05:14:54 PM PDT 24
Finished Jul 18 05:17:19 PM PDT 24
Peak memory 240884 kb
Host smart-c1a06be7-7689-48f4-8b1b-a800e20b7392
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3414143721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.3414143721
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3227750913
Short name T46
Test name
Test status
Simulation time 765089013 ps
CPU time 13.84 seconds
Started Jul 18 05:15:32 PM PDT 24
Finished Jul 18 05:15:47 PM PDT 24
Peak memory 217844 kb
Host smart-8f0f7bec-6cd4-404d-9d06-7e12934d809c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227750913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3227750913
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.2249041757
Short name T58
Test name
Test status
Simulation time 61443348314 ps
CPU time 1260.51 seconds
Started Jul 18 05:15:12 PM PDT 24
Finished Jul 18 05:36:15 PM PDT 24
Peak memory 421936 kb
Host smart-546d998a-4f8e-4156-aa2b-108c8411ffd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2249041757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.2249041757
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1883128397
Short name T15
Test name
Test status
Simulation time 723391663 ps
CPU time 9.97 seconds
Started Jul 18 05:15:10 PM PDT 24
Finished Jul 18 05:15:22 PM PDT 24
Peak memory 225576 kb
Host smart-6eeda6d2-0fd9-4a15-aa9f-c9d02e25891c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883128397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1883128397
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.279685208
Short name T114
Test name
Test status
Simulation time 78484235 ps
CPU time 2.99 seconds
Started Jul 18 06:00:41 PM PDT 24
Finished Jul 18 06:00:46 PM PDT 24
Peak memory 222388 kb
Host smart-f104cac7-bf2a-487e-a5ec-08e0969c197f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279685208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.279685208
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1690306964
Short name T51
Test name
Test status
Simulation time 24455072 ps
CPU time 0.99 seconds
Started Jul 18 05:16:15 PM PDT 24
Finished Jul 18 05:16:20 PM PDT 24
Peak memory 208440 kb
Host smart-6f2ceb3d-68af-4132-a18c-df439f1c686c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690306964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1690306964
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3981109989
Short name T67
Test name
Test status
Simulation time 898063013 ps
CPU time 33.42 seconds
Started Jul 18 05:12:48 PM PDT 24
Finished Jul 18 05:13:26 PM PDT 24
Peak memory 269532 kb
Host smart-5c3bb2cc-2fb1-4757-84a6-e114ca4983b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981109989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3981109989
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2428125625
Short name T3
Test name
Test status
Simulation time 228116737 ps
CPU time 6.74 seconds
Started Jul 18 05:15:08 PM PDT 24
Finished Jul 18 05:15:16 PM PDT 24
Peak memory 225484 kb
Host smart-c38915d0-3736-4997-8829-6e3b12b4ef96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428125625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2428125625
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.4060851111
Short name T106
Test name
Test status
Simulation time 15910469822 ps
CPU time 566.54 seconds
Started Jul 18 05:15:09 PM PDT 24
Finished Jul 18 05:24:37 PM PDT 24
Peak memory 345048 kb
Host smart-7df4b9eb-839b-479f-b6af-fe98e624e531
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4060851111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.4060851111
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1883548471
Short name T8
Test name
Test status
Simulation time 1312163406 ps
CPU time 9.79 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:16:25 PM PDT 24
Peak memory 216744 kb
Host smart-21793073-19ec-4812-8cd2-2651c8d69b6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883548471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1883548471
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2688970693
Short name T121
Test name
Test status
Simulation time 511337418 ps
CPU time 3.19 seconds
Started Jul 18 06:00:41 PM PDT 24
Finished Jul 18 06:00:46 PM PDT 24
Peak memory 217980 kb
Host smart-ebb7ef69-7f2e-4f06-974d-d930cc48c658
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688970693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2688970693
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2464347450
Short name T13
Test name
Test status
Simulation time 25331932 ps
CPU time 1 seconds
Started Jul 18 05:13:32 PM PDT 24
Finished Jul 18 05:13:36 PM PDT 24
Peak memory 208488 kb
Host smart-3dae473f-e01b-4b6a-8a16-412030c378e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464347450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2464347450
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.336945231
Short name T185
Test name
Test status
Simulation time 47203930 ps
CPU time 1 seconds
Started Jul 18 06:01:09 PM PDT 24
Finished Jul 18 06:01:24 PM PDT 24
Peak memory 209680 kb
Host smart-58ba5c5b-76ed-4e69-a44b-32c9560cdfca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336945231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.336945231
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3470822828
Short name T140
Test name
Test status
Simulation time 463134723 ps
CPU time 1.95 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:29 PM PDT 24
Peak memory 211228 kb
Host smart-6ac75759-d0ee-4c90-a80c-d4cb8ad64727
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470822828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3470822828
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.3700095140
Short name T109
Test name
Test status
Simulation time 28494493233 ps
CPU time 539.6 seconds
Started Jul 18 05:15:30 PM PDT 24
Finished Jul 18 05:24:31 PM PDT 24
Peak memory 388416 kb
Host smart-08e8837e-4548-40d7-b05a-d97a58ed64be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3700095140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.3700095140
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.4095711085
Short name T1
Test name
Test status
Simulation time 349069625 ps
CPU time 7.78 seconds
Started Jul 18 05:15:13 PM PDT 24
Finished Jul 18 05:15:25 PM PDT 24
Peak memory 218464 kb
Host smart-560d1785-0741-4f6d-8e57-07871be77847
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095711085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.4095711085
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3821464801
Short name T124
Test name
Test status
Simulation time 123988734 ps
CPU time 4.58 seconds
Started Jul 18 06:00:16 PM PDT 24
Finished Jul 18 06:00:29 PM PDT 24
Peak memory 217924 kb
Host smart-fd8dff12-a291-4b1e-a3c0-f6c8112463b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821464801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3821464801
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3294828415
Short name T50
Test name
Test status
Simulation time 308882312 ps
CPU time 7.66 seconds
Started Jul 18 05:12:47 PM PDT 24
Finished Jul 18 05:12:58 PM PDT 24
Peak memory 217848 kb
Host smart-bf318535-d98d-4ee0-99ca-e5e66148ce69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294828415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3294828415
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2981622877
Short name T115
Test name
Test status
Simulation time 721183316 ps
CPU time 3.23 seconds
Started Jul 18 06:01:19 PM PDT 24
Finished Jul 18 06:01:32 PM PDT 24
Peak memory 217860 kb
Host smart-94f74f43-87de-46ec-bb4b-748c41041b81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981622877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2981622877
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.984284209
Short name T14
Test name
Test status
Simulation time 62122233 ps
CPU time 0.79 seconds
Started Jul 18 05:14:18 PM PDT 24
Finished Jul 18 05:14:19 PM PDT 24
Peak memory 208436 kb
Host smart-1909b4ae-6825-472c-b9ca-424ecbf3f1b3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984284209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.984284209
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3969081280
Short name T132
Test name
Test status
Simulation time 202794042 ps
CPU time 3.94 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:01:22 PM PDT 24
Peak memory 217952 kb
Host smart-81c656da-56c2-4978-b89e-c1972dafe981
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969081280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3969081280
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.2495435047
Short name T20
Test name
Test status
Simulation time 6758262636 ps
CPU time 176.97 seconds
Started Jul 18 05:15:10 PM PDT 24
Finished Jul 18 05:18:09 PM PDT 24
Peak memory 308568 kb
Host smart-2c7b79aa-cec0-4e73-bc44-4aaff7b92957
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2495435047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.2495435047
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1914919058
Short name T127
Test name
Test status
Simulation time 858716123 ps
CPU time 4.18 seconds
Started Jul 18 06:00:53 PM PDT 24
Finished Jul 18 06:01:02 PM PDT 24
Peak memory 217860 kb
Host smart-35195e0e-2af7-4197-b2b5-08bd5a6a3ac1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914919058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1914919058
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2802280103
Short name T904
Test name
Test status
Simulation time 98289842 ps
CPU time 2.99 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:01:21 PM PDT 24
Peak memory 218892 kb
Host smart-b07f8371-59e9-4fb1-bf9f-ae7d0ae1d5b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802280103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2802280103
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3700782972
Short name T130
Test name
Test status
Simulation time 329067515 ps
CPU time 1.97 seconds
Started Jul 18 06:00:19 PM PDT 24
Finished Jul 18 06:00:31 PM PDT 24
Peak memory 221196 kb
Host smart-7d985c3c-05ae-4b81-9efd-ca309d16e685
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700782972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3700782972
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3483411066
Short name T135
Test name
Test status
Simulation time 221995797 ps
CPU time 2.95 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:31 PM PDT 24
Peak memory 217972 kb
Host smart-09af079f-d674-45c7-ad79-60b920c27074
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483411066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3483411066
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.774008674
Short name T176
Test name
Test status
Simulation time 15405345 ps
CPU time 0.83 seconds
Started Jul 18 05:12:46 PM PDT 24
Finished Jul 18 05:12:50 PM PDT 24
Peak memory 208492 kb
Host smart-17d33d04-e36a-403c-bc76-f3281c921707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774008674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.774008674
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1822373022
Short name T206
Test name
Test status
Simulation time 26214283 ps
CPU time 0.88 seconds
Started Jul 18 05:13:03 PM PDT 24
Finished Jul 18 05:13:05 PM PDT 24
Peak memory 208164 kb
Host smart-7a83c6ef-b6ab-46dc-8956-0e2b55162059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822373022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1822373022
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3571947361
Short name T27
Test name
Test status
Simulation time 13433008 ps
CPU time 0.99 seconds
Started Jul 18 05:13:10 PM PDT 24
Finished Jul 18 05:13:15 PM PDT 24
Peak memory 208292 kb
Host smart-413e3b71-26d1-4f66-800e-aa1f493110f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571947361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3571947361
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2240722403
Short name T207
Test name
Test status
Simulation time 10662517 ps
CPU time 0.82 seconds
Started Jul 18 05:13:29 PM PDT 24
Finished Jul 18 05:13:34 PM PDT 24
Peak memory 208196 kb
Host smart-50092f47-8df1-4439-acf0-5d9ed7416249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240722403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2240722403
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2654022381
Short name T205
Test name
Test status
Simulation time 22388982 ps
CPU time 0.93 seconds
Started Jul 18 05:13:28 PM PDT 24
Finished Jul 18 05:13:34 PM PDT 24
Peak memory 208320 kb
Host smart-67ba9ff8-3135-498e-ab0e-63d11b01f081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654022381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2654022381
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2693210180
Short name T136
Test name
Test status
Simulation time 662231465 ps
CPU time 4.01 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:01:22 PM PDT 24
Peak memory 217768 kb
Host smart-e9d7a25b-2db3-4084-8780-7349991d92f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693210180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2693210180
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.847507579
Short name T116
Test name
Test status
Simulation time 49025294 ps
CPU time 2.5 seconds
Started Jul 18 06:00:53 PM PDT 24
Finished Jul 18 06:01:01 PM PDT 24
Peak memory 217860 kb
Host smart-d33b0f12-97f4-4443-8701-08a232eb9f94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847507579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.847507579
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2403312849
Short name T131
Test name
Test status
Simulation time 168452461 ps
CPU time 1.84 seconds
Started Jul 18 06:00:41 PM PDT 24
Finished Jul 18 06:00:45 PM PDT 24
Peak memory 222600 kb
Host smart-81ad0194-1ecc-4e03-a43a-1078cf7fe119
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403312849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2403312849
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3857261603
Short name T134
Test name
Test status
Simulation time 199003283 ps
CPU time 2.21 seconds
Started Jul 18 06:00:45 PM PDT 24
Finished Jul 18 06:00:51 PM PDT 24
Peak memory 222452 kb
Host smart-a683744f-7d9d-4318-bee3-76b83c079d60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857261603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3857261603
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2309486283
Short name T59
Test name
Test status
Simulation time 51173827378 ps
CPU time 258.99 seconds
Started Jul 18 05:14:37 PM PDT 24
Finished Jul 18 05:18:58 PM PDT 24
Peak memory 278280 kb
Host smart-4ceb69a6-4b09-46dc-829f-f7696440d9c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2309486283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2309486283
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1382095607
Short name T26
Test name
Test status
Simulation time 116643072 ps
CPU time 3.39 seconds
Started Jul 18 05:16:08 PM PDT 24
Finished Jul 18 05:16:12 PM PDT 24
Peak memory 217796 kb
Host smart-e48ea1eb-223e-441e-b42a-bd483e1684c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382095607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1382095607
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.747102523
Short name T193
Test name
Test status
Simulation time 23766506 ps
CPU time 1.12 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:25 PM PDT 24
Peak memory 209780 kb
Host smart-fdda9ab8-4aaf-430c-b18a-4746f330d7a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747102523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.747102523
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.818789866
Short name T917
Test name
Test status
Simulation time 98722532 ps
CPU time 1.53 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:29 PM PDT 24
Peak memory 209092 kb
Host smart-adf4dd77-4fb7-4164-a2e8-e2c86dd27fe6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818789866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.818789866
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3987607338
Short name T870
Test name
Test status
Simulation time 15076219 ps
CPU time 1.06 seconds
Started Jul 18 06:00:13 PM PDT 24
Finished Jul 18 06:00:19 PM PDT 24
Peak memory 210268 kb
Host smart-2963a9b0-f702-407d-a611-3b66f5c365ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987607338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3987607338
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3931158974
Short name T117
Test name
Test status
Simulation time 33395546 ps
CPU time 1.37 seconds
Started Jul 18 06:00:16 PM PDT 24
Finished Jul 18 06:00:25 PM PDT 24
Peak memory 219588 kb
Host smart-3ddaf693-ee42-4b72-af45-1ff27e25653d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931158974 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3931158974
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2549326853
Short name T188
Test name
Test status
Simulation time 24646307 ps
CPU time 0.94 seconds
Started Jul 18 06:00:14 PM PDT 24
Finished Jul 18 06:00:21 PM PDT 24
Peak memory 209336 kb
Host smart-70cb4a8e-17f2-4d0d-ad99-c12a9d18402d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549326853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2549326853
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2199013178
Short name T926
Test name
Test status
Simulation time 47064981 ps
CPU time 1.12 seconds
Started Jul 18 06:00:11 PM PDT 24
Finished Jul 18 06:00:17 PM PDT 24
Peak memory 209588 kb
Host smart-26be0066-42cc-457e-ad5d-0daf99f95773
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199013178 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2199013178
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1426272623
Short name T954
Test name
Test status
Simulation time 417294404 ps
CPU time 10.3 seconds
Started Jul 18 06:00:14 PM PDT 24
Finished Jul 18 06:00:31 PM PDT 24
Peak memory 208940 kb
Host smart-ceded23a-b4e7-413a-a136-9bef204a37c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426272623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1426272623
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1300306354
Short name T877
Test name
Test status
Simulation time 981696464 ps
CPU time 19.48 seconds
Started Jul 18 06:00:14 PM PDT 24
Finished Jul 18 06:00:40 PM PDT 24
Peak memory 208928 kb
Host smart-4a608727-ce19-4de1-be32-3ced308804b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300306354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1300306354
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.531065849
Short name T897
Test name
Test status
Simulation time 108246853 ps
CPU time 3.27 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:31 PM PDT 24
Peak memory 217928 kb
Host smart-a54739f1-9321-4e0c-9e54-9827c5620464
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531065
849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.531065849
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3125431548
Short name T951
Test name
Test status
Simulation time 187179364 ps
CPU time 1.48 seconds
Started Jul 18 06:00:11 PM PDT 24
Finished Jul 18 06:00:18 PM PDT 24
Peak memory 209624 kb
Host smart-3de6b757-1040-4c31-9363-3be1239e27c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125431548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3125431548
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1379585205
Short name T971
Test name
Test status
Simulation time 18834987 ps
CPU time 1.19 seconds
Started Jul 18 06:00:11 PM PDT 24
Finished Jul 18 06:00:17 PM PDT 24
Peak memory 217728 kb
Host smart-fde37677-7736-4744-8e9b-9e8f2f184bcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379585205 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1379585205
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2618214417
Short name T922
Test name
Test status
Simulation time 38646225 ps
CPU time 1.95 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:30 PM PDT 24
Peak memory 209636 kb
Host smart-f35ab907-b67b-45e4-8601-dc35b52e3bd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618214417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2618214417
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1344768997
Short name T976
Test name
Test status
Simulation time 461420901 ps
CPU time 3.44 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:27 PM PDT 24
Peak memory 217880 kb
Host smart-6c6f4050-17ad-4ba8-82ba-f0b9fbd0db4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344768997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1344768997
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3303418390
Short name T128
Test name
Test status
Simulation time 955632457 ps
CPU time 2.59 seconds
Started Jul 18 06:00:21 PM PDT 24
Finished Jul 18 06:00:34 PM PDT 24
Peak memory 222340 kb
Host smart-1091a99c-122c-4576-81f2-772da05f296f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303418390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3303418390
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3398030964
Short name T186
Test name
Test status
Simulation time 92743184 ps
CPU time 1.14 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:28 PM PDT 24
Peak memory 209728 kb
Host smart-b5f9f7a9-52c4-471c-945c-3953f165c18c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398030964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3398030964
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.4157047501
Short name T196
Test name
Test status
Simulation time 28113518 ps
CPU time 1.63 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:25 PM PDT 24
Peak memory 209608 kb
Host smart-eb09d5a3-c536-4082-98b4-bf6da5d236ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157047501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.4157047501
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1541208225
Short name T965
Test name
Test status
Simulation time 41703510 ps
CPU time 1.06 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:29 PM PDT 24
Peak memory 210304 kb
Host smart-a12d1e09-5659-4806-81e8-44366045bd3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541208225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1541208225
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2301759328
Short name T913
Test name
Test status
Simulation time 165442828 ps
CPU time 1.97 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:25 PM PDT 24
Peak memory 219580 kb
Host smart-8f80842e-3471-4190-8345-c02042a9c833
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301759328 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2301759328
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3656204801
Short name T901
Test name
Test status
Simulation time 18810629 ps
CPU time 0.93 seconds
Started Jul 18 06:00:16 PM PDT 24
Finished Jul 18 06:00:26 PM PDT 24
Peak memory 209448 kb
Host smart-03420df7-012f-46d4-b27d-3aa17f8ff629
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656204801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3656204801
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1585702794
Short name T969
Test name
Test status
Simulation time 123994221 ps
CPU time 1.93 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:30 PM PDT 24
Peak memory 209592 kb
Host smart-854adcfb-8092-41fb-b825-74da95d5f44d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585702794 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1585702794
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1936756150
Short name T984
Test name
Test status
Simulation time 485379883 ps
CPU time 6.88 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:30 PM PDT 24
Peak memory 208912 kb
Host smart-e23003b3-587c-496c-88cd-656441658644
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936756150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1936756150
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2441200627
Short name T920
Test name
Test status
Simulation time 6092871191 ps
CPU time 13.87 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:37 PM PDT 24
Peak memory 209720 kb
Host smart-427778cc-39c1-44bc-beeb-30f95e811eaf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441200627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2441200627
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.713869476
Short name T919
Test name
Test status
Simulation time 107334911 ps
CPU time 2.99 seconds
Started Jul 18 06:00:14 PM PDT 24
Finished Jul 18 06:00:24 PM PDT 24
Peak memory 210920 kb
Host smart-86087747-972b-48b8-b51d-3aa89ef160ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713869476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.713869476
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4042200591
Short name T968
Test name
Test status
Simulation time 78276921 ps
CPU time 1.73 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:28 PM PDT 24
Peak memory 217896 kb
Host smart-de4a5a2f-9837-4570-90eb-f1971fc468cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404220
0591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4042200591
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1389225988
Short name T873
Test name
Test status
Simulation time 69588268 ps
CPU time 1.51 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:28 PM PDT 24
Peak memory 209688 kb
Host smart-37aa0318-ef8c-4f3f-b092-6faddee3f649
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389225988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1389225988
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3240681959
Short name T941
Test name
Test status
Simulation time 36128497 ps
CPU time 1.41 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:25 PM PDT 24
Peak memory 209708 kb
Host smart-c7e3a8ed-f63f-4956-bd1b-ee5d8a2e3f54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240681959 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3240681959
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.977819602
Short name T970
Test name
Test status
Simulation time 41177794 ps
CPU time 1.29 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:24 PM PDT 24
Peak memory 211872 kb
Host smart-b5b7c5d1-37eb-4c58-bc35-28db8ab49626
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977819602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.977819602
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.979522976
Short name T955
Test name
Test status
Simulation time 215268190 ps
CPU time 3.63 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:27 PM PDT 24
Peak memory 217836 kb
Host smart-d7bcc6af-8481-47fb-a921-4f7d7935f10d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979522976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.979522976
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.853313714
Short name T129
Test name
Test status
Simulation time 289428459 ps
CPU time 3.44 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:27 PM PDT 24
Peak memory 213700 kb
Host smart-216326bf-4fd2-40cf-b99a-868c7264a834
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853313714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.853313714
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4233419763
Short name T921
Test name
Test status
Simulation time 116677049 ps
CPU time 1.83 seconds
Started Jul 18 06:00:33 PM PDT 24
Finished Jul 18 06:00:38 PM PDT 24
Peak memory 218048 kb
Host smart-92511a9f-9729-4de7-b7ae-95f7c2d82af6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233419763 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.4233419763
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2328600675
Short name T888
Test name
Test status
Simulation time 40687704 ps
CPU time 1.01 seconds
Started Jul 18 06:00:41 PM PDT 24
Finished Jul 18 06:00:44 PM PDT 24
Peak memory 209676 kb
Host smart-d0b317dc-f191-45fc-bc99-c5b3623a3ccf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328600675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2328600675
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.263816433
Short name T993
Test name
Test status
Simulation time 24231256 ps
CPU time 1.48 seconds
Started Jul 18 06:00:33 PM PDT 24
Finished Jul 18 06:00:38 PM PDT 24
Peak memory 217864 kb
Host smart-7152a43b-0889-4373-9066-fc5af5d34195
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263816433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.263816433
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2101592489
Short name T892
Test name
Test status
Simulation time 368908064 ps
CPU time 1.95 seconds
Started Jul 18 06:00:29 PM PDT 24
Finished Jul 18 06:00:37 PM PDT 24
Peak memory 218000 kb
Host smart-eb9ef673-e770-4f1e-8242-dbc78bf1412c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101592489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2101592489
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3715688862
Short name T961
Test name
Test status
Simulation time 62609597 ps
CPU time 2.01 seconds
Started Jul 18 06:00:43 PM PDT 24
Finished Jul 18 06:00:48 PM PDT 24
Peak memory 221736 kb
Host smart-1647719e-68b6-4baf-b965-7c13d071cdf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715688862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3715688862
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2589971924
Short name T874
Test name
Test status
Simulation time 16894743 ps
CPU time 1.25 seconds
Started Jul 18 06:00:58 PM PDT 24
Finished Jul 18 06:01:07 PM PDT 24
Peak memory 217844 kb
Host smart-ee04e47a-8f18-4a8f-b893-b4adcbc50709
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589971924 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2589971924
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1990019627
Short name T192
Test name
Test status
Simulation time 18162444 ps
CPU time 0.93 seconds
Started Jul 18 06:00:44 PM PDT 24
Finished Jul 18 06:00:48 PM PDT 24
Peak memory 209672 kb
Host smart-806e205e-a9ca-435c-a8b4-167b14e324fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990019627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1990019627
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3858840455
Short name T949
Test name
Test status
Simulation time 22872816 ps
CPU time 1.24 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:01:20 PM PDT 24
Peak memory 211612 kb
Host smart-fca3c397-44ed-46f6-9808-c8e2f0a4f790
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858840455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.3858840455
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2070791086
Short name T879
Test name
Test status
Simulation time 152946718 ps
CPU time 3.28 seconds
Started Jul 18 06:00:42 PM PDT 24
Finished Jul 18 06:00:48 PM PDT 24
Peak memory 218988 kb
Host smart-aff4165d-7ee5-4705-8a46-3f0a09d6fdb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070791086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2070791086
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4069509643
Short name T979
Test name
Test status
Simulation time 18734611 ps
CPU time 1.3 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:01:20 PM PDT 24
Peak memory 218084 kb
Host smart-1d7fdb2f-124d-45da-b3d0-3a3d4704ac1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069509643 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.4069509643
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2619983063
Short name T191
Test name
Test status
Simulation time 24957910 ps
CPU time 0.86 seconds
Started Jul 18 06:00:53 PM PDT 24
Finished Jul 18 06:01:00 PM PDT 24
Peak memory 209608 kb
Host smart-24921c07-a675-4539-9746-0400c054fd4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619983063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2619983063
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.899203307
Short name T925
Test name
Test status
Simulation time 46330904 ps
CPU time 1.39 seconds
Started Jul 18 06:00:44 PM PDT 24
Finished Jul 18 06:00:49 PM PDT 24
Peak memory 209868 kb
Host smart-957b8fa0-b179-4e96-9825-2e6d37f730c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899203307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.899203307
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.622512694
Short name T959
Test name
Test status
Simulation time 136192504 ps
CPU time 2.39 seconds
Started Jul 18 06:00:35 PM PDT 24
Finished Jul 18 06:00:40 PM PDT 24
Peak memory 217952 kb
Host smart-c3011967-37e1-4f5b-8fd9-4f49210bfe9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622512694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.622512694
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3474785924
Short name T964
Test name
Test status
Simulation time 37955847 ps
CPU time 1.63 seconds
Started Jul 18 06:00:43 PM PDT 24
Finished Jul 18 06:00:47 PM PDT 24
Peak memory 217988 kb
Host smart-5c2b700f-079c-499a-9fcf-265f5620eb9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474785924 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3474785924
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.631833639
Short name T953
Test name
Test status
Simulation time 14669600 ps
CPU time 0.83 seconds
Started Jul 18 06:00:52 PM PDT 24
Finished Jul 18 06:00:58 PM PDT 24
Peak memory 209680 kb
Host smart-3394c164-4973-41e0-b2db-7ddea8b60190
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631833639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.631833639
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2878150770
Short name T200
Test name
Test status
Simulation time 27825438 ps
CPU time 1.06 seconds
Started Jul 18 06:00:58 PM PDT 24
Finished Jul 18 06:01:05 PM PDT 24
Peak memory 209608 kb
Host smart-c14ca507-d4da-4a18-8dac-a6bdcd84aa75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878150770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2878150770
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2144984327
Short name T875
Test name
Test status
Simulation time 97711957 ps
CPU time 1.72 seconds
Started Jul 18 06:00:41 PM PDT 24
Finished Jul 18 06:00:44 PM PDT 24
Peak memory 218884 kb
Host smart-656dbacd-0492-459f-b514-24a33b75a3ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144984327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2144984327
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1581444467
Short name T126
Test name
Test status
Simulation time 336651492 ps
CPU time 1.89 seconds
Started Jul 18 06:00:41 PM PDT 24
Finished Jul 18 06:00:46 PM PDT 24
Peak memory 213092 kb
Host smart-8f59255f-e3e4-4dad-9b75-a6430fdce2d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581444467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1581444467
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.235611623
Short name T946
Test name
Test status
Simulation time 67900816 ps
CPU time 1.37 seconds
Started Jul 18 06:00:41 PM PDT 24
Finished Jul 18 06:00:44 PM PDT 24
Peak memory 218064 kb
Host smart-80a194e4-4df0-4c53-9b0c-66489b5dc2de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235611623 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.235611623
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1121319324
Short name T902
Test name
Test status
Simulation time 43698096 ps
CPU time 0.86 seconds
Started Jul 18 06:00:44 PM PDT 24
Finished Jul 18 06:00:49 PM PDT 24
Peak memory 209644 kb
Host smart-122b61f0-a028-46a7-b924-9f7dc73fd730
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121319324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1121319324
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3473168761
Short name T930
Test name
Test status
Simulation time 27209115 ps
CPU time 1.02 seconds
Started Jul 18 06:00:43 PM PDT 24
Finished Jul 18 06:00:48 PM PDT 24
Peak memory 209660 kb
Host smart-af9aa9c6-3523-4841-8c82-04d3999139b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473168761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3473168761
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4080088541
Short name T992
Test name
Test status
Simulation time 1327280715 ps
CPU time 2.23 seconds
Started Jul 18 06:00:45 PM PDT 24
Finished Jul 18 06:00:52 PM PDT 24
Peak memory 217864 kb
Host smart-58968906-7edd-47e2-a5ee-ebec5aeba502
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080088541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.4080088541
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3001772583
Short name T994
Test name
Test status
Simulation time 141694228 ps
CPU time 0.99 seconds
Started Jul 18 06:00:58 PM PDT 24
Finished Jul 18 06:01:05 PM PDT 24
Peak memory 217936 kb
Host smart-7f7b81c7-b3e8-466c-98ab-79692bff4236
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001772583 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3001772583
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3135243484
Short name T943
Test name
Test status
Simulation time 53745751 ps
CPU time 1.04 seconds
Started Jul 18 06:00:43 PM PDT 24
Finished Jul 18 06:00:47 PM PDT 24
Peak memory 209636 kb
Host smart-87fe5ffb-5558-43b1-93d0-53166f9f9487
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135243484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3135243484
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.617570006
Short name T203
Test name
Test status
Simulation time 30230031 ps
CPU time 1.01 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:01:19 PM PDT 24
Peak memory 209696 kb
Host smart-94e9b249-b29c-49a5-995d-cc2a945bb6fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617570006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.617570006
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.234519276
Short name T935
Test name
Test status
Simulation time 74687947 ps
CPU time 1.38 seconds
Started Jul 18 06:00:45 PM PDT 24
Finished Jul 18 06:00:55 PM PDT 24
Peak memory 220028 kb
Host smart-28c504d6-d381-4fef-a514-f7fd59f76acb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234519276 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.234519276
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1090496544
Short name T937
Test name
Test status
Simulation time 282573519 ps
CPU time 1.71 seconds
Started Jul 18 06:01:19 PM PDT 24
Finished Jul 18 06:01:31 PM PDT 24
Peak memory 209624 kb
Host smart-0c7ffce0-b694-474f-95a8-bda32cc1da53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090496544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1090496544
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1239368513
Short name T977
Test name
Test status
Simulation time 125759719 ps
CPU time 2.99 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:01:21 PM PDT 24
Peak memory 217780 kb
Host smart-4c2bae35-a3ee-4325-92b6-29a6158711c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239368513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1239368513
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1676658918
Short name T911
Test name
Test status
Simulation time 31919926 ps
CPU time 1.22 seconds
Started Jul 18 06:00:53 PM PDT 24
Finished Jul 18 06:01:00 PM PDT 24
Peak memory 219068 kb
Host smart-aba9d030-c25a-4153-b950-f46a6753ba89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676658918 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1676658918
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2720692066
Short name T988
Test name
Test status
Simulation time 22020556 ps
CPU time 0.83 seconds
Started Jul 18 06:01:19 PM PDT 24
Finished Jul 18 06:01:30 PM PDT 24
Peak memory 209152 kb
Host smart-c7767a1d-ca46-4b57-aa53-d83774ab5f7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720692066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2720692066
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.242927745
Short name T939
Test name
Test status
Simulation time 41536381 ps
CPU time 1.52 seconds
Started Jul 18 06:00:54 PM PDT 24
Finished Jul 18 06:01:01 PM PDT 24
Peak memory 217976 kb
Host smart-8950c585-0bd9-425b-a9bc-b75c3ebec94e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242927745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.242927745
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1805064695
Short name T967
Test name
Test status
Simulation time 349456983 ps
CPU time 2.05 seconds
Started Jul 18 06:00:53 PM PDT 24
Finished Jul 18 06:01:00 PM PDT 24
Peak memory 218416 kb
Host smart-281f0a6c-4d58-4d89-8f95-6e2a05b73790
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805064695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1805064695
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2466402978
Short name T151
Test name
Test status
Simulation time 37855352 ps
CPU time 1.02 seconds
Started Jul 18 06:01:01 PM PDT 24
Finished Jul 18 06:01:10 PM PDT 24
Peak memory 218036 kb
Host smart-87b530c2-d7d6-48c4-bf6d-cc03b6799516
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466402978 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2466402978
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.298316704
Short name T190
Test name
Test status
Simulation time 12714142 ps
CPU time 0.86 seconds
Started Jul 18 06:01:19 PM PDT 24
Finished Jul 18 06:01:30 PM PDT 24
Peak memory 209640 kb
Host smart-9ab7c4a0-564f-417a-ab8f-d0fe9fa33f07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298316704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.298316704
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.435092156
Short name T197
Test name
Test status
Simulation time 172398840 ps
CPU time 1.48 seconds
Started Jul 18 06:00:59 PM PDT 24
Finished Jul 18 06:01:08 PM PDT 24
Peak memory 211772 kb
Host smart-ded0a4f6-f1d1-451a-973c-153253812a39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435092156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.435092156
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.926683620
Short name T112
Test name
Test status
Simulation time 388726952 ps
CPU time 2.31 seconds
Started Jul 18 06:11:12 PM PDT 24
Finished Jul 18 06:11:16 PM PDT 24
Peak memory 218156 kb
Host smart-1934bd9b-8663-4c03-abe6-50939c2ea6ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926683620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.926683620
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2061324488
Short name T133
Test name
Test status
Simulation time 493148525 ps
CPU time 3.2 seconds
Started Jul 18 06:00:44 PM PDT 24
Finished Jul 18 06:00:50 PM PDT 24
Peak memory 222820 kb
Host smart-29d6d350-7a20-43bd-ae89-f3fa801e5b86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061324488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2061324488
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3156000881
Short name T973
Test name
Test status
Simulation time 23738024 ps
CPU time 1.48 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:01:20 PM PDT 24
Peak memory 219868 kb
Host smart-3eb69b20-fef1-4b39-9cab-79710181952e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156000881 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3156000881
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2070016606
Short name T899
Test name
Test status
Simulation time 47560631 ps
CPU time 1.01 seconds
Started Jul 18 06:00:44 PM PDT 24
Finished Jul 18 06:00:49 PM PDT 24
Peak memory 209680 kb
Host smart-d0f210a5-6c1d-4e5b-a8dc-b23277893c7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070016606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2070016606
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.821129748
Short name T900
Test name
Test status
Simulation time 38763676 ps
CPU time 1.44 seconds
Started Jul 18 06:00:50 PM PDT 24
Finished Jul 18 06:00:55 PM PDT 24
Peak memory 211752 kb
Host smart-85de1a53-0f6b-48f5-87c4-85bba1c563ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821129748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.821129748
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2576764854
Short name T872
Test name
Test status
Simulation time 254957010 ps
CPU time 2.18 seconds
Started Jul 18 06:01:00 PM PDT 24
Finished Jul 18 06:01:10 PM PDT 24
Peak memory 218220 kb
Host smart-646f89f5-295e-4bf0-b07a-b6037d28a74a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576764854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2576764854
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1392738749
Short name T137
Test name
Test status
Simulation time 108817489 ps
CPU time 3.95 seconds
Started Jul 18 06:01:06 PM PDT 24
Finished Jul 18 06:01:22 PM PDT 24
Peak memory 217860 kb
Host smart-19e50a3c-cdb8-461a-af2d-e62cc67ea913
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392738749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1392738749
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3068832719
Short name T982
Test name
Test status
Simulation time 14456413 ps
CPU time 1.16 seconds
Started Jul 18 06:00:22 PM PDT 24
Finished Jul 18 06:00:34 PM PDT 24
Peak memory 209608 kb
Host smart-2be33e22-ab45-4eea-9658-b83d7a421778
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068832719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3068832719
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.325052490
Short name T950
Test name
Test status
Simulation time 391389001 ps
CPU time 1.96 seconds
Started Jul 18 06:00:14 PM PDT 24
Finished Jul 18 06:00:23 PM PDT 24
Peak memory 209396 kb
Host smart-f194e683-ebe7-4b5d-a4a4-f862eb4952d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325052490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.325052490
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3057967797
Short name T194
Test name
Test status
Simulation time 27526158 ps
CPU time 1.2 seconds
Started Jul 18 06:00:16 PM PDT 24
Finished Jul 18 06:00:26 PM PDT 24
Peak memory 218476 kb
Host smart-f7a8195a-cf2d-4e52-b784-777155ccaccd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057967797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3057967797
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.998154909
Short name T932
Test name
Test status
Simulation time 109327836 ps
CPU time 1.71 seconds
Started Jul 18 06:00:21 PM PDT 24
Finished Jul 18 06:00:33 PM PDT 24
Peak memory 218092 kb
Host smart-0d23fed6-3686-41d0-9b5a-4dc6b6192ef5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998154909 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.998154909
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2482277600
Short name T885
Test name
Test status
Simulation time 15891844 ps
CPU time 1.05 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:29 PM PDT 24
Peak memory 209072 kb
Host smart-b01044cf-adf3-4379-aa57-82c68b98b240
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482277600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2482277600
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.222764759
Short name T910
Test name
Test status
Simulation time 251946577 ps
CPU time 2.22 seconds
Started Jul 18 06:00:14 PM PDT 24
Finished Jul 18 06:00:23 PM PDT 24
Peak memory 209596 kb
Host smart-5402a767-f03f-4ff8-86df-caf638913cc4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222764759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.222764759
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.847236129
Short name T139
Test name
Test status
Simulation time 1273810792 ps
CPU time 5.82 seconds
Started Jul 18 06:00:21 PM PDT 24
Finished Jul 18 06:00:38 PM PDT 24
Peak memory 208016 kb
Host smart-7a46c80b-ccb6-4014-9ac6-5471b0e357ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847236129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.847236129
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1971246140
Short name T948
Test name
Test status
Simulation time 830908668 ps
CPU time 9.59 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:33 PM PDT 24
Peak memory 209440 kb
Host smart-b740c4f5-f68b-4035-a0ce-f4bb852dbfe5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971246140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1971246140
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.326356279
Short name T966
Test name
Test status
Simulation time 186057209 ps
CPU time 2.17 seconds
Started Jul 18 06:00:13 PM PDT 24
Finished Jul 18 06:00:21 PM PDT 24
Peak memory 211384 kb
Host smart-8b49fd95-4bb6-45c7-9ace-3199e8d1ce7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326356279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.326356279
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1644271053
Short name T940
Test name
Test status
Simulation time 1099245633 ps
CPU time 3.57 seconds
Started Jul 18 06:00:20 PM PDT 24
Finished Jul 18 06:00:34 PM PDT 24
Peak memory 218076 kb
Host smart-12da3224-2a4c-4852-ab45-98dd4f556c0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164427
1053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1644271053
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.270062035
Short name T956
Test name
Test status
Simulation time 39118330 ps
CPU time 1.59 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:25 PM PDT 24
Peak memory 209676 kb
Host smart-f561bcba-4c6c-4299-8f57-69ad65fe7143
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270062035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.270062035
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3287675065
Short name T980
Test name
Test status
Simulation time 39396742 ps
CPU time 1.83 seconds
Started Jul 18 06:00:16 PM PDT 24
Finished Jul 18 06:00:26 PM PDT 24
Peak memory 209664 kb
Host smart-84a1ee08-884e-484e-8115-4a8e3f229980
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287675065 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3287675065
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3976750198
Short name T985
Test name
Test status
Simulation time 62537631 ps
CPU time 1.28 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:24 PM PDT 24
Peak memory 209776 kb
Host smart-ddebc526-b3c4-48d7-8539-5e6e939fbc92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976750198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3976750198
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.4235477254
Short name T889
Test name
Test status
Simulation time 62568910 ps
CPU time 2.13 seconds
Started Jul 18 06:00:14 PM PDT 24
Finished Jul 18 06:00:23 PM PDT 24
Peak memory 218900 kb
Host smart-aaa5eb4a-4707-4d42-a6fe-94f2029025be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235477254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.4235477254
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1323307412
Short name T942
Test name
Test status
Simulation time 42391092 ps
CPU time 1.34 seconds
Started Jul 18 06:00:19 PM PDT 24
Finished Jul 18 06:00:31 PM PDT 24
Peak memory 208280 kb
Host smart-bccf797c-d0b2-4a69-9a7f-8de2d1f700a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323307412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1323307412
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.206906796
Short name T999
Test name
Test status
Simulation time 233629349 ps
CPU time 1.64 seconds
Started Jul 18 06:00:22 PM PDT 24
Finished Jul 18 06:00:34 PM PDT 24
Peak memory 209600 kb
Host smart-0a2e2c67-5ee8-4e20-9363-62a171341ed7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206906796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.206906796
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1406799068
Short name T871
Test name
Test status
Simulation time 23747966 ps
CPU time 0.92 seconds
Started Jul 18 06:00:19 PM PDT 24
Finished Jul 18 06:00:31 PM PDT 24
Peak memory 210260 kb
Host smart-f69aaa0c-a3fc-47a5-8229-bfa6c82e5f20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406799068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1406799068
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.4258486406
Short name T887
Test name
Test status
Simulation time 17039253 ps
CPU time 1.23 seconds
Started Jul 18 06:00:21 PM PDT 24
Finished Jul 18 06:00:33 PM PDT 24
Peak memory 219656 kb
Host smart-f8a64e18-98a1-43c3-be7b-8d1644bf8a2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258486406 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.4258486406
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.641926301
Short name T983
Test name
Test status
Simulation time 25240723 ps
CPU time 0.9 seconds
Started Jul 18 06:00:22 PM PDT 24
Finished Jul 18 06:00:34 PM PDT 24
Peak memory 209648 kb
Host smart-111ef09b-d41f-446c-a109-049aca782edd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641926301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.641926301
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1563131573
Short name T142
Test name
Test status
Simulation time 47411368 ps
CPU time 1.16 seconds
Started Jul 18 06:00:22 PM PDT 24
Finished Jul 18 06:00:34 PM PDT 24
Peak memory 209596 kb
Host smart-cad0d81b-28d7-4a2a-a08b-e82f1097392b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563131573 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1563131573
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3426079713
Short name T972
Test name
Test status
Simulation time 1164566640 ps
CPU time 12.02 seconds
Started Jul 18 06:00:22 PM PDT 24
Finished Jul 18 06:00:45 PM PDT 24
Peak memory 209120 kb
Host smart-b34d9df0-3286-4eaa-ac8d-e7c1c1fde932
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426079713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3426079713
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.501047008
Short name T906
Test name
Test status
Simulation time 5829312406 ps
CPU time 4.71 seconds
Started Jul 18 06:00:16 PM PDT 24
Finished Jul 18 06:00:29 PM PDT 24
Peak memory 209700 kb
Host smart-d44dcaf2-91a6-4617-8b1e-2d020aaebd05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501047008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.501047008
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2381964528
Short name T141
Test name
Test status
Simulation time 74140805 ps
CPU time 2.51 seconds
Started Jul 18 06:00:22 PM PDT 24
Finished Jul 18 06:00:35 PM PDT 24
Peak memory 210788 kb
Host smart-902f2b02-ff95-43a1-8df8-326e84e10e88
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381964528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2381964528
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2061258343
Short name T975
Test name
Test status
Simulation time 245972038 ps
CPU time 4.73 seconds
Started Jul 18 06:00:21 PM PDT 24
Finished Jul 18 06:00:36 PM PDT 24
Peak memory 223388 kb
Host smart-31ccf3c5-fe22-4e63-9ec9-bd656840fee5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206125
8343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2061258343
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1159536136
Short name T918
Test name
Test status
Simulation time 72526290 ps
CPU time 1.42 seconds
Started Jul 18 06:00:14 PM PDT 24
Finished Jul 18 06:00:22 PM PDT 24
Peak memory 209588 kb
Host smart-21438c8a-e698-4722-a5e3-8af2a7e255a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159536136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1159536136
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1759326169
Short name T201
Test name
Test status
Simulation time 109288523 ps
CPU time 1.41 seconds
Started Jul 18 06:00:20 PM PDT 24
Finished Jul 18 06:00:32 PM PDT 24
Peak memory 211684 kb
Host smart-b8ae2c5a-7604-405a-822d-8f111bb90efa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759326169 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1759326169
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.645759434
Short name T893
Test name
Test status
Simulation time 50795452 ps
CPU time 1.15 seconds
Started Jul 18 06:00:21 PM PDT 24
Finished Jul 18 06:00:33 PM PDT 24
Peak memory 209648 kb
Host smart-428e5d18-c0a9-4c42-9026-4f0d87a48fa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645759434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.645759434
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4280336013
Short name T898
Test name
Test status
Simulation time 106057456 ps
CPU time 4.27 seconds
Started Jul 18 06:00:18 PM PDT 24
Finished Jul 18 06:00:32 PM PDT 24
Peak memory 217872 kb
Host smart-aebc3708-22d0-4827-b5b9-9de6ba93cf71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280336013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.4280336013
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2788321580
Short name T187
Test name
Test status
Simulation time 49801462 ps
CPU time 1.1 seconds
Started Jul 18 06:00:19 PM PDT 24
Finished Jul 18 06:00:31 PM PDT 24
Peak memory 209600 kb
Host smart-61a18f40-fe94-4d28-ba57-4b69756c95c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788321580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2788321580
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4020912318
Short name T927
Test name
Test status
Simulation time 153801756 ps
CPU time 1.53 seconds
Started Jul 18 06:00:19 PM PDT 24
Finished Jul 18 06:00:32 PM PDT 24
Peak memory 209592 kb
Host smart-552d223b-1bfe-4817-b824-b5cfdb1a6601
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020912318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.4020912318
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3696821619
Short name T184
Test name
Test status
Simulation time 15513699 ps
CPU time 0.99 seconds
Started Jul 18 06:00:23 PM PDT 24
Finished Jul 18 06:00:34 PM PDT 24
Peak memory 210756 kb
Host smart-8477ef9b-a280-4835-9f35-e7261dea9479
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696821619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3696821619
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.778959536
Short name T962
Test name
Test status
Simulation time 29372720 ps
CPU time 1.65 seconds
Started Jul 18 06:00:22 PM PDT 24
Finished Jul 18 06:00:34 PM PDT 24
Peak memory 217968 kb
Host smart-3904b7d6-2dfb-4d18-b70e-7258904a07ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778959536 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.778959536
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2557368746
Short name T923
Test name
Test status
Simulation time 20850970 ps
CPU time 1.14 seconds
Started Jul 18 06:00:19 PM PDT 24
Finished Jul 18 06:00:30 PM PDT 24
Peak memory 209748 kb
Host smart-5b9c53e2-c845-495f-a8d2-11f377dbcb76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557368746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2557368746
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.496544083
Short name T990
Test name
Test status
Simulation time 166770947 ps
CPU time 1.2 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:29 PM PDT 24
Peak memory 209568 kb
Host smart-1591a8f0-eed7-4646-a943-4b81b1717328
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496544083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.496544083
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.739669804
Short name T912
Test name
Test status
Simulation time 2563890671 ps
CPU time 14.26 seconds
Started Jul 18 06:00:22 PM PDT 24
Finished Jul 18 06:00:47 PM PDT 24
Peak memory 209032 kb
Host smart-f1450efb-8564-4569-901e-a750b21ffda6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739669804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.739669804
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3702363344
Short name T914
Test name
Test status
Simulation time 5134012054 ps
CPU time 18.29 seconds
Started Jul 18 06:00:19 PM PDT 24
Finished Jul 18 06:00:49 PM PDT 24
Peak memory 209720 kb
Host smart-2450e78e-e752-4a96-bae5-667514c9b112
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702363344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3702363344
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4121550056
Short name T881
Test name
Test status
Simulation time 352916463 ps
CPU time 1.34 seconds
Started Jul 18 06:00:22 PM PDT 24
Finished Jul 18 06:00:34 PM PDT 24
Peak memory 211088 kb
Host smart-dff6a76f-0b1c-4839-a1c4-c60bc9a72c99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121550056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.4121550056
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3797929284
Short name T978
Test name
Test status
Simulation time 229147876 ps
CPU time 2.24 seconds
Started Jul 18 06:00:16 PM PDT 24
Finished Jul 18 06:00:27 PM PDT 24
Peak memory 217920 kb
Host smart-3c23c237-6cbf-4dcb-9458-17e43836da22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379792
9284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3797929284
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.647131414
Short name T896
Test name
Test status
Simulation time 75856109 ps
CPU time 1.52 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:29 PM PDT 24
Peak memory 209608 kb
Host smart-dc65c932-d688-49ca-b4d1-7aae9907e6c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647131414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.647131414
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4251194475
Short name T974
Test name
Test status
Simulation time 145657464 ps
CPU time 1.26 seconds
Started Jul 18 06:00:16 PM PDT 24
Finished Jul 18 06:00:27 PM PDT 24
Peak memory 211728 kb
Host smart-d9e17b0b-93ce-4fe2-9069-cf6415f79861
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251194475 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.4251194475
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2219369269
Short name T199
Test name
Test status
Simulation time 50379278 ps
CPU time 1.29 seconds
Started Jul 18 06:00:18 PM PDT 24
Finished Jul 18 06:00:30 PM PDT 24
Peak memory 209684 kb
Host smart-66fa001a-94ab-4202-b61d-c3f291dc3de8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219369269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2219369269
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3587801542
Short name T929
Test name
Test status
Simulation time 161364345 ps
CPU time 6.05 seconds
Started Jul 18 06:00:20 PM PDT 24
Finished Jul 18 06:00:37 PM PDT 24
Peak memory 217868 kb
Host smart-001780b3-cd27-486b-8b60-93236d66de77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587801542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3587801542
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1905610162
Short name T878
Test name
Test status
Simulation time 20163960 ps
CPU time 1.44 seconds
Started Jul 18 06:00:22 PM PDT 24
Finished Jul 18 06:00:34 PM PDT 24
Peak memory 219232 kb
Host smart-18637e09-df38-4aeb-b539-131bcdf3ebdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905610162 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1905610162
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3552296707
Short name T189
Test name
Test status
Simulation time 23551577 ps
CPU time 0.86 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:28 PM PDT 24
Peak memory 209588 kb
Host smart-20007bbd-1bd6-4749-aef8-fc55a3412772
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552296707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3552296707
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1472519628
Short name T928
Test name
Test status
Simulation time 31776249 ps
CPU time 1.03 seconds
Started Jul 18 06:00:18 PM PDT 24
Finished Jul 18 06:00:29 PM PDT 24
Peak memory 208148 kb
Host smart-21117c67-b088-4fe3-93e7-60bde326bcac
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472519628 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1472519628
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2960567273
Short name T908
Test name
Test status
Simulation time 1240535415 ps
CPU time 3.45 seconds
Started Jul 18 06:00:20 PM PDT 24
Finished Jul 18 06:00:34 PM PDT 24
Peak memory 209472 kb
Host smart-35797235-71bb-42e3-9acc-dbc899ff5723
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960567273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2960567273
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3826837718
Short name T944
Test name
Test status
Simulation time 962372785 ps
CPU time 11.04 seconds
Started Jul 18 06:00:22 PM PDT 24
Finished Jul 18 06:00:44 PM PDT 24
Peak memory 209468 kb
Host smart-2605923b-9bd8-46d4-b102-7fb756d043c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826837718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3826837718
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.493726922
Short name T963
Test name
Test status
Simulation time 463474058 ps
CPU time 3.53 seconds
Started Jul 18 06:00:21 PM PDT 24
Finished Jul 18 06:00:35 PM PDT 24
Peak memory 211444 kb
Host smart-e328fc89-fa71-481b-8508-70371c171d25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493726922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.493726922
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3922194075
Short name T952
Test name
Test status
Simulation time 287811501 ps
CPU time 2.29 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:25 PM PDT 24
Peak memory 217912 kb
Host smart-aed26a43-c856-4fa5-97d4-3e8909c7b39a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392219
4075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3922194075
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1893771934
Short name T880
Test name
Test status
Simulation time 109311192 ps
CPU time 1.15 seconds
Started Jul 18 06:00:20 PM PDT 24
Finished Jul 18 06:00:32 PM PDT 24
Peak memory 209636 kb
Host smart-b44d6958-0571-44de-bb42-b91904a1e135
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893771934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1893771934
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3443593207
Short name T916
Test name
Test status
Simulation time 42974420 ps
CPU time 1.99 seconds
Started Jul 18 06:00:18 PM PDT 24
Finished Jul 18 06:00:30 PM PDT 24
Peak memory 211772 kb
Host smart-ffd6dd59-0640-498e-9220-329bc1d42aa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443593207 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3443593207
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2351934716
Short name T198
Test name
Test status
Simulation time 57955509 ps
CPU time 1 seconds
Started Jul 18 06:00:18 PM PDT 24
Finished Jul 18 06:00:29 PM PDT 24
Peak memory 209652 kb
Host smart-f4e0c157-ab92-4b5b-a213-4b404d74c147
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351934716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2351934716
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.691092565
Short name T118
Test name
Test status
Simulation time 84834629 ps
CPU time 3.77 seconds
Started Jul 18 06:00:21 PM PDT 24
Finished Jul 18 06:00:36 PM PDT 24
Peak memory 217888 kb
Host smart-42f9f61b-929c-43f0-8320-e6f64aae7ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691092565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.691092565
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1394508858
Short name T125
Test name
Test status
Simulation time 49676742 ps
CPU time 2.19 seconds
Started Jul 18 06:00:18 PM PDT 24
Finished Jul 18 06:00:30 PM PDT 24
Peak memory 217852 kb
Host smart-4c946f2c-0565-462b-99f8-eb87c4fe65d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394508858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1394508858
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.4073812997
Short name T934
Test name
Test status
Simulation time 33369903 ps
CPU time 2.3 seconds
Started Jul 18 06:00:23 PM PDT 24
Finished Jul 18 06:00:35 PM PDT 24
Peak memory 219788 kb
Host smart-9136b2b0-1d48-4578-82d5-92d34f01ebe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073812997 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.4073812997
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3495675434
Short name T183
Test name
Test status
Simulation time 130431444 ps
CPU time 1.09 seconds
Started Jul 18 06:00:23 PM PDT 24
Finished Jul 18 06:00:34 PM PDT 24
Peak memory 209732 kb
Host smart-ae91f3eb-bc8b-4a7e-98b7-c42cbe08fcb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495675434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3495675434
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1422514728
Short name T905
Test name
Test status
Simulation time 144158402 ps
CPU time 1.68 seconds
Started Jul 18 06:00:22 PM PDT 24
Finished Jul 18 06:00:34 PM PDT 24
Peak memory 209596 kb
Host smart-f098c051-386e-4b2f-a4ce-1977bae1a8e6
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422514728 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1422514728
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3552699295
Short name T884
Test name
Test status
Simulation time 948348677 ps
CPU time 20.95 seconds
Started Jul 18 06:00:21 PM PDT 24
Finished Jul 18 06:00:53 PM PDT 24
Peak memory 209548 kb
Host smart-81c7732d-9ad6-4873-b921-0078ab0ace1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552699295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3552699295
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2811771792
Short name T989
Test name
Test status
Simulation time 1910075189 ps
CPU time 5.96 seconds
Started Jul 18 06:00:18 PM PDT 24
Finished Jul 18 06:00:35 PM PDT 24
Peak memory 208944 kb
Host smart-d0015751-a2fc-46fc-9c61-45e530c8156e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811771792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2811771792
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1821796991
Short name T991
Test name
Test status
Simulation time 116934006 ps
CPU time 3.35 seconds
Started Jul 18 06:00:18 PM PDT 24
Finished Jul 18 06:00:31 PM PDT 24
Peak memory 211132 kb
Host smart-4de3a384-898a-4c55-9b9d-eb8cd8136ab6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821796991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1821796991
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3310406814
Short name T995
Test name
Test status
Simulation time 82353889 ps
CPU time 2.93 seconds
Started Jul 18 06:00:14 PM PDT 24
Finished Jul 18 06:00:24 PM PDT 24
Peak memory 218124 kb
Host smart-f950591b-ec99-4152-b477-622a018e032c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331040
6814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3310406814
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1300626801
Short name T895
Test name
Test status
Simulation time 58117478 ps
CPU time 2.11 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:25 PM PDT 24
Peak memory 209640 kb
Host smart-d37ac5f5-c860-4eab-b417-78e4f1591d38
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300626801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1300626801
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1521093891
Short name T120
Test name
Test status
Simulation time 41777645 ps
CPU time 1.42 seconds
Started Jul 18 06:00:18 PM PDT 24
Finished Jul 18 06:00:30 PM PDT 24
Peak memory 211700 kb
Host smart-22b20d90-7078-43a4-a4e2-dcd82aa68c40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521093891 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1521093891
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1629985324
Short name T960
Test name
Test status
Simulation time 161929670 ps
CPU time 2.01 seconds
Started Jul 18 06:00:22 PM PDT 24
Finished Jul 18 06:00:35 PM PDT 24
Peak memory 209700 kb
Host smart-b6a3bbb7-1730-491d-a2da-35c4e60f8acf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629985324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1629985324
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1141705907
Short name T113
Test name
Test status
Simulation time 46554453 ps
CPU time 2.56 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:30 PM PDT 24
Peak memory 217948 kb
Host smart-7ce9fec7-db0d-4f52-b95f-8ad4f5f34181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141705907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1141705907
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.894036248
Short name T958
Test name
Test status
Simulation time 76799737 ps
CPU time 3.41 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:31 PM PDT 24
Peak memory 217940 kb
Host smart-327f061b-d76b-4fca-9453-a22dd7933247
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894036248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.894036248
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2265589030
Short name T150
Test name
Test status
Simulation time 229980436 ps
CPU time 1.11 seconds
Started Jul 18 06:00:43 PM PDT 24
Finished Jul 18 06:00:47 PM PDT 24
Peak memory 218044 kb
Host smart-4c2a2a06-c9cc-4233-ac2e-8f518244ce52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265589030 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2265589030
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1190904135
Short name T195
Test name
Test status
Simulation time 12981286 ps
CPU time 0.9 seconds
Started Jul 18 06:00:36 PM PDT 24
Finished Jul 18 06:00:39 PM PDT 24
Peak memory 209664 kb
Host smart-00aab815-8bf9-4205-953b-31e067d74ab3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190904135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1190904135
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2422784190
Short name T894
Test name
Test status
Simulation time 363154739 ps
CPU time 1.42 seconds
Started Jul 18 06:00:34 PM PDT 24
Finished Jul 18 06:00:38 PM PDT 24
Peak memory 209652 kb
Host smart-3f3c839c-6619-4b29-b307-7b6e7c0273ff
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422784190 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2422784190
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3426372655
Short name T947
Test name
Test status
Simulation time 899361943 ps
CPU time 11.17 seconds
Started Jul 18 06:00:20 PM PDT 24
Finished Jul 18 06:00:42 PM PDT 24
Peak memory 209468 kb
Host smart-be075cc3-9fd6-40fa-90c3-3a4e50321da7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426372655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3426372655
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2151875193
Short name T903
Test name
Test status
Simulation time 351962329 ps
CPU time 5.23 seconds
Started Jul 18 06:00:20 PM PDT 24
Finished Jul 18 06:00:36 PM PDT 24
Peak memory 209656 kb
Host smart-0c05b3f7-d599-46fe-bdb0-ed76d87a1c12
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151875193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2151875193
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1752230912
Short name T882
Test name
Test status
Simulation time 100552530 ps
CPU time 1.63 seconds
Started Jul 18 06:00:15 PM PDT 24
Finished Jul 18 06:00:24 PM PDT 24
Peak memory 211064 kb
Host smart-ce6a0c39-a99b-4c1e-906d-f171e3323721
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752230912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1752230912
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1956510189
Short name T890
Test name
Test status
Simulation time 51244849 ps
CPU time 2.19 seconds
Started Jul 18 06:00:16 PM PDT 24
Finished Jul 18 06:00:28 PM PDT 24
Peak memory 221816 kb
Host smart-68ba5cdd-12f3-42c4-95fb-1b39bee2fe8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195651
0189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1956510189
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1309944905
Short name T907
Test name
Test status
Simulation time 177236819 ps
CPU time 2.23 seconds
Started Jul 18 06:00:22 PM PDT 24
Finished Jul 18 06:00:35 PM PDT 24
Peak memory 209608 kb
Host smart-eb6c4ddb-1fed-4986-a1dd-7766841effc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309944905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1309944905
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.990091554
Short name T931
Test name
Test status
Simulation time 169114480 ps
CPU time 0.99 seconds
Started Jul 18 06:00:17 PM PDT 24
Finished Jul 18 06:00:29 PM PDT 24
Peak memory 209648 kb
Host smart-3327ae9f-e3f4-4ba3-b483-70006aad12d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990091554 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.990091554
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3475687136
Short name T891
Test name
Test status
Simulation time 78207017 ps
CPU time 1.85 seconds
Started Jul 18 06:00:44 PM PDT 24
Finished Jul 18 06:00:49 PM PDT 24
Peak memory 209716 kb
Host smart-5381b9f8-9dc0-4d84-8350-fb0543a9f034
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475687136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3475687136
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1941322419
Short name T123
Test name
Test status
Simulation time 170069478 ps
CPU time 2.79 seconds
Started Jul 18 06:00:55 PM PDT 24
Finished Jul 18 06:01:04 PM PDT 24
Peak memory 217920 kb
Host smart-36dad67a-079e-44e2-ae47-ed52e90ba0a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941322419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1941322419
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3024344567
Short name T122
Test name
Test status
Simulation time 155815070 ps
CPU time 3.18 seconds
Started Jul 18 06:00:32 PM PDT 24
Finished Jul 18 06:00:39 PM PDT 24
Peak memory 213736 kb
Host smart-b218809d-0ac5-4616-862b-c4d3aeed4d5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024344567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.3024344567
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.306167520
Short name T936
Test name
Test status
Simulation time 14859932 ps
CPU time 1.16 seconds
Started Jul 18 06:00:57 PM PDT 24
Finished Jul 18 06:01:05 PM PDT 24
Peak memory 217920 kb
Host smart-c1d775ec-b973-4549-8244-02bef3b1334d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306167520 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.306167520
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.532766279
Short name T883
Test name
Test status
Simulation time 16668913 ps
CPU time 0.88 seconds
Started Jul 18 06:00:43 PM PDT 24
Finished Jul 18 06:00:47 PM PDT 24
Peak memory 209292 kb
Host smart-ee5b9c58-5581-410f-bc81-551bef1087a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532766279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.532766279
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1038011645
Short name T909
Test name
Test status
Simulation time 22196986 ps
CPU time 0.93 seconds
Started Jul 18 06:00:35 PM PDT 24
Finished Jul 18 06:00:38 PM PDT 24
Peak memory 209572 kb
Host smart-ed91a769-16d9-4c6a-9092-c7752df1df76
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038011645 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1038011645
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2303217149
Short name T981
Test name
Test status
Simulation time 1089824567 ps
CPU time 8.86 seconds
Started Jul 18 06:00:43 PM PDT 24
Finished Jul 18 06:00:56 PM PDT 24
Peak memory 209440 kb
Host smart-5bace5da-74f0-41ec-8662-6325ee109ba4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303217149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2303217149
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1030605168
Short name T924
Test name
Test status
Simulation time 1249957691 ps
CPU time 12.53 seconds
Started Jul 18 06:00:44 PM PDT 24
Finished Jul 18 06:01:00 PM PDT 24
Peak memory 209644 kb
Host smart-e3d6bb50-7276-4fbf-98f0-1f4aaa35eecf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030605168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1030605168
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1156812837
Short name T996
Test name
Test status
Simulation time 95354430 ps
CPU time 1.23 seconds
Started Jul 18 06:00:36 PM PDT 24
Finished Jul 18 06:00:39 PM PDT 24
Peak memory 211148 kb
Host smart-227cf649-e597-49b0-b05b-72e655cb5773
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156812837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1156812837
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2399028830
Short name T987
Test name
Test status
Simulation time 1499168569 ps
CPU time 3.59 seconds
Started Jul 18 06:00:42 PM PDT 24
Finished Jul 18 06:00:48 PM PDT 24
Peak memory 218620 kb
Host smart-7c817383-91d9-48fa-ab9f-2fedab4a4237
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239902
8830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2399028830
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3796057987
Short name T986
Test name
Test status
Simulation time 516540642 ps
CPU time 1.47 seconds
Started Jul 18 06:00:36 PM PDT 24
Finished Jul 18 06:00:39 PM PDT 24
Peak memory 209620 kb
Host smart-8088ba40-1aeb-4138-b6c3-43d4493a31b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796057987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3796057987
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4121207181
Short name T119
Test name
Test status
Simulation time 27402520 ps
CPU time 1.43 seconds
Started Jul 18 06:00:45 PM PDT 24
Finished Jul 18 06:00:51 PM PDT 24
Peak memory 209208 kb
Host smart-3bfdee52-cf2d-4082-aed4-b083da1e6652
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121207181 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.4121207181
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3315915707
Short name T202
Test name
Test status
Simulation time 24352402 ps
CPU time 1.37 seconds
Started Jul 18 06:00:36 PM PDT 24
Finished Jul 18 06:00:39 PM PDT 24
Peak memory 209688 kb
Host smart-e1dd2f89-4e00-4195-bfa2-8eea98ddf9c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315915707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3315915707
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.296361089
Short name T957
Test name
Test status
Simulation time 58799012 ps
CPU time 2.01 seconds
Started Jul 18 06:00:55 PM PDT 24
Finished Jul 18 06:01:04 PM PDT 24
Peak memory 217172 kb
Host smart-a3f2bfb7-aafb-4f4a-8a68-536c17845591
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296361089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.296361089
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3714237598
Short name T938
Test name
Test status
Simulation time 180476181 ps
CPU time 1.49 seconds
Started Jul 18 06:00:33 PM PDT 24
Finished Jul 18 06:00:38 PM PDT 24
Peak memory 218448 kb
Host smart-6eb63913-cf7e-438b-a3f4-5d8da5f292d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714237598 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3714237598
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.4137170932
Short name T876
Test name
Test status
Simulation time 45075762 ps
CPU time 1.01 seconds
Started Jul 18 06:00:55 PM PDT 24
Finished Jul 18 06:01:03 PM PDT 24
Peak memory 209504 kb
Host smart-40651ef2-bc3a-4240-a822-9ba9633b8fbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137170932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.4137170932
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2137415968
Short name T1000
Test name
Test status
Simulation time 31961994 ps
CPU time 1.55 seconds
Started Jul 18 06:00:41 PM PDT 24
Finished Jul 18 06:00:46 PM PDT 24
Peak memory 208348 kb
Host smart-5c6d04f9-9563-45f4-aa87-6b90262a8bd7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137415968 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2137415968
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3382798457
Short name T886
Test name
Test status
Simulation time 520412490 ps
CPU time 12.83 seconds
Started Jul 18 06:00:40 PM PDT 24
Finished Jul 18 06:00:55 PM PDT 24
Peak memory 209524 kb
Host smart-20935ce6-edb2-456f-a9c8-9b2baa05abf6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382798457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3382798457
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3828808924
Short name T933
Test name
Test status
Simulation time 1039096128 ps
CPU time 8.8 seconds
Started Jul 18 06:00:37 PM PDT 24
Finished Jul 18 06:00:48 PM PDT 24
Peak memory 208912 kb
Host smart-25dd65cb-5e28-4dc8-9aaa-4accd6331787
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828808924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3828808924
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2534272808
Short name T138
Test name
Test status
Simulation time 112087905 ps
CPU time 1.27 seconds
Started Jul 18 06:00:54 PM PDT 24
Finished Jul 18 06:01:01 PM PDT 24
Peak memory 210744 kb
Host smart-b46bb126-9d17-4d59-bf88-c88e757dd40c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534272808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2534272808
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4001843014
Short name T915
Test name
Test status
Simulation time 181471759 ps
CPU time 4.44 seconds
Started Jul 18 06:00:41 PM PDT 24
Finished Jul 18 06:00:48 PM PDT 24
Peak memory 222952 kb
Host smart-52b32dc7-5f59-401a-8d30-780e9f2ff0ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400184
3014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4001843014
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.133273311
Short name T998
Test name
Test status
Simulation time 207528496 ps
CPU time 1.2 seconds
Started Jul 18 06:00:45 PM PDT 24
Finished Jul 18 06:00:52 PM PDT 24
Peak memory 209636 kb
Host smart-503371ba-f622-4ddc-b057-900edbdb27ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133273311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.133273311
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2167191947
Short name T997
Test name
Test status
Simulation time 24951735 ps
CPU time 1.02 seconds
Started Jul 18 06:00:44 PM PDT 24
Finished Jul 18 06:00:48 PM PDT 24
Peak memory 209688 kb
Host smart-5034a992-8f26-408d-b3ca-a803667635a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167191947 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2167191947
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2885961028
Short name T945
Test name
Test status
Simulation time 24980180 ps
CPU time 1.34 seconds
Started Jul 18 06:01:02 PM PDT 24
Finished Jul 18 06:01:13 PM PDT 24
Peak memory 209648 kb
Host smart-6b508994-3793-43d3-8c1f-f82811f7d068
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885961028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2885961028
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3247763956
Short name T96
Test name
Test status
Simulation time 22089670 ps
CPU time 0.8 seconds
Started Jul 18 05:12:50 PM PDT 24
Finished Jul 18 05:12:55 PM PDT 24
Peak memory 208208 kb
Host smart-94c9a23e-eb18-4625-a74e-616589303c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247763956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3247763956
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1495346468
Short name T298
Test name
Test status
Simulation time 3142100541 ps
CPU time 15.24 seconds
Started Jul 18 05:12:53 PM PDT 24
Finished Jul 18 05:13:12 PM PDT 24
Peak memory 218484 kb
Host smart-30ea77c7-f733-4c6a-8311-85c593223e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495346468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1495346468
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2955695397
Short name T857
Test name
Test status
Simulation time 4017658678 ps
CPU time 9.18 seconds
Started Jul 18 05:12:47 PM PDT 24
Finished Jul 18 05:13:00 PM PDT 24
Peak memory 217232 kb
Host smart-c5ebedd0-9bca-4fd4-844c-9ede0c937437
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955695397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2955695397
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3909669453
Short name T367
Test name
Test status
Simulation time 1103564513 ps
CPU time 34.24 seconds
Started Jul 18 05:12:49 PM PDT 24
Finished Jul 18 05:13:27 PM PDT 24
Peak memory 217720 kb
Host smart-47643f5e-4c7f-4fd1-ba20-32dfbec155bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909669453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3909669453
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1681248213
Short name T541
Test name
Test status
Simulation time 3395927542 ps
CPU time 39.95 seconds
Started Jul 18 05:12:48 PM PDT 24
Finished Jul 18 05:13:32 PM PDT 24
Peak memory 217284 kb
Host smart-5f0ff836-782e-4726-ba44-aed746bd3c62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681248213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
681248213
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3764794531
Short name T789
Test name
Test status
Simulation time 339870829 ps
CPU time 7.14 seconds
Started Jul 18 05:12:48 PM PDT 24
Finished Jul 18 05:12:59 PM PDT 24
Peak memory 222904 kb
Host smart-42d7576f-bac7-4fb1-81ac-72aa06529ac5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764794531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3764794531
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.4111487380
Short name T561
Test name
Test status
Simulation time 4798889534 ps
CPU time 33.1 seconds
Started Jul 18 05:12:48 PM PDT 24
Finished Jul 18 05:13:25 PM PDT 24
Peak memory 217172 kb
Host smart-0889fc6a-7068-4d0a-90ce-00758c0fc5eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111487380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.4111487380
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3820610163
Short name T166
Test name
Test status
Simulation time 273603133 ps
CPU time 5.05 seconds
Started Jul 18 05:12:46 PM PDT 24
Finished Jul 18 05:12:53 PM PDT 24
Peak memory 217076 kb
Host smart-db89291d-a01a-4963-ab63-24acc7641adf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820610163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3820610163
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1814769501
Short name T464
Test name
Test status
Simulation time 6478019765 ps
CPU time 42.22 seconds
Started Jul 18 05:12:47 PM PDT 24
Finished Jul 18 05:13:33 PM PDT 24
Peak memory 250508 kb
Host smart-865d75d2-5195-4eb0-b739-63615846b134
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814769501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1814769501
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2666984449
Short name T305
Test name
Test status
Simulation time 1178327588 ps
CPU time 6.6 seconds
Started Jul 18 05:12:47 PM PDT 24
Finished Jul 18 05:12:58 PM PDT 24
Peak memory 222400 kb
Host smart-e00aaba0-dba7-4eb4-9342-2d100161767e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666984449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2666984449
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3271990642
Short name T848
Test name
Test status
Simulation time 64864848 ps
CPU time 2.48 seconds
Started Jul 18 05:12:53 PM PDT 24
Finished Jul 18 05:12:59 PM PDT 24
Peak memory 217772 kb
Host smart-36fe2621-bd2d-4e19-9825-688217ba3266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271990642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3271990642
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3635471975
Short name T518
Test name
Test status
Simulation time 1102795517 ps
CPU time 16.37 seconds
Started Jul 18 05:12:48 PM PDT 24
Finished Jul 18 05:13:08 PM PDT 24
Peak memory 217176 kb
Host smart-3270002d-6330-4505-84d6-65d2ff6bd5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635471975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3635471975
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.4205252375
Short name T36
Test name
Test status
Simulation time 647899946 ps
CPU time 9.17 seconds
Started Jul 18 05:12:48 PM PDT 24
Finished Jul 18 05:13:01 PM PDT 24
Peak memory 217964 kb
Host smart-95af12a5-df4a-474d-8d96-811be4a21c85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205252375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.4205252375
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3498472063
Short name T864
Test name
Test status
Simulation time 583535086 ps
CPU time 12.76 seconds
Started Jul 18 05:12:49 PM PDT 24
Finished Jul 18 05:13:06 PM PDT 24
Peak memory 217756 kb
Host smart-f75f7db8-61bb-4cd5-aa17-5834af994ac7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498472063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3498472063
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.19519283
Short name T840
Test name
Test status
Simulation time 1871101401 ps
CPU time 12.59 seconds
Started Jul 18 05:12:48 PM PDT 24
Finished Jul 18 05:13:04 PM PDT 24
Peak memory 225492 kb
Host smart-7a8dfadd-0dc1-4193-9f07-a39d08de8a8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19519283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.19519283
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2259972023
Short name T715
Test name
Test status
Simulation time 70378342 ps
CPU time 5.16 seconds
Started Jul 18 05:12:48 PM PDT 24
Finished Jul 18 05:12:57 PM PDT 24
Peak memory 217216 kb
Host smart-b55a1804-fa35-47c8-ae51-553bf1f8e013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259972023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2259972023
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3167595824
Short name T295
Test name
Test status
Simulation time 1005429533 ps
CPU time 25.96 seconds
Started Jul 18 05:14:10 PM PDT 24
Finished Jul 18 05:14:38 PM PDT 24
Peak memory 250508 kb
Host smart-c88e370c-853c-4c39-8b58-1150625ec07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167595824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3167595824
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1276533564
Short name T279
Test name
Test status
Simulation time 94509635 ps
CPU time 7.99 seconds
Started Jul 18 05:12:47 PM PDT 24
Finished Jul 18 05:12:59 PM PDT 24
Peak memory 250520 kb
Host smart-ae03a04f-7811-4bc1-8a23-c234d34110ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276533564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1276533564
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.4159039680
Short name T794
Test name
Test status
Simulation time 26489574910 ps
CPU time 102.6 seconds
Started Jul 18 05:12:50 PM PDT 24
Finished Jul 18 05:14:37 PM PDT 24
Peak memory 267656 kb
Host smart-1feb0f00-cf9f-4cb4-acb0-266e8e23a6dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159039680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.4159039680
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.888192785
Short name T346
Test name
Test status
Simulation time 13222884 ps
CPU time 0.97 seconds
Started Jul 18 05:12:45 PM PDT 24
Finished Jul 18 05:12:48 PM PDT 24
Peak memory 208476 kb
Host smart-66966902-60ee-4347-90bb-fd90d2acfa7e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888192785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.888192785
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1099864677
Short name T219
Test name
Test status
Simulation time 46431783 ps
CPU time 1.05 seconds
Started Jul 18 05:12:44 PM PDT 24
Finished Jul 18 05:12:46 PM PDT 24
Peak memory 208544 kb
Host smart-ab372d5b-113b-44c3-ba31-07f75ca6602c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099864677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1099864677
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.4219003951
Short name T728
Test name
Test status
Simulation time 13425880 ps
CPU time 1.01 seconds
Started Jul 18 05:12:51 PM PDT 24
Finished Jul 18 05:12:57 PM PDT 24
Peak memory 208308 kb
Host smart-065c5ec7-a825-4d8e-bce1-20b4f5182824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219003951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.4219003951
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1999498678
Short name T637
Test name
Test status
Simulation time 850153062 ps
CPU time 12.9 seconds
Started Jul 18 05:12:46 PM PDT 24
Finished Jul 18 05:13:02 PM PDT 24
Peak memory 217776 kb
Host smart-1b7b1fa6-619f-4730-9dd3-3a66a2118d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999498678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1999498678
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.567251144
Short name T766
Test name
Test status
Simulation time 1430689673 ps
CPU time 7.93 seconds
Started Jul 18 05:12:49 PM PDT 24
Finished Jul 18 05:13:01 PM PDT 24
Peak memory 216556 kb
Host smart-9f8c6d49-1f27-4dd1-a370-40c83be1b584
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567251144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.567251144
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3749352592
Short name T672
Test name
Test status
Simulation time 3724107539 ps
CPU time 30.64 seconds
Started Jul 18 05:12:49 PM PDT 24
Finished Jul 18 05:13:23 PM PDT 24
Peak memory 217780 kb
Host smart-0c8df673-8c93-4aa3-bf13-20cd8ba2b06c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749352592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3749352592
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1680240778
Short name T531
Test name
Test status
Simulation time 1491042631 ps
CPU time 19.11 seconds
Started Jul 18 05:12:50 PM PDT 24
Finished Jul 18 05:13:14 PM PDT 24
Peak memory 217248 kb
Host smart-d2e1f8fc-a27e-488e-abdc-2914fa495a15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680240778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
680240778
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2221791291
Short name T355
Test name
Test status
Simulation time 267244965 ps
CPU time 4.77 seconds
Started Jul 18 05:12:58 PM PDT 24
Finished Jul 18 05:13:04 PM PDT 24
Peak memory 222460 kb
Host smart-12ee2339-a3fa-4aed-b02f-80826b6d89d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221791291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2221791291
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.179034254
Short name T364
Test name
Test status
Simulation time 1031615651 ps
CPU time 13.22 seconds
Started Jul 18 05:12:48 PM PDT 24
Finished Jul 18 05:13:05 PM PDT 24
Peak memory 217240 kb
Host smart-32e71aae-1601-4d2b-b4c7-fdf5e0855efb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179034254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.179034254
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3731761663
Short name T821
Test name
Test status
Simulation time 895941225 ps
CPU time 6.93 seconds
Started Jul 18 05:12:50 PM PDT 24
Finished Jul 18 05:13:01 PM PDT 24
Peak memory 217128 kb
Host smart-7567020f-2866-46d3-9c0a-b5545c7f2ffa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731761663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3731761663
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1490019033
Short name T669
Test name
Test status
Simulation time 2832731606 ps
CPU time 58 seconds
Started Jul 18 05:12:52 PM PDT 24
Finished Jul 18 05:13:54 PM PDT 24
Peak memory 267940 kb
Host smart-07a7515c-ef38-4e8f-a7dd-828ce5f8ac7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490019033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.1490019033
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1524315348
Short name T647
Test name
Test status
Simulation time 1101280137 ps
CPU time 21.43 seconds
Started Jul 18 05:12:48 PM PDT 24
Finished Jul 18 05:13:13 PM PDT 24
Peak memory 250412 kb
Host smart-61afea61-e60d-409d-9cbd-59e6319e52cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524315348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1524315348
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1460387729
Short name T274
Test name
Test status
Simulation time 60638067 ps
CPU time 2.17 seconds
Started Jul 18 05:12:48 PM PDT 24
Finished Jul 18 05:12:54 PM PDT 24
Peak memory 217760 kb
Host smart-99fca6b2-a449-44a8-930f-d15799447b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460387729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1460387729
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.4097010904
Short name T668
Test name
Test status
Simulation time 730733085 ps
CPU time 5.02 seconds
Started Jul 18 05:12:51 PM PDT 24
Finished Jul 18 05:13:01 PM PDT 24
Peak memory 213876 kb
Host smart-424b5cc1-6477-43b1-b0fc-e50e5d26df55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097010904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.4097010904
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.4199612147
Short name T94
Test name
Test status
Simulation time 108786565 ps
CPU time 23.9 seconds
Started Jul 18 05:12:48 PM PDT 24
Finished Jul 18 05:13:16 PM PDT 24
Peak memory 284056 kb
Host smart-10d31187-7114-4ccb-9d50-8ad53da161de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199612147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.4199612147
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.846212575
Short name T235
Test name
Test status
Simulation time 238969403 ps
CPU time 11.64 seconds
Started Jul 18 05:12:47 PM PDT 24
Finished Jul 18 05:13:02 PM PDT 24
Peak memory 218504 kb
Host smart-44e5daaa-7cef-417f-a088-36fb7e8ddd1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846212575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.846212575
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2097537756
Short name T757
Test name
Test status
Simulation time 463132777 ps
CPU time 12.17 seconds
Started Jul 18 05:12:48 PM PDT 24
Finished Jul 18 05:13:05 PM PDT 24
Peak memory 225472 kb
Host smart-0261a3ba-1c13-46a7-8096-95e89cc01ed6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097537756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2097537756
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2949827704
Short name T807
Test name
Test status
Simulation time 1075268325 ps
CPU time 8.18 seconds
Started Jul 18 05:12:47 PM PDT 24
Finished Jul 18 05:12:59 PM PDT 24
Peak memory 225500 kb
Host smart-0f2cc188-bcaf-4d5c-a040-9daa93b8e298
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949827704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
949827704
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3372601939
Short name T698
Test name
Test status
Simulation time 490502956 ps
CPU time 13.49 seconds
Started Jul 18 05:12:49 PM PDT 24
Finished Jul 18 05:13:07 PM PDT 24
Peak memory 217808 kb
Host smart-b561e082-af83-4154-a96b-cfa300adf23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372601939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3372601939
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3394206852
Short name T640
Test name
Test status
Simulation time 832378089 ps
CPU time 3.12 seconds
Started Jul 18 05:12:59 PM PDT 24
Finished Jul 18 05:13:03 PM PDT 24
Peak memory 217208 kb
Host smart-6f678753-d71d-41b7-aa55-1ea23059edff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394206852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3394206852
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3446226335
Short name T288
Test name
Test status
Simulation time 556286140 ps
CPU time 33.08 seconds
Started Jul 18 05:12:49 PM PDT 24
Finished Jul 18 05:13:26 PM PDT 24
Peak memory 250508 kb
Host smart-5d640c8d-8a1f-4e5f-9f57-5e1d05c7c899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446226335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3446226335
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3581460301
Short name T673
Test name
Test status
Simulation time 263068917 ps
CPU time 7.71 seconds
Started Jul 18 05:12:48 PM PDT 24
Finished Jul 18 05:13:00 PM PDT 24
Peak memory 248168 kb
Host smart-83f849be-3f02-427e-b3ae-7567d1daf551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581460301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3581460301
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1159934465
Short name T70
Test name
Test status
Simulation time 9026365599 ps
CPU time 95.11 seconds
Started Jul 18 05:12:46 PM PDT 24
Finished Jul 18 05:14:23 PM PDT 24
Peak memory 251124 kb
Host smart-fa270d08-bb16-4f75-9f67-83166a3222f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159934465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1159934465
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2496731513
Short name T84
Test name
Test status
Simulation time 21912951 ps
CPU time 1.07 seconds
Started Jul 18 05:12:49 PM PDT 24
Finished Jul 18 05:12:55 PM PDT 24
Peak memory 211460 kb
Host smart-3769acb3-f24d-432d-8e33-f00fcdeeb6f0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496731513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2496731513
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1279403018
Short name T390
Test name
Test status
Simulation time 67977042 ps
CPU time 0.98 seconds
Started Jul 18 05:13:46 PM PDT 24
Finished Jul 18 05:13:49 PM PDT 24
Peak memory 208452 kb
Host smart-c52b7e0c-8daa-4928-84f3-40ec4a78a9ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279403018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1279403018
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3401663559
Short name T683
Test name
Test status
Simulation time 1102988282 ps
CPU time 15.13 seconds
Started Jul 18 05:13:46 PM PDT 24
Finished Jul 18 05:14:03 PM PDT 24
Peak memory 217780 kb
Host smart-a242ef45-ad0b-4bb5-ad67-1bf4c3a97448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401663559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3401663559
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1895854438
Short name T363
Test name
Test status
Simulation time 540124163 ps
CPU time 5.98 seconds
Started Jul 18 05:13:46 PM PDT 24
Finished Jul 18 05:13:55 PM PDT 24
Peak memory 216552 kb
Host smart-5ed793fd-03e3-4a1d-b49d-62594a9a7fd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895854438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1895854438
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2748773864
Short name T538
Test name
Test status
Simulation time 2626847700 ps
CPU time 24.46 seconds
Started Jul 18 05:13:49 PM PDT 24
Finished Jul 18 05:14:16 PM PDT 24
Peak memory 225580 kb
Host smart-28d4ee3f-cf54-4063-89d2-cf983e3e4690
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748773864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2748773864
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3425624379
Short name T462
Test name
Test status
Simulation time 302689128 ps
CPU time 10.3 seconds
Started Jul 18 05:13:45 PM PDT 24
Finished Jul 18 05:13:58 PM PDT 24
Peak memory 222800 kb
Host smart-685988c0-cf29-4d61-8ed2-54589062c9f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425624379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3425624379
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3908303732
Short name T426
Test name
Test status
Simulation time 124179143 ps
CPU time 3.91 seconds
Started Jul 18 05:13:44 PM PDT 24
Finished Jul 18 05:13:49 PM PDT 24
Peak memory 217084 kb
Host smart-d2af7b6f-a0b0-43cd-a80a-2a8086d29096
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908303732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3908303732
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1123961019
Short name T788
Test name
Test status
Simulation time 13507252440 ps
CPU time 72.04 seconds
Started Jul 18 05:13:45 PM PDT 24
Finished Jul 18 05:14:58 PM PDT 24
Peak memory 283272 kb
Host smart-186b8637-b804-4658-9b22-7f7a03412b0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123961019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1123961019
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1161837570
Short name T819
Test name
Test status
Simulation time 973797624 ps
CPU time 19.35 seconds
Started Jul 18 05:13:46 PM PDT 24
Finished Jul 18 05:14:07 PM PDT 24
Peak memory 250412 kb
Host smart-b24bf940-5670-40cf-af7b-1b80001f0742
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161837570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1161837570
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3396419665
Short name T718
Test name
Test status
Simulation time 557581438 ps
CPU time 2.83 seconds
Started Jul 18 05:13:45 PM PDT 24
Finished Jul 18 05:13:50 PM PDT 24
Peak memory 217812 kb
Host smart-ef466274-94e6-45b7-921d-535b278e9171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396419665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3396419665
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1644448600
Short name T47
Test name
Test status
Simulation time 1025071853 ps
CPU time 9.34 seconds
Started Jul 18 05:13:44 PM PDT 24
Finished Jul 18 05:13:55 PM PDT 24
Peak memory 217768 kb
Host smart-c11d39aa-c92d-4889-b467-e0676f12281d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644448600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1644448600
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1492793934
Short name T777
Test name
Test status
Simulation time 219722203 ps
CPU time 8.95 seconds
Started Jul 18 05:13:45 PM PDT 24
Finished Jul 18 05:13:56 PM PDT 24
Peak memory 225472 kb
Host smart-b0bc8542-e285-42d9-ae87-bee242b166e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492793934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1492793934
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2931378264
Short name T659
Test name
Test status
Simulation time 920016511 ps
CPU time 10.8 seconds
Started Jul 18 05:13:45 PM PDT 24
Finished Jul 18 05:13:57 PM PDT 24
Peak memory 217836 kb
Host smart-07817140-8448-4b83-8ff7-d6f967285ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931378264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2931378264
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3653621588
Short name T791
Test name
Test status
Simulation time 324907891 ps
CPU time 4.07 seconds
Started Jul 18 05:13:48 PM PDT 24
Finished Jul 18 05:13:55 PM PDT 24
Peak memory 217184 kb
Host smart-4041f6de-c253-4cf5-810d-e95aa40544be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653621588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3653621588
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.98721650
Short name T359
Test name
Test status
Simulation time 875183859 ps
CPU time 24.23 seconds
Started Jul 18 05:13:44 PM PDT 24
Finished Jul 18 05:14:09 PM PDT 24
Peak memory 250520 kb
Host smart-2e63ca2e-226e-441e-8d60-e7a4a2b4b365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98721650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.98721650
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.539249543
Short name T783
Test name
Test status
Simulation time 125798383 ps
CPU time 6.91 seconds
Started Jul 18 05:13:48 PM PDT 24
Finished Jul 18 05:13:58 PM PDT 24
Peak memory 249980 kb
Host smart-ad24f28a-c5a3-42f5-ad91-56753bc0927f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539249543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.539249543
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3632827268
Short name T597
Test name
Test status
Simulation time 25227955290 ps
CPU time 233.63 seconds
Started Jul 18 05:13:43 PM PDT 24
Finished Jul 18 05:17:38 PM PDT 24
Peak memory 283320 kb
Host smart-4222d8df-c62d-4f24-9d66-4bb6ad9858aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632827268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3632827268
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.914631539
Short name T808
Test name
Test status
Simulation time 26941624 ps
CPU time 1.11 seconds
Started Jul 18 05:13:46 PM PDT 24
Finished Jul 18 05:13:49 PM PDT 24
Peak memory 211376 kb
Host smart-e3ead817-272d-4566-acd5-ddf82236f939
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914631539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.914631539
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2646594463
Short name T537
Test name
Test status
Simulation time 27272060 ps
CPU time 1.07 seconds
Started Jul 18 05:13:46 PM PDT 24
Finished Jul 18 05:13:50 PM PDT 24
Peak memory 208404 kb
Host smart-6b4433cf-3847-4c72-944d-faa3f76e3d06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646594463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2646594463
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.312235695
Short name T749
Test name
Test status
Simulation time 748034264 ps
CPU time 13.08 seconds
Started Jul 18 05:13:45 PM PDT 24
Finished Jul 18 05:14:00 PM PDT 24
Peak memory 217776 kb
Host smart-ac309e61-801e-4462-9191-540dc4999084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312235695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.312235695
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2342015375
Short name T430
Test name
Test status
Simulation time 230402166 ps
CPU time 3.56 seconds
Started Jul 18 05:13:48 PM PDT 24
Finished Jul 18 05:13:54 PM PDT 24
Peak memory 216848 kb
Host smart-3522c075-de60-41ee-acdd-142828b6949c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342015375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2342015375
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2574384435
Short name T345
Test name
Test status
Simulation time 7592748717 ps
CPU time 34.48 seconds
Started Jul 18 05:13:49 PM PDT 24
Finished Jul 18 05:14:26 PM PDT 24
Peak memory 218432 kb
Host smart-10fbbfbb-e534-4e7f-b1a0-df3d6072515f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574384435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2574384435
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3840289897
Short name T655
Test name
Test status
Simulation time 1705148724 ps
CPU time 12.91 seconds
Started Jul 18 05:13:47 PM PDT 24
Finished Jul 18 05:14:03 PM PDT 24
Peak memory 222828 kb
Host smart-c1258444-03aa-41d5-b648-a41bc0f1ac3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840289897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3840289897
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.4117230629
Short name T645
Test name
Test status
Simulation time 1398734507 ps
CPU time 5.5 seconds
Started Jul 18 05:13:47 PM PDT 24
Finished Jul 18 05:13:56 PM PDT 24
Peak memory 217128 kb
Host smart-b07b2fb3-d3c9-4d40-b80e-ecb75aa1060b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117230629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.4117230629
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.904796837
Short name T598
Test name
Test status
Simulation time 2312044855 ps
CPU time 87.71 seconds
Started Jul 18 05:13:46 PM PDT 24
Finished Jul 18 05:15:17 PM PDT 24
Peak memory 279528 kb
Host smart-e44d02d2-4757-4c5b-b741-89d0ec3ff0f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904796837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.904796837
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2971281799
Short name T859
Test name
Test status
Simulation time 418738538 ps
CPU time 17.6 seconds
Started Jul 18 05:13:50 PM PDT 24
Finished Jul 18 05:14:10 PM PDT 24
Peak memory 245716 kb
Host smart-b69c8536-50ee-4824-941e-d7c1d220833a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971281799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2971281799
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1001752890
Short name T403
Test name
Test status
Simulation time 200844308 ps
CPU time 3.58 seconds
Started Jul 18 05:13:47 PM PDT 24
Finished Jul 18 05:13:53 PM PDT 24
Peak memory 222176 kb
Host smart-9c444152-905b-49da-89b8-49708041322f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001752890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1001752890
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3763982187
Short name T244
Test name
Test status
Simulation time 3731572276 ps
CPU time 20.63 seconds
Started Jul 18 05:13:46 PM PDT 24
Finished Jul 18 05:14:10 PM PDT 24
Peak memory 219844 kb
Host smart-e752e2c2-d8a1-4fc1-9566-bc0c889ae594
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763982187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3763982187
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.816886779
Short name T247
Test name
Test status
Simulation time 522522885 ps
CPU time 9.73 seconds
Started Jul 18 05:13:48 PM PDT 24
Finished Jul 18 05:14:01 PM PDT 24
Peak memory 217756 kb
Host smart-5783e1ca-2523-4f15-af55-87cb818df9a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816886779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.816886779
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.547829291
Short name T795
Test name
Test status
Simulation time 1081796647 ps
CPU time 10.57 seconds
Started Jul 18 05:13:48 PM PDT 24
Finished Jul 18 05:14:01 PM PDT 24
Peak memory 225496 kb
Host smart-2380fa7d-e752-4967-8e06-9b96803999a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547829291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.547829291
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3846629588
Short name T474
Test name
Test status
Simulation time 946165724 ps
CPU time 7.75 seconds
Started Jul 18 05:13:48 PM PDT 24
Finished Jul 18 05:13:58 PM PDT 24
Peak memory 217840 kb
Host smart-4b75eaf6-1cb2-4e4c-978a-33e2af19b173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846629588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3846629588
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3579912937
Short name T78
Test name
Test status
Simulation time 19977788 ps
CPU time 0.87 seconds
Started Jul 18 05:13:44 PM PDT 24
Finished Jul 18 05:13:45 PM PDT 24
Peak memory 208344 kb
Host smart-34c4b601-e3b8-444f-977d-64f576690344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579912937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3579912937
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2204078389
Short name T330
Test name
Test status
Simulation time 333372652 ps
CPU time 31.98 seconds
Started Jul 18 05:13:47 PM PDT 24
Finished Jul 18 05:14:21 PM PDT 24
Peak memory 250548 kb
Host smart-2ea8aa45-fa47-4a8f-9a66-76f928af2819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204078389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2204078389
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2671588877
Short name T365
Test name
Test status
Simulation time 114331897 ps
CPU time 8.32 seconds
Started Jul 18 05:13:44 PM PDT 24
Finished Jul 18 05:13:53 PM PDT 24
Peak memory 250516 kb
Host smart-d9c73c9a-ab55-46c3-95f5-bfcb05569202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671588877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2671588877
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3750934056
Short name T786
Test name
Test status
Simulation time 4731252012 ps
CPU time 129.85 seconds
Started Jul 18 05:13:44 PM PDT 24
Finished Jul 18 05:15:55 PM PDT 24
Peak memory 271868 kb
Host smart-677200d0-04b3-461d-848e-97649f491636
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750934056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3750934056
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4225192686
Short name T405
Test name
Test status
Simulation time 13158399 ps
CPU time 0.94 seconds
Started Jul 18 05:13:46 PM PDT 24
Finished Jul 18 05:13:49 PM PDT 24
Peak memory 208152 kb
Host smart-adc8144a-2528-407e-b6c7-430ba942586c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225192686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.4225192686
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3737117784
Short name T721
Test name
Test status
Simulation time 19285463 ps
CPU time 0.87 seconds
Started Jul 18 05:13:52 PM PDT 24
Finished Jul 18 05:13:55 PM PDT 24
Peak memory 208384 kb
Host smart-dcd723f1-0d83-4d3f-8ac1-c40ccec7ea99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737117784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3737117784
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.209747235
Short name T593
Test name
Test status
Simulation time 443649518 ps
CPU time 9.55 seconds
Started Jul 18 05:13:53 PM PDT 24
Finished Jul 18 05:14:05 PM PDT 24
Peak memory 217736 kb
Host smart-5c1e4f3c-281b-4134-a00f-f6791e5a052c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209747235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.209747235
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3920528049
Short name T667
Test name
Test status
Simulation time 1741438965 ps
CPU time 11.17 seconds
Started Jul 18 05:13:50 PM PDT 24
Finished Jul 18 05:14:03 PM PDT 24
Peak memory 216904 kb
Host smart-02f6cb07-cdf6-475b-9f32-546a83f9c619
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920528049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3920528049
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3121643317
Short name T409
Test name
Test status
Simulation time 7850631311 ps
CPU time 56.47 seconds
Started Jul 18 05:13:51 PM PDT 24
Finished Jul 18 05:14:50 PM PDT 24
Peak memory 218404 kb
Host smart-414dcc50-b152-406f-9f1c-294c3c0e3ce1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121643317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3121643317
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1414867576
Short name T542
Test name
Test status
Simulation time 1571592224 ps
CPU time 21.38 seconds
Started Jul 18 05:13:52 PM PDT 24
Finished Jul 18 05:14:16 PM PDT 24
Peak memory 225080 kb
Host smart-9df2c466-7558-4dc0-8ebe-804b1f364bad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414867576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1414867576
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.27574785
Short name T820
Test name
Test status
Simulation time 1116689446 ps
CPU time 8.87 seconds
Started Jul 18 05:13:50 PM PDT 24
Finished Jul 18 05:14:01 PM PDT 24
Peak memory 217140 kb
Host smart-e1e6335f-9174-4180-88a1-4a12fa183315
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27574785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.27574785
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2193565644
Short name T744
Test name
Test status
Simulation time 9872503283 ps
CPU time 84.65 seconds
Started Jul 18 05:13:53 PM PDT 24
Finished Jul 18 05:15:20 PM PDT 24
Peak memory 272996 kb
Host smart-fee1dd66-ada3-4abb-a428-15db51fc08da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193565644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2193565644
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3974691703
Short name T250
Test name
Test status
Simulation time 1779183585 ps
CPU time 14.27 seconds
Started Jul 18 05:13:53 PM PDT 24
Finished Jul 18 05:14:09 PM PDT 24
Peak memory 225908 kb
Host smart-7492125d-c7d6-48da-9585-47b2ff9117af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974691703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3974691703
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1498668568
Short name T575
Test name
Test status
Simulation time 547454560 ps
CPU time 2.52 seconds
Started Jul 18 05:13:53 PM PDT 24
Finished Jul 18 05:13:58 PM PDT 24
Peak memory 217784 kb
Host smart-e2fb84d6-0912-4621-a6ae-ce6636384e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498668568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1498668568
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.495113060
Short name T534
Test name
Test status
Simulation time 263316778 ps
CPU time 14.02 seconds
Started Jul 18 05:13:50 PM PDT 24
Finished Jul 18 05:14:07 PM PDT 24
Peak memory 218444 kb
Host smart-82d25a67-8d46-43c3-a0b5-64e8bb17aab4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495113060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.495113060
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1038443394
Short name T582
Test name
Test status
Simulation time 452620156 ps
CPU time 10.25 seconds
Started Jul 18 05:13:51 PM PDT 24
Finished Jul 18 05:14:03 PM PDT 24
Peak memory 217780 kb
Host smart-f62558bb-92c5-4915-8613-89efd4565d06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038443394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1038443394
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.455302238
Short name T263
Test name
Test status
Simulation time 336620635 ps
CPU time 8.98 seconds
Started Jul 18 05:13:52 PM PDT 24
Finished Jul 18 05:14:03 PM PDT 24
Peak memory 225524 kb
Host smart-4551adeb-7615-4403-8695-852b243765f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455302238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.455302238
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2580773307
Short name T801
Test name
Test status
Simulation time 931750622 ps
CPU time 8.17 seconds
Started Jul 18 05:13:52 PM PDT 24
Finished Jul 18 05:14:02 PM PDT 24
Peak memory 217832 kb
Host smart-5baa243c-625b-4111-86af-0fb56b73dfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580773307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2580773307
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2837262794
Short name T692
Test name
Test status
Simulation time 62122906 ps
CPU time 3.23 seconds
Started Jul 18 05:13:50 PM PDT 24
Finished Jul 18 05:13:56 PM PDT 24
Peak memory 214124 kb
Host smart-97a22f72-529c-4660-9d0c-2361a869fc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837262794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2837262794
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1171173776
Short name T705
Test name
Test status
Simulation time 1353559587 ps
CPU time 29.47 seconds
Started Jul 18 05:13:46 PM PDT 24
Finished Jul 18 05:14:19 PM PDT 24
Peak memory 250680 kb
Host smart-5bb19406-e649-4c25-9f61-b7bfb0b514fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171173776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1171173776
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2032804173
Short name T813
Test name
Test status
Simulation time 75082265 ps
CPU time 4.09 seconds
Started Jul 18 05:13:51 PM PDT 24
Finished Jul 18 05:13:58 PM PDT 24
Peak memory 221984 kb
Host smart-c33200e3-6141-4f48-9525-e29dcce93a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032804173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2032804173
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.533917116
Short name T398
Test name
Test status
Simulation time 3718053633 ps
CPU time 61.81 seconds
Started Jul 18 05:13:52 PM PDT 24
Finished Jul 18 05:14:56 PM PDT 24
Peak memory 250568 kb
Host smart-b6a3c62f-11c9-4820-bf80-3a2d9761f06d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533917116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.533917116
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.619004470
Short name T676
Test name
Test status
Simulation time 36667636 ps
CPU time 0.81 seconds
Started Jul 18 05:13:48 PM PDT 24
Finished Jul 18 05:13:52 PM PDT 24
Peak memory 208216 kb
Host smart-e2d88955-349b-4fbb-8e52-9ebd6cab70f7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619004470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.619004470
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3365420679
Short name T750
Test name
Test status
Simulation time 22846042 ps
CPU time 1.29 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:14:08 PM PDT 24
Peak memory 208564 kb
Host smart-2c8f1e92-28e8-4308-816a-0c9f4af4b134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365420679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3365420679
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2922412110
Short name T243
Test name
Test status
Simulation time 1795505625 ps
CPU time 12.62 seconds
Started Jul 18 05:13:51 PM PDT 24
Finished Jul 18 05:14:06 PM PDT 24
Peak memory 225560 kb
Host smart-845f7076-f87c-43fa-b857-ada76e785b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922412110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2922412110
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2114382782
Short name T335
Test name
Test status
Simulation time 1538888524 ps
CPU time 5.98 seconds
Started Jul 18 05:14:01 PM PDT 24
Finished Jul 18 05:14:09 PM PDT 24
Peak memory 216712 kb
Host smart-febac484-acae-4d3f-b60e-23fff0736df4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114382782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2114382782
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3602486
Short name T354
Test name
Test status
Simulation time 3694143029 ps
CPU time 31.54 seconds
Started Jul 18 05:13:51 PM PDT 24
Finished Jul 18 05:14:25 PM PDT 24
Peak memory 225560 kb
Host smart-9783e950-7628-47cc-a79a-64cba5a7e234
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc
_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_erro
rs.3602486
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3112598893
Short name T802
Test name
Test status
Simulation time 917442784 ps
CPU time 11.41 seconds
Started Jul 18 05:13:54 PM PDT 24
Finished Jul 18 05:14:07 PM PDT 24
Peak memory 222956 kb
Host smart-43f37533-933a-47d2-88e3-d4a64f4f00b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112598893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3112598893
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.399903263
Short name T471
Test name
Test status
Simulation time 113792265 ps
CPU time 2.27 seconds
Started Jul 18 05:13:52 PM PDT 24
Finished Jul 18 05:13:57 PM PDT 24
Peak memory 217124 kb
Host smart-9260f09c-aabe-49d4-b977-c4d1f1f28099
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399903263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
399903263
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.931452394
Short name T373
Test name
Test status
Simulation time 1852512075 ps
CPU time 44.2 seconds
Started Jul 18 05:13:51 PM PDT 24
Finished Jul 18 05:14:38 PM PDT 24
Peak memory 251248 kb
Host smart-dc0179f3-06ed-44f5-b136-20dff47b3000
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931452394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.931452394
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.435178000
Short name T232
Test name
Test status
Simulation time 3589019511 ps
CPU time 6.35 seconds
Started Jul 18 05:13:51 PM PDT 24
Finished Jul 18 05:14:00 PM PDT 24
Peak memory 223092 kb
Host smart-5fbb622f-33c6-4b55-b01b-50208d775d68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435178000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.435178000
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1302090341
Short name T342
Test name
Test status
Simulation time 190921139 ps
CPU time 1.55 seconds
Started Jul 18 05:13:52 PM PDT 24
Finished Jul 18 05:13:56 PM PDT 24
Peak memory 217704 kb
Host smart-a5c0a90e-6e60-4abd-acad-ac8371103d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302090341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1302090341
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3013824813
Short name T312
Test name
Test status
Simulation time 335740143 ps
CPU time 14.82 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:14:23 PM PDT 24
Peak memory 218396 kb
Host smart-26111f4d-bc71-430e-8a94-d9bb6e591234
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013824813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3013824813
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.689063970
Short name T776
Test name
Test status
Simulation time 1157687680 ps
CPU time 12.5 seconds
Started Jul 18 05:14:11 PM PDT 24
Finished Jul 18 05:14:25 PM PDT 24
Peak memory 225484 kb
Host smart-1315b8aa-4f47-4eb6-9f2d-19d67b827ccc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689063970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.689063970
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.4281912787
Short name T493
Test name
Test status
Simulation time 303549518 ps
CPU time 7.96 seconds
Started Jul 18 05:14:13 PM PDT 24
Finished Jul 18 05:14:23 PM PDT 24
Peak memory 225484 kb
Host smart-8d2b099d-b1d6-4e91-923b-78afc23c43e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281912787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
4281912787
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1461227837
Short name T481
Test name
Test status
Simulation time 477006019 ps
CPU time 16.93 seconds
Started Jul 18 05:13:51 PM PDT 24
Finished Jul 18 05:14:10 PM PDT 24
Peak memory 217840 kb
Host smart-5caf54d6-fbbb-4f90-b0e3-48463e24ba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461227837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1461227837
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2623834886
Short name T272
Test name
Test status
Simulation time 70744260 ps
CPU time 1.89 seconds
Started Jul 18 05:13:52 PM PDT 24
Finished Jul 18 05:13:56 PM PDT 24
Peak memory 217184 kb
Host smart-329aae08-8bb7-4689-82bf-05c62a253138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623834886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2623834886
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.323163131
Short name T834
Test name
Test status
Simulation time 617367913 ps
CPU time 23.09 seconds
Started Jul 18 05:13:47 PM PDT 24
Finished Jul 18 05:14:13 PM PDT 24
Peak memory 250496 kb
Host smart-b17aeb90-78ce-4ab5-b3f0-d8966a7a8102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323163131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.323163131
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.138081714
Short name T246
Test name
Test status
Simulation time 341007303 ps
CPU time 8.34 seconds
Started Jul 18 05:13:50 PM PDT 24
Finished Jul 18 05:14:01 PM PDT 24
Peak memory 250492 kb
Host smart-efb4d8dc-dbc0-42cb-b1a3-de98108a8cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138081714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.138081714
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1330102738
Short name T227
Test name
Test status
Simulation time 1428409993 ps
CPU time 44.37 seconds
Started Jul 18 05:14:01 PM PDT 24
Finished Jul 18 05:14:47 PM PDT 24
Peak memory 225560 kb
Host smart-2022a2ec-6f9d-4dd4-a1c1-a6aa2a96305a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330102738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1330102738
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1080650073
Short name T290
Test name
Test status
Simulation time 45093562 ps
CPU time 1.02 seconds
Started Jul 18 05:13:53 PM PDT 24
Finished Jul 18 05:13:56 PM PDT 24
Peak memory 211476 kb
Host smart-25b55652-5db7-406d-b40d-3c14e3df7540
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080650073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1080650073
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1243237416
Short name T719
Test name
Test status
Simulation time 18108330 ps
CPU time 1.18 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:14:09 PM PDT 24
Peak memory 208524 kb
Host smart-780307c3-febd-487f-8e6a-33afc2197b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243237416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1243237416
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2831166467
Short name T441
Test name
Test status
Simulation time 233927979 ps
CPU time 10.5 seconds
Started Jul 18 05:14:03 PM PDT 24
Finished Jul 18 05:14:17 PM PDT 24
Peak memory 217768 kb
Host smart-b038eec7-3894-4598-8d44-1b1f78f574fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831166467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2831166467
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3397640113
Short name T448
Test name
Test status
Simulation time 1701770717 ps
CPU time 6.19 seconds
Started Jul 18 05:14:05 PM PDT 24
Finished Jul 18 05:14:15 PM PDT 24
Peak memory 217044 kb
Host smart-3c9c14fd-bf66-4aca-848b-717611408a4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397640113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3397640113
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3216458920
Short name T867
Test name
Test status
Simulation time 1560916290 ps
CPU time 23.88 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:14:32 PM PDT 24
Peak memory 218376 kb
Host smart-912241dc-2f40-467b-b2ee-f86ac01ac2de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216458920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3216458920
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2242717382
Short name T230
Test name
Test status
Simulation time 317834795 ps
CPU time 6.89 seconds
Started Jul 18 05:14:03 PM PDT 24
Finished Jul 18 05:14:13 PM PDT 24
Peak memory 222656 kb
Host smart-feda56fc-a6cb-4324-a299-efa7c43ca64c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242717382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2242717382
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1270460416
Short name T508
Test name
Test status
Simulation time 631549855 ps
CPU time 9.1 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:14:17 PM PDT 24
Peak memory 217116 kb
Host smart-f6bcd77c-519c-4a29-b06b-2547e7afe966
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270460416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1270460416
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3928061839
Short name T169
Test name
Test status
Simulation time 2158569307 ps
CPU time 56.42 seconds
Started Jul 18 05:14:05 PM PDT 24
Finished Jul 18 05:15:05 PM PDT 24
Peak memory 267008 kb
Host smart-3ae971cf-637a-4903-a1d2-014c91020bc4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928061839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3928061839
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.3649853931
Short name T527
Test name
Test status
Simulation time 800859799 ps
CPU time 11.37 seconds
Started Jul 18 05:14:11 PM PDT 24
Finished Jul 18 05:14:24 PM PDT 24
Peak memory 247124 kb
Host smart-6dc7fcf1-dd39-43e0-927f-3bba0686fd80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649853931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.3649853931
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3536795398
Short name T627
Test name
Test status
Simulation time 903113959 ps
CPU time 3.2 seconds
Started Jul 18 05:14:01 PM PDT 24
Finished Jul 18 05:14:05 PM PDT 24
Peak memory 217776 kb
Host smart-96b64f81-73fb-47d8-bb78-bcb12e7d5a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536795398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3536795398
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1559415002
Short name T836
Test name
Test status
Simulation time 393437911 ps
CPU time 12.99 seconds
Started Jul 18 05:14:12 PM PDT 24
Finished Jul 18 05:14:26 PM PDT 24
Peak memory 217744 kb
Host smart-885d9ece-f2b5-4e15-838b-26b91b573439
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559415002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1559415002
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3614906990
Short name T684
Test name
Test status
Simulation time 425673536 ps
CPU time 6.26 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:14:14 PM PDT 24
Peak memory 225528 kb
Host smart-0c14e62c-37c2-4799-a21d-1225a1975e62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614906990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3614906990
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.707888109
Short name T634
Test name
Test status
Simulation time 168153322 ps
CPU time 7.27 seconds
Started Jul 18 05:14:01 PM PDT 24
Finished Jul 18 05:14:10 PM PDT 24
Peak memory 225592 kb
Host smart-d77789f1-90b7-4789-8c56-9201315c7ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707888109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.707888109
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2919994923
Short name T338
Test name
Test status
Simulation time 38280285 ps
CPU time 2.38 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:14:09 PM PDT 24
Peak memory 213752 kb
Host smart-fa78f3f0-4d28-472d-99f4-0434215aba29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919994923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2919994923
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1495474261
Short name T614
Test name
Test status
Simulation time 142841950 ps
CPU time 22.97 seconds
Started Jul 18 05:14:02 PM PDT 24
Finished Jul 18 05:14:27 PM PDT 24
Peak memory 250508 kb
Host smart-0bbc13e9-335c-4053-a251-51d0d3cdda35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495474261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1495474261
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3754660632
Short name T252
Test name
Test status
Simulation time 282434069 ps
CPU time 3.94 seconds
Started Jul 18 05:14:00 PM PDT 24
Finished Jul 18 05:14:05 PM PDT 24
Peak memory 221880 kb
Host smart-f209e27f-5327-417e-a110-d50587d88752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754660632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3754660632
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3011611363
Short name T170
Test name
Test status
Simulation time 2676093364 ps
CPU time 92.41 seconds
Started Jul 18 05:14:01 PM PDT 24
Finished Jul 18 05:15:34 PM PDT 24
Peak memory 266972 kb
Host smart-6fdec760-20d9-4405-adfe-3bc9b66ca35d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011611363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3011611363
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.4014461432
Short name T358
Test name
Test status
Simulation time 13179611 ps
CPU time 0.82 seconds
Started Jul 18 05:14:03 PM PDT 24
Finished Jul 18 05:14:07 PM PDT 24
Peak memory 208352 kb
Host smart-6182621b-e874-4162-9f57-60bbb6337b30
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014461432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.4014461432
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3166043007
Short name T617
Test name
Test status
Simulation time 15909134 ps
CPU time 0.97 seconds
Started Jul 18 05:14:06 PM PDT 24
Finished Jul 18 05:14:11 PM PDT 24
Peak memory 208320 kb
Host smart-a0030a62-96f2-4f94-9deb-c5c13993dab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166043007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3166043007
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3598033750
Short name T666
Test name
Test status
Simulation time 373975523 ps
CPU time 16.05 seconds
Started Jul 18 05:14:02 PM PDT 24
Finished Jul 18 05:14:19 PM PDT 24
Peak memory 217728 kb
Host smart-031252eb-5ea0-4404-87a0-8d17907534c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598033750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3598033750
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2191119610
Short name T485
Test name
Test status
Simulation time 2510804419 ps
CPU time 16.4 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:14:24 PM PDT 24
Peak memory 217188 kb
Host smart-cb9250a5-407f-4f64-bd65-083a127d325f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191119610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2191119610
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1999415252
Short name T282
Test name
Test status
Simulation time 4692071767 ps
CPU time 43.14 seconds
Started Jul 18 05:14:05 PM PDT 24
Finished Jul 18 05:14:52 PM PDT 24
Peak memory 218420 kb
Host smart-ccb10d40-d937-4093-85f4-651dd1ce97e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999415252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1999415252
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.981209847
Short name T787
Test name
Test status
Simulation time 1013721125 ps
CPU time 12.21 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:14:19 PM PDT 24
Peak memory 223044 kb
Host smart-eab534ab-3ac7-4119-bb95-95ebb5dc6256
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981209847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.981209847
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1993602357
Short name T80
Test name
Test status
Simulation time 249825853 ps
CPU time 6.51 seconds
Started Jul 18 05:14:08 PM PDT 24
Finished Jul 18 05:14:18 PM PDT 24
Peak memory 217340 kb
Host smart-ed0eab10-9981-4595-9410-731a482bef4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993602357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1993602357
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3759359506
Short name T843
Test name
Test status
Simulation time 5997381954 ps
CPU time 58.4 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:15:06 PM PDT 24
Peak memory 277376 kb
Host smart-14d9c665-f7d4-4c0a-ba82-44316b79a925
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759359506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3759359506
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.965413511
Short name T486
Test name
Test status
Simulation time 1503550272 ps
CPU time 23.2 seconds
Started Jul 18 05:14:05 PM PDT 24
Finished Jul 18 05:14:32 PM PDT 24
Peak memory 250024 kb
Host smart-e1b12abb-ec5f-420c-a368-3e3ba8c78639
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965413511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.965413511
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.949072459
Short name T350
Test name
Test status
Simulation time 47956528 ps
CPU time 2.66 seconds
Started Jul 18 05:14:01 PM PDT 24
Finished Jul 18 05:14:05 PM PDT 24
Peak memory 221864 kb
Host smart-f948864b-561c-46e2-b1a8-e78ae3d6690e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949072459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.949072459
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2613768723
Short name T708
Test name
Test status
Simulation time 270776842 ps
CPU time 11.78 seconds
Started Jul 18 05:14:03 PM PDT 24
Finished Jul 18 05:14:17 PM PDT 24
Peak memory 217896 kb
Host smart-18c51342-4513-4b33-ac92-fe56cc4a9779
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613768723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2613768723
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2877005762
Short name T730
Test name
Test status
Simulation time 1097351897 ps
CPU time 9.69 seconds
Started Jul 18 05:14:05 PM PDT 24
Finished Jul 18 05:14:19 PM PDT 24
Peak memory 217788 kb
Host smart-a0b7f277-a2db-471f-960e-88040d1a62d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877005762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2877005762
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.86183747
Short name T602
Test name
Test status
Simulation time 296962617 ps
CPU time 9.49 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:14:17 PM PDT 24
Peak memory 225496 kb
Host smart-91c1d7e1-15ee-41dc-b1ca-12b21ec75db7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86183747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.86183747
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1940859587
Short name T316
Test name
Test status
Simulation time 401336571 ps
CPU time 14.54 seconds
Started Jul 18 05:14:01 PM PDT 24
Finished Jul 18 05:14:17 PM PDT 24
Peak memory 217824 kb
Host smart-b4b92304-9ddc-4099-81b7-589862c618a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940859587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1940859587
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1572662267
Short name T837
Test name
Test status
Simulation time 33341787 ps
CPU time 2.69 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:14:10 PM PDT 24
Peak memory 214156 kb
Host smart-8fa2ac62-06f9-421e-b03b-a630b3334efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572662267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1572662267
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1368102945
Short name T167
Test name
Test status
Simulation time 1007598462 ps
CPU time 28.94 seconds
Started Jul 18 05:14:05 PM PDT 24
Finished Jul 18 05:14:37 PM PDT 24
Peak memory 250484 kb
Host smart-fafead37-3920-4be0-8a99-3f746a7b07b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368102945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1368102945
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1426495927
Short name T177
Test name
Test status
Simulation time 89725371 ps
CPU time 8.09 seconds
Started Jul 18 05:14:08 PM PDT 24
Finished Jul 18 05:14:20 PM PDT 24
Peak memory 250140 kb
Host smart-545de233-e577-4faf-916e-0b74c2a8bea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426495927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1426495927
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.4082051014
Short name T256
Test name
Test status
Simulation time 7175060710 ps
CPU time 72.89 seconds
Started Jul 18 05:14:11 PM PDT 24
Finished Jul 18 05:15:26 PM PDT 24
Peak memory 271936 kb
Host smart-f1b0873f-e141-4690-bf03-e0ca393ff145
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082051014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.4082051014
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1650351979
Short name T107
Test name
Test status
Simulation time 20643506056 ps
CPU time 738.02 seconds
Started Jul 18 05:14:09 PM PDT 24
Finished Jul 18 05:26:30 PM PDT 24
Peak memory 447600 kb
Host smart-5c2ef27f-5bd2-43b5-97d8-e0a9fa7cefe6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1650351979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.1650351979
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.344563842
Short name T336
Test name
Test status
Simulation time 34609985 ps
CPU time 0.8 seconds
Started Jul 18 05:14:05 PM PDT 24
Finished Jul 18 05:14:10 PM PDT 24
Peak memory 208224 kb
Host smart-083a2632-b1e0-4ed6-8f5f-d7c7ea188d0f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344563842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.344563842
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1380227138
Short name T103
Test name
Test status
Simulation time 79924999 ps
CPU time 1.27 seconds
Started Jul 18 05:14:08 PM PDT 24
Finished Jul 18 05:14:13 PM PDT 24
Peak memory 208228 kb
Host smart-4de5304c-64c6-44eb-bcfd-06c254757b22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380227138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1380227138
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2658930873
Short name T620
Test name
Test status
Simulation time 463622644 ps
CPU time 10.5 seconds
Started Jul 18 05:14:05 PM PDT 24
Finished Jul 18 05:14:19 PM PDT 24
Peak memory 217732 kb
Host smart-92f5b4b7-d449-48aa-9ade-01c9e5ff6d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658930873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2658930873
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1076630287
Short name T682
Test name
Test status
Simulation time 1026183898 ps
CPU time 3.49 seconds
Started Jul 18 05:14:13 PM PDT 24
Finished Jul 18 05:14:18 PM PDT 24
Peak memory 216636 kb
Host smart-3c70f74f-2865-4451-a0a9-2d871505b0ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076630287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1076630287
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1794134698
Short name T435
Test name
Test status
Simulation time 2875607818 ps
CPU time 45.01 seconds
Started Jul 18 05:14:08 PM PDT 24
Finished Jul 18 05:14:57 PM PDT 24
Peak memory 218352 kb
Host smart-743fac48-571a-40f6-8a1c-7f95a06681a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794134698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1794134698
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1529256175
Short name T812
Test name
Test status
Simulation time 678272624 ps
CPU time 7.13 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:14:14 PM PDT 24
Peak memory 222856 kb
Host smart-0de7142c-630a-446b-994e-effb1f5ffbee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529256175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1529256175
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3407857997
Short name T6
Test name
Test status
Simulation time 232110115 ps
CPU time 3.64 seconds
Started Jul 18 05:14:05 PM PDT 24
Finished Jul 18 05:14:12 PM PDT 24
Peak memory 217108 kb
Host smart-7319d8eb-95a0-4991-80c3-16049fd55342
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407857997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3407857997
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2504248419
Short name T536
Test name
Test status
Simulation time 2495744379 ps
CPU time 36.4 seconds
Started Jul 18 05:14:01 PM PDT 24
Finished Jul 18 05:14:39 PM PDT 24
Peak memory 252364 kb
Host smart-8447ebd8-2887-45c8-a12a-d82d2096874f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504248419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2504248419
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.357630765
Short name T280
Test name
Test status
Simulation time 2381534102 ps
CPU time 35.66 seconds
Started Jul 18 05:14:00 PM PDT 24
Finished Jul 18 05:14:37 PM PDT 24
Peak memory 247044 kb
Host smart-7bfc3526-152f-4cc0-976c-b30392f63722
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357630765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.357630765
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2142543705
Short name T98
Test name
Test status
Simulation time 197289987 ps
CPU time 2.28 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:14:10 PM PDT 24
Peak memory 217744 kb
Host smart-b802760a-4f7a-4bcf-912e-06bb04024998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142543705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2142543705
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.337322579
Short name T339
Test name
Test status
Simulation time 291180421 ps
CPU time 9.55 seconds
Started Jul 18 05:14:03 PM PDT 24
Finished Jul 18 05:14:14 PM PDT 24
Peak memory 225676 kb
Host smart-295a30d5-9146-4db7-9625-17aeb928a69a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337322579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.337322579
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.727586744
Short name T212
Test name
Test status
Simulation time 321113340 ps
CPU time 10.75 seconds
Started Jul 18 05:14:13 PM PDT 24
Finished Jul 18 05:14:25 PM PDT 24
Peak memory 217852 kb
Host smart-23ef2d4a-ad3f-481c-aeb9-8c1fe4567518
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727586744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.727586744
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2987999729
Short name T649
Test name
Test status
Simulation time 582880784 ps
CPU time 10.94 seconds
Started Jul 18 05:14:13 PM PDT 24
Finished Jul 18 05:14:26 PM PDT 24
Peak memory 225484 kb
Host smart-8263b865-c6c0-4d00-908d-2dc6fd640b29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987999729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2987999729
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1271479605
Short name T702
Test name
Test status
Simulation time 535232368 ps
CPU time 11.65 seconds
Started Jul 18 05:14:03 PM PDT 24
Finished Jul 18 05:14:17 PM PDT 24
Peak memory 217812 kb
Host smart-a52902c4-4aaf-485f-85c6-b570f82d40f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271479605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1271479605
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3710831848
Short name T762
Test name
Test status
Simulation time 50967503 ps
CPU time 2.16 seconds
Started Jul 18 05:14:05 PM PDT 24
Finished Jul 18 05:14:11 PM PDT 24
Peak memory 213620 kb
Host smart-372fa735-d2b6-476e-8b76-1ac241a01b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710831848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3710831848
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.924925542
Short name T331
Test name
Test status
Simulation time 583033374 ps
CPU time 28.57 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:14:36 PM PDT 24
Peak memory 250584 kb
Host smart-528746e7-e9b6-42ec-b48a-a1134c9730c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924925542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.924925542
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3176788868
Short name T397
Test name
Test status
Simulation time 206478878 ps
CPU time 8.6 seconds
Started Jul 18 05:14:03 PM PDT 24
Finished Jul 18 05:14:15 PM PDT 24
Peak memory 250532 kb
Host smart-222a78b7-3d22-4a50-8c22-a309fc357e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176788868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3176788868
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1628775063
Short name T636
Test name
Test status
Simulation time 3262745808 ps
CPU time 62.35 seconds
Started Jul 18 05:14:05 PM PDT 24
Finished Jul 18 05:15:11 PM PDT 24
Peak memory 273372 kb
Host smart-7285764d-d056-4655-b3cc-7e49f83d20e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628775063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1628775063
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.3480392103
Short name T149
Test name
Test status
Simulation time 265422415016 ps
CPU time 322.61 seconds
Started Jul 18 05:14:02 PM PDT 24
Finished Jul 18 05:19:26 PM PDT 24
Peak memory 279284 kb
Host smart-d9ce4aae-dc48-4030-af7d-0b471f42c840
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3480392103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.3480392103
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.124772848
Short name T344
Test name
Test status
Simulation time 38544865 ps
CPU time 0.93 seconds
Started Jul 18 05:14:02 PM PDT 24
Finished Jul 18 05:14:05 PM PDT 24
Peak memory 211340 kb
Host smart-fb31810f-830e-40b8-a56f-b41ab6723315
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124772848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.124772848
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1713961322
Short name T491
Test name
Test status
Simulation time 31073385 ps
CPU time 0.97 seconds
Started Jul 18 05:14:17 PM PDT 24
Finished Jul 18 05:14:19 PM PDT 24
Peak memory 208408 kb
Host smart-265b97fe-a301-45a7-8461-a3637cfd6dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713961322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1713961322
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.548113547
Short name T503
Test name
Test status
Simulation time 1209980258 ps
CPU time 14.64 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:14:21 PM PDT 24
Peak memory 217872 kb
Host smart-708f4f35-eae8-4da8-a100-a7fbfa663123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548113547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.548113547
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.716900556
Short name T424
Test name
Test status
Simulation time 926617430 ps
CPU time 4.71 seconds
Started Jul 18 05:14:02 PM PDT 24
Finished Jul 18 05:14:09 PM PDT 24
Peak memory 216708 kb
Host smart-69fb1e4b-595e-4eb8-b31a-759a3020d913
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716900556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.716900556
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3007614900
Short name T301
Test name
Test status
Simulation time 1427920566 ps
CPU time 27.1 seconds
Started Jul 18 05:14:07 PM PDT 24
Finished Jul 18 05:14:38 PM PDT 24
Peak memory 217768 kb
Host smart-5a0bbbe9-a58a-4c6d-a257-7a6597d53fe2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007614900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3007614900
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2903801647
Short name T209
Test name
Test status
Simulation time 1703327192 ps
CPU time 12.77 seconds
Started Jul 18 05:14:02 PM PDT 24
Finished Jul 18 05:14:17 PM PDT 24
Peak memory 221664 kb
Host smart-9741af10-443e-42fb-8e3f-4724f36ceb65
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903801647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2903801647
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.499617461
Short name T502
Test name
Test status
Simulation time 901954050 ps
CPU time 3.73 seconds
Started Jul 18 05:14:12 PM PDT 24
Finished Jul 18 05:14:17 PM PDT 24
Peak memory 217088 kb
Host smart-b45b822d-dcec-41bf-9c65-6827e350c815
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499617461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
499617461
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3479273425
Short name T394
Test name
Test status
Simulation time 4004421274 ps
CPU time 47.46 seconds
Started Jul 18 05:14:07 PM PDT 24
Finished Jul 18 05:14:59 PM PDT 24
Peak memory 275092 kb
Host smart-71a91a69-4d0b-45ff-a783-7f37bc8ac2cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479273425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3479273425
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2051509441
Short name T611
Test name
Test status
Simulation time 441162593 ps
CPU time 12.37 seconds
Started Jul 18 05:14:11 PM PDT 24
Finished Jul 18 05:14:26 PM PDT 24
Peak memory 250432 kb
Host smart-72c31163-62ef-4882-801c-ee04f8b54898
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051509441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2051509441
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.4101915831
Short name T341
Test name
Test status
Simulation time 29181642 ps
CPU time 1.42 seconds
Started Jul 18 05:14:12 PM PDT 24
Finished Jul 18 05:14:15 PM PDT 24
Peak memory 217836 kb
Host smart-8ac6621d-7e2d-4eb4-ac8a-063dd200dd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101915831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.4101915831
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.788630611
Short name T210
Test name
Test status
Simulation time 261094216 ps
CPU time 12.61 seconds
Started Jul 18 05:14:06 PM PDT 24
Finished Jul 18 05:14:23 PM PDT 24
Peak memory 225560 kb
Host smart-a2d6dd46-4eef-46e5-b917-9b71c1e16d8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788630611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.788630611
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3807184735
Short name T211
Test name
Test status
Simulation time 320610053 ps
CPU time 14.66 seconds
Started Jul 18 05:14:23 PM PDT 24
Finished Jul 18 05:14:38 PM PDT 24
Peak memory 217732 kb
Host smart-3a0db471-651a-4171-82f1-ba7e3e49a116
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807184735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3807184735
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3927107742
Short name T838
Test name
Test status
Simulation time 1030678400 ps
CPU time 7.91 seconds
Started Jul 18 05:14:07 PM PDT 24
Finished Jul 18 05:14:19 PM PDT 24
Peak memory 225504 kb
Host smart-bbf341a7-16eb-4fb2-b820-4e94b53b03b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927107742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3927107742
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.543345438
Short name T18
Test name
Test status
Simulation time 1252839521 ps
CPU time 10.35 seconds
Started Jul 18 05:14:03 PM PDT 24
Finished Jul 18 05:14:17 PM PDT 24
Peak memory 225508 kb
Host smart-ff75f8dd-75a0-4ac3-880b-4483c2e3061c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543345438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.543345438
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.4192254532
Short name T271
Test name
Test status
Simulation time 400421116 ps
CPU time 4.54 seconds
Started Jul 18 05:14:03 PM PDT 24
Finished Jul 18 05:14:09 PM PDT 24
Peak memory 217212 kb
Host smart-5a0e3203-e85c-4a2e-96e7-568395ca1792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192254532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.4192254532
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2254437150
Short name T693
Test name
Test status
Simulation time 1840148181 ps
CPU time 28.82 seconds
Started Jul 18 05:14:04 PM PDT 24
Finished Jul 18 05:14:37 PM PDT 24
Peak memory 250368 kb
Host smart-a58e4460-e127-4d4d-92d7-d3ebbf734145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254437150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2254437150
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.4101385151
Short name T504
Test name
Test status
Simulation time 256989427 ps
CPU time 8.09 seconds
Started Jul 18 05:14:10 PM PDT 24
Finished Jul 18 05:14:21 PM PDT 24
Peak memory 250508 kb
Host smart-bc01d2cd-6257-4d38-bbbb-ae37d3c06650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101385151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.4101385151
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2997734094
Short name T815
Test name
Test status
Simulation time 30230676427 ps
CPU time 197.52 seconds
Started Jul 18 05:14:22 PM PDT 24
Finished Jul 18 05:17:41 PM PDT 24
Peak memory 278128 kb
Host smart-59eff39d-11ae-4c82-bfe0-aebdb7cae10c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997734094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2997734094
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2632400088
Short name T675
Test name
Test status
Simulation time 22914909 ps
CPU time 1.11 seconds
Started Jul 18 05:14:08 PM PDT 24
Finished Jul 18 05:14:13 PM PDT 24
Peak memory 217116 kb
Host smart-0c2ab503-2555-404e-9905-492f4fcdb545
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632400088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2632400088
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3399059224
Short name T589
Test name
Test status
Simulation time 37222518 ps
CPU time 0.96 seconds
Started Jul 18 05:14:34 PM PDT 24
Finished Jul 18 05:14:36 PM PDT 24
Peak memory 208632 kb
Host smart-d88cc162-ba75-48ff-b7d7-11a83788e7e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399059224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3399059224
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2201488665
Short name T827
Test name
Test status
Simulation time 274300298 ps
CPU time 9.97 seconds
Started Jul 18 05:14:33 PM PDT 24
Finished Jul 18 05:14:44 PM PDT 24
Peak memory 217820 kb
Host smart-0f2e5f86-ad32-4f4a-adaf-15d7ba6c1ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201488665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2201488665
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3121623527
Short name T9
Test name
Test status
Simulation time 124336727 ps
CPU time 2.37 seconds
Started Jul 18 05:14:38 PM PDT 24
Finished Jul 18 05:14:43 PM PDT 24
Peak memory 216672 kb
Host smart-16c19026-76d4-474a-bca2-d59a39ce454b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121623527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3121623527
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.262317155
Short name T829
Test name
Test status
Simulation time 1564179840 ps
CPU time 50.38 seconds
Started Jul 18 05:14:33 PM PDT 24
Finished Jul 18 05:15:25 PM PDT 24
Peak memory 225660 kb
Host smart-38b2cefe-8a0c-42ff-832c-03d43fdfb2ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262317155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.262317155
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.4215287651
Short name T623
Test name
Test status
Simulation time 117514654 ps
CPU time 3.18 seconds
Started Jul 18 05:14:38 PM PDT 24
Finished Jul 18 05:14:43 PM PDT 24
Peak memory 221420 kb
Host smart-7dd7ed9a-93fd-4117-8358-c8e3e7a81cf9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215287651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.4215287651
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.701136810
Short name T389
Test name
Test status
Simulation time 318308280 ps
CPU time 9.54 seconds
Started Jul 18 05:14:35 PM PDT 24
Finished Jul 18 05:14:45 PM PDT 24
Peak memory 217124 kb
Host smart-5d068683-272b-4598-8b1f-2518a22db7be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701136810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
701136810
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1177758551
Short name T745
Test name
Test status
Simulation time 10782157534 ps
CPU time 74.88 seconds
Started Jul 18 05:14:32 PM PDT 24
Finished Jul 18 05:15:48 PM PDT 24
Peak memory 250508 kb
Host smart-a159879b-5efe-484a-8ec6-f8327a116c6e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177758551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1177758551
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3410091031
Short name T818
Test name
Test status
Simulation time 2734363664 ps
CPU time 26.88 seconds
Started Jul 18 05:14:33 PM PDT 24
Finished Jul 18 05:15:01 PM PDT 24
Peak memory 250528 kb
Host smart-50496261-b84f-43ac-a4f5-409f921cc23f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410091031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3410091031
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1558088062
Short name T445
Test name
Test status
Simulation time 60498988 ps
CPU time 1.87 seconds
Started Jul 18 05:14:32 PM PDT 24
Finished Jul 18 05:14:35 PM PDT 24
Peak memory 221724 kb
Host smart-b378033a-0b57-4255-acad-1e572ac0c57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558088062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1558088062
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.483622099
Short name T260
Test name
Test status
Simulation time 1347387224 ps
CPU time 12.13 seconds
Started Jul 18 05:14:35 PM PDT 24
Finished Jul 18 05:14:48 PM PDT 24
Peak memory 218512 kb
Host smart-612320fa-107b-4f83-b153-23e8b4f1dee0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483622099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.483622099
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.502365765
Short name T613
Test name
Test status
Simulation time 635028904 ps
CPU time 16.98 seconds
Started Jul 18 05:14:46 PM PDT 24
Finished Jul 18 05:15:04 PM PDT 24
Peak memory 225472 kb
Host smart-1a36d231-e2d3-4dfe-bc4d-654633c229aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502365765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.502365765
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3505782520
Short name T414
Test name
Test status
Simulation time 510321519 ps
CPU time 10.02 seconds
Started Jul 18 05:14:33 PM PDT 24
Finished Jul 18 05:14:44 PM PDT 24
Peak memory 225576 kb
Host smart-c45d458b-cb33-47fe-8d18-ef01faa07e2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505782520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3505782520
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2214366790
Short name T473
Test name
Test status
Simulation time 954621311 ps
CPU time 6.8 seconds
Started Jul 18 05:14:33 PM PDT 24
Finished Jul 18 05:14:41 PM PDT 24
Peak memory 217840 kb
Host smart-02bcc0b0-745d-45aa-ba68-d71e39275203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214366790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2214366790
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2631348567
Short name T289
Test name
Test status
Simulation time 83288106 ps
CPU time 2.87 seconds
Started Jul 18 05:14:22 PM PDT 24
Finished Jul 18 05:14:26 PM PDT 24
Peak memory 217164 kb
Host smart-8c2e2433-1fe9-4bf1-a0c3-61f2ccdf83bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631348567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2631348567
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2029955062
Short name T437
Test name
Test status
Simulation time 430299374 ps
CPU time 23.83 seconds
Started Jul 18 05:14:36 PM PDT 24
Finished Jul 18 05:15:01 PM PDT 24
Peak memory 250412 kb
Host smart-f131d214-9ca6-45cd-bd61-1b0e69d2bc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029955062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2029955062
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3650056162
Short name T97
Test name
Test status
Simulation time 51531367 ps
CPU time 3.19 seconds
Started Jul 18 05:14:33 PM PDT 24
Finished Jul 18 05:14:38 PM PDT 24
Peak memory 221832 kb
Host smart-c9e23c3e-e9aa-417e-9703-29dd381bca9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650056162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3650056162
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2365610497
Short name T690
Test name
Test status
Simulation time 10329985566 ps
CPU time 148.69 seconds
Started Jul 18 05:14:39 PM PDT 24
Finished Jul 18 05:17:10 PM PDT 24
Peak memory 229608 kb
Host smart-4f00ac92-0b75-4e31-83f3-05c0b5a26d09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365610497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2365610497
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.70155782
Short name T146
Test name
Test status
Simulation time 37493996579 ps
CPU time 1180.55 seconds
Started Jul 18 05:14:32 PM PDT 24
Finished Jul 18 05:34:14 PM PDT 24
Peak memory 447232 kb
Host smart-0881dc39-41a1-4ae4-9e05-b8c21370c734
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=70155782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.70155782
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2233766211
Short name T236
Test name
Test status
Simulation time 48700970 ps
CPU time 1.05 seconds
Started Jul 18 05:14:40 PM PDT 24
Finished Jul 18 05:14:44 PM PDT 24
Peak memory 208396 kb
Host smart-83cecef3-bd31-41f4-8efc-422736b4bb26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233766211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2233766211
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2333684126
Short name T48
Test name
Test status
Simulation time 277289076 ps
CPU time 8.9 seconds
Started Jul 18 05:14:40 PM PDT 24
Finished Jul 18 05:14:51 PM PDT 24
Peak memory 217792 kb
Host smart-2dc191e9-d689-4d2b-96fa-f45a24db585c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333684126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2333684126
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3533337476
Short name T182
Test name
Test status
Simulation time 419276546 ps
CPU time 4.35 seconds
Started Jul 18 05:14:39 PM PDT 24
Finished Jul 18 05:14:46 PM PDT 24
Peak memory 216664 kb
Host smart-81e8779c-6607-44df-a099-5bef1f208e85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533337476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3533337476
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2692614963
Short name T444
Test name
Test status
Simulation time 8359386730 ps
CPU time 65.68 seconds
Started Jul 18 05:14:34 PM PDT 24
Finished Jul 18 05:15:40 PM PDT 24
Peak memory 219180 kb
Host smart-b99584e4-be7e-40cb-b242-b0430a88622f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692614963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2692614963
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1099608015
Short name T581
Test name
Test status
Simulation time 1739929909 ps
CPU time 7.55 seconds
Started Jul 18 05:14:39 PM PDT 24
Finished Jul 18 05:14:49 PM PDT 24
Peak memory 223816 kb
Host smart-3f774f0e-1fba-4138-8388-ddd3df214600
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099608015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1099608015
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.254312961
Short name T686
Test name
Test status
Simulation time 191183603 ps
CPU time 3.46 seconds
Started Jul 18 05:14:39 PM PDT 24
Finished Jul 18 05:14:45 PM PDT 24
Peak memory 217108 kb
Host smart-4d44ab7e-029a-435e-be94-388b50e8b723
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254312961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
254312961
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1904084075
Short name T755
Test name
Test status
Simulation time 5371064135 ps
CPU time 34.48 seconds
Started Jul 18 05:14:34 PM PDT 24
Finished Jul 18 05:15:09 PM PDT 24
Peak memory 250744 kb
Host smart-7a5c95e4-19f1-497c-9efe-8c1e758b1fe9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904084075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1904084075
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.621293371
Short name T594
Test name
Test status
Simulation time 5287950764 ps
CPU time 25.79 seconds
Started Jul 18 05:14:32 PM PDT 24
Finished Jul 18 05:14:59 PM PDT 24
Peak memory 250532 kb
Host smart-1536bf1c-9529-45dd-854b-cc88ccd23f5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621293371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.621293371
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1797392166
Short name T540
Test name
Test status
Simulation time 35505797 ps
CPU time 1.98 seconds
Started Jul 18 05:14:38 PM PDT 24
Finished Jul 18 05:14:43 PM PDT 24
Peak memory 217864 kb
Host smart-8c955b4b-a854-408c-9e9b-ac0b87eba9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797392166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1797392166
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.2117987594
Short name T796
Test name
Test status
Simulation time 684451430 ps
CPU time 17.18 seconds
Started Jul 18 05:14:32 PM PDT 24
Finished Jul 18 05:14:51 PM PDT 24
Peak memory 217892 kb
Host smart-d5c4450f-fffe-46af-8766-56826f01979c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117987594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2117987594
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.421437117
Short name T386
Test name
Test status
Simulation time 787854624 ps
CPU time 17.7 seconds
Started Jul 18 05:14:36 PM PDT 24
Finished Jul 18 05:14:55 PM PDT 24
Peak memory 225496 kb
Host smart-8de71fba-d6fd-4335-8fc8-994b2f9b55ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421437117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.421437117
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1558256998
Short name T267
Test name
Test status
Simulation time 454641929 ps
CPU time 15.77 seconds
Started Jul 18 05:14:35 PM PDT 24
Finished Jul 18 05:14:52 PM PDT 24
Peak memory 225500 kb
Host smart-bc6622c8-f94d-4527-90f4-dc92f777ba1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558256998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1558256998
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2078732409
Short name T356
Test name
Test status
Simulation time 438748655 ps
CPU time 10.05 seconds
Started Jul 18 05:14:35 PM PDT 24
Finished Jul 18 05:14:46 PM PDT 24
Peak memory 217864 kb
Host smart-a5f4f928-db88-4b26-a168-8a5471889879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078732409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2078732409
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2637557862
Short name T475
Test name
Test status
Simulation time 155669299 ps
CPU time 4.81 seconds
Started Jul 18 05:14:38 PM PDT 24
Finished Jul 18 05:14:46 PM PDT 24
Peak memory 217208 kb
Host smart-9f131819-6924-4818-a706-dab935edae8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637557862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2637557862
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3394102241
Short name T268
Test name
Test status
Simulation time 953248469 ps
CPU time 17.88 seconds
Started Jul 18 05:14:39 PM PDT 24
Finished Jul 18 05:14:59 PM PDT 24
Peak memory 250420 kb
Host smart-2dd6f9fd-f631-422b-87c7-ec837a3e8222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394102241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3394102241
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2865391056
Short name T646
Test name
Test status
Simulation time 191846683 ps
CPU time 12.37 seconds
Started Jul 18 05:14:33 PM PDT 24
Finished Jul 18 05:14:46 PM PDT 24
Peak memory 250524 kb
Host smart-e7017889-a0ac-41e4-9ea1-668c5d16dd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865391056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2865391056
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3189390235
Short name T55
Test name
Test status
Simulation time 7531868638 ps
CPU time 227.38 seconds
Started Jul 18 05:14:36 PM PDT 24
Finished Jul 18 05:18:24 PM PDT 24
Peak memory 260520 kb
Host smart-19b0fe2c-ef74-43a6-9ea5-0c5e2323661c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189390235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3189390235
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.4044619937
Short name T44
Test name
Test status
Simulation time 20447174 ps
CPU time 0.75 seconds
Started Jul 18 05:14:34 PM PDT 24
Finished Jul 18 05:14:36 PM PDT 24
Peak memory 208420 kb
Host smart-42898406-3fd3-417b-ba9a-632530b003f4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044619937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.4044619937
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3359976943
Short name T622
Test name
Test status
Simulation time 17655463 ps
CPU time 1.15 seconds
Started Jul 18 05:13:07 PM PDT 24
Finished Jul 18 05:13:12 PM PDT 24
Peak memory 208444 kb
Host smart-13769190-bf7d-47b8-a19e-2ac51b1c63f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359976943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3359976943
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2310826391
Short name T105
Test name
Test status
Simulation time 465875245 ps
CPU time 15.48 seconds
Started Jul 18 05:13:06 PM PDT 24
Finished Jul 18 05:13:25 PM PDT 24
Peak memory 217604 kb
Host smart-a6da7687-662c-467a-ad48-fb87a9672b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310826391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2310826391
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1981166420
Short name T422
Test name
Test status
Simulation time 208678368 ps
CPU time 3.26 seconds
Started Jul 18 05:13:01 PM PDT 24
Finished Jul 18 05:13:06 PM PDT 24
Peak memory 216796 kb
Host smart-8417586e-5be9-49c2-8076-5712e16e7ae2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981166420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1981166420
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2126884173
Short name T591
Test name
Test status
Simulation time 917268063 ps
CPU time 29.89 seconds
Started Jul 18 05:13:01 PM PDT 24
Finished Jul 18 05:13:32 PM PDT 24
Peak memory 217776 kb
Host smart-439b0714-09f0-41a8-96bf-35464497691a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126884173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2126884173
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.768372400
Short name T311
Test name
Test status
Simulation time 4805975990 ps
CPU time 22.13 seconds
Started Jul 18 05:13:05 PM PDT 24
Finished Jul 18 05:13:29 PM PDT 24
Peak memory 217284 kb
Host smart-7d9d5528-4fed-431d-ab7e-7759edb5bf83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768372400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.768372400
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.633687586
Short name T429
Test name
Test status
Simulation time 295899086 ps
CPU time 3.65 seconds
Started Jul 18 05:13:07 PM PDT 24
Finished Jul 18 05:13:14 PM PDT 24
Peak memory 222464 kb
Host smart-a241a072-c0ff-41dc-93c6-45d830fd2275
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633687586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.633687586
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3014501856
Short name T25
Test name
Test status
Simulation time 838397942 ps
CPU time 23.96 seconds
Started Jul 18 05:13:07 PM PDT 24
Finished Jul 18 05:13:34 PM PDT 24
Peak memory 217136 kb
Host smart-a07d3c1a-13af-44ba-856a-2280e1f1e216
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014501856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3014501856
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3327491681
Short name T380
Test name
Test status
Simulation time 202266892 ps
CPU time 6.46 seconds
Started Jul 18 05:13:04 PM PDT 24
Finished Jul 18 05:13:12 PM PDT 24
Peak memory 217084 kb
Host smart-15dc2764-ce27-4561-833b-1c7baf889da9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327491681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3327491681
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4245830468
Short name T552
Test name
Test status
Simulation time 2654486977 ps
CPU time 64.98 seconds
Started Jul 18 05:13:06 PM PDT 24
Finished Jul 18 05:14:14 PM PDT 24
Peak memory 275176 kb
Host smart-8f97a367-9817-4293-be10-d64653b24c4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245830468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.4245830468
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.360783360
Short name T228
Test name
Test status
Simulation time 282039949 ps
CPU time 14.47 seconds
Started Jul 18 05:13:05 PM PDT 24
Finished Jul 18 05:13:22 PM PDT 24
Peak memory 250428 kb
Host smart-b4e0b1b3-d6c9-4998-9802-2b8472e73ba2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360783360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.360783360
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.811261577
Short name T822
Test name
Test status
Simulation time 71505681 ps
CPU time 3.08 seconds
Started Jul 18 05:13:04 PM PDT 24
Finished Jul 18 05:13:09 PM PDT 24
Peak memory 222136 kb
Host smart-7284dde3-abe8-409b-824b-e5466d2ef534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811261577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.811261577
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3315641974
Short name T19
Test name
Test status
Simulation time 1123794912 ps
CPU time 10.75 seconds
Started Jul 18 05:13:07 PM PDT 24
Finished Jul 18 05:13:21 PM PDT 24
Peak memory 217136 kb
Host smart-11ca2251-46b5-4080-8c9f-e864ab173806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315641974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3315641974
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2258428002
Short name T93
Test name
Test status
Simulation time 149822680 ps
CPU time 22.66 seconds
Started Jul 18 05:13:07 PM PDT 24
Finished Jul 18 05:13:34 PM PDT 24
Peak memory 269128 kb
Host smart-ac2dbc54-9b55-4645-b6ba-9d9427c8abd9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258428002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2258428002
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1240894203
Short name T349
Test name
Test status
Simulation time 372025049 ps
CPU time 15.69 seconds
Started Jul 18 05:13:09 PM PDT 24
Finished Jul 18 05:13:28 PM PDT 24
Peak memory 217916 kb
Host smart-a7893b77-dbd6-4be2-9be0-f0394a7714e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240894203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1240894203
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1327290032
Short name T35
Test name
Test status
Simulation time 210390235 ps
CPU time 6.96 seconds
Started Jul 18 05:13:07 PM PDT 24
Finished Jul 18 05:13:17 PM PDT 24
Peak memory 217708 kb
Host smart-e3b1bf6d-34e0-4233-a702-c21c71430526
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327290032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1327290032
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3088345174
Short name T497
Test name
Test status
Simulation time 352514774 ps
CPU time 12.55 seconds
Started Jul 18 05:13:07 PM PDT 24
Finished Jul 18 05:13:24 PM PDT 24
Peak memory 225524 kb
Host smart-36a82247-40bc-47d3-8af7-3966c0cefd6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088345174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
088345174
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1040214235
Short name T248
Test name
Test status
Simulation time 1192746194 ps
CPU time 11.14 seconds
Started Jul 18 05:13:07 PM PDT 24
Finished Jul 18 05:13:22 PM PDT 24
Peak memory 224296 kb
Host smart-1d1600ac-3ffc-47c1-8102-250ac189c126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040214235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1040214235
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.669173737
Short name T287
Test name
Test status
Simulation time 70097426 ps
CPU time 2.84 seconds
Started Jul 18 05:12:46 PM PDT 24
Finished Jul 18 05:12:53 PM PDT 24
Peak memory 217164 kb
Host smart-d897a548-1928-459b-9b13-6074e4673263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669173737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.669173737
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3650325106
Short name T229
Test name
Test status
Simulation time 300778908 ps
CPU time 30.29 seconds
Started Jul 18 05:13:07 PM PDT 24
Finished Jul 18 05:13:41 PM PDT 24
Peak memory 250520 kb
Host smart-bac2311b-7a40-499e-aa1f-9e54acaf8cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650325106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3650325106
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3586019728
Short name T60
Test name
Test status
Simulation time 301180248 ps
CPU time 7.69 seconds
Started Jul 18 05:13:04 PM PDT 24
Finished Jul 18 05:13:13 PM PDT 24
Peak memory 250488 kb
Host smart-e0403f44-d50e-4716-9208-ca4940a86daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586019728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3586019728
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2655558793
Short name T173
Test name
Test status
Simulation time 6772430133 ps
CPU time 51.5 seconds
Started Jul 18 05:13:06 PM PDT 24
Finished Jul 18 05:14:01 PM PDT 24
Peak memory 250564 kb
Host smart-a6f15951-dc1c-4668-9dfb-f0097a9a5cfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655558793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2655558793
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4053916916
Short name T733
Test name
Test status
Simulation time 118055949 ps
CPU time 0.92 seconds
Started Jul 18 05:12:45 PM PDT 24
Finished Jul 18 05:12:48 PM PDT 24
Peak memory 211388 kb
Host smart-4e7632e1-4873-4e67-bfe0-75a6ec87b0d9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053916916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.4053916916
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3124833655
Short name T747
Test name
Test status
Simulation time 55927680 ps
CPU time 0.93 seconds
Started Jul 18 05:14:38 PM PDT 24
Finished Jul 18 05:14:41 PM PDT 24
Peak memory 208360 kb
Host smart-81f1a5bc-eeb0-4131-95b6-8a466392de8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124833655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3124833655
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.846474224
Short name T710
Test name
Test status
Simulation time 282967362 ps
CPU time 9.48 seconds
Started Jul 18 05:14:31 PM PDT 24
Finished Jul 18 05:14:41 PM PDT 24
Peak memory 217772 kb
Host smart-233dc988-307e-4bfd-982a-a615c20af148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846474224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.846474224
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.787033978
Short name T10
Test name
Test status
Simulation time 2281371163 ps
CPU time 12.35 seconds
Started Jul 18 05:14:38 PM PDT 24
Finished Jul 18 05:14:52 PM PDT 24
Peak memory 216976 kb
Host smart-7bef1e15-9a8c-45a9-aa69-d0163846b25d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787033978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.787033978
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1275060134
Short name T526
Test name
Test status
Simulation time 465363797 ps
CPU time 4.66 seconds
Started Jul 18 05:14:32 PM PDT 24
Finished Jul 18 05:14:38 PM PDT 24
Peak memory 217796 kb
Host smart-1006ba8c-049a-406f-818e-e46bc0efc972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275060134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1275060134
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.4012114021
Short name T781
Test name
Test status
Simulation time 1775200468 ps
CPU time 16.96 seconds
Started Jul 18 05:14:37 PM PDT 24
Finished Jul 18 05:14:56 PM PDT 24
Peak memory 219468 kb
Host smart-57b6d796-5cc2-4165-bd8b-9c673c0db3dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012114021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.4012114021
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2830495075
Short name T307
Test name
Test status
Simulation time 1061620197 ps
CPU time 7.91 seconds
Started Jul 18 05:14:32 PM PDT 24
Finished Jul 18 05:14:41 PM PDT 24
Peak memory 217788 kb
Host smart-f31d9a06-6469-4057-8db7-a3c15f47eb32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830495075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2830495075
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3547709014
Short name T163
Test name
Test status
Simulation time 213806861 ps
CPU time 6.67 seconds
Started Jul 18 05:14:39 PM PDT 24
Finished Jul 18 05:14:48 PM PDT 24
Peak memory 225372 kb
Host smart-8ab8fa7c-a8b2-4f41-a730-c96d8181defb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547709014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3547709014
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2884411209
Short name T399
Test name
Test status
Simulation time 1282349036 ps
CPU time 9.7 seconds
Started Jul 18 05:14:37 PM PDT 24
Finished Jul 18 05:14:49 PM PDT 24
Peak memory 225564 kb
Host smart-6d4544e9-c868-40d0-88d1-6d3b805e75ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884411209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2884411209
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.898972096
Short name T233
Test name
Test status
Simulation time 73324111 ps
CPU time 2.07 seconds
Started Jul 18 05:14:44 PM PDT 24
Finished Jul 18 05:14:47 PM PDT 24
Peak memory 213744 kb
Host smart-b2f31e32-bd86-49f3-a558-a9938c2fa948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898972096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.898972096
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3346868876
Short name T352
Test name
Test status
Simulation time 233512207 ps
CPU time 25.62 seconds
Started Jul 18 05:14:38 PM PDT 24
Finished Jul 18 05:15:06 PM PDT 24
Peak memory 250500 kb
Host smart-7bf52b24-1cf0-4be8-bcde-ee25f50578e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346868876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3346868876
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2758814726
Short name T483
Test name
Test status
Simulation time 61763875 ps
CPU time 8.05 seconds
Started Jul 18 05:14:36 PM PDT 24
Finished Jul 18 05:14:45 PM PDT 24
Peak memory 250460 kb
Host smart-940c7160-964f-4efc-b706-50f0ca19c3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758814726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2758814726
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3277521473
Short name T446
Test name
Test status
Simulation time 2185613064 ps
CPU time 22.08 seconds
Started Jul 18 05:14:38 PM PDT 24
Finished Jul 18 05:15:03 PM PDT 24
Peak memory 225620 kb
Host smart-81ad72c7-f4b7-4670-a88b-c2ca5398a370
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277521473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3277521473
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.631820283
Short name T371
Test name
Test status
Simulation time 40363495 ps
CPU time 0.87 seconds
Started Jul 18 05:14:38 PM PDT 24
Finished Jul 18 05:14:41 PM PDT 24
Peak memory 211412 kb
Host smart-1ef1b16b-8b4f-460f-9f8e-aa9533193f35
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631820283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.631820283
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2671204836
Short name T691
Test name
Test status
Simulation time 17014189 ps
CPU time 1.15 seconds
Started Jul 18 05:14:40 PM PDT 24
Finished Jul 18 05:14:44 PM PDT 24
Peak memory 208412 kb
Host smart-28dcfe63-40bc-4b92-a6d8-10de4f96e002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671204836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2671204836
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1475847767
Short name T528
Test name
Test status
Simulation time 325353549 ps
CPU time 16.05 seconds
Started Jul 18 05:14:38 PM PDT 24
Finished Jul 18 05:14:55 PM PDT 24
Peak memory 217824 kb
Host smart-9693891c-7107-437f-9376-18290f6f546f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475847767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1475847767
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2864863418
Short name T703
Test name
Test status
Simulation time 11635440325 ps
CPU time 26.72 seconds
Started Jul 18 05:14:37 PM PDT 24
Finished Jul 18 05:15:05 PM PDT 24
Peak memory 217252 kb
Host smart-8a6eb8d4-775d-4745-aab7-8e79560d4c3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864863418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2864863418
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.4223739953
Short name T461
Test name
Test status
Simulation time 84413060 ps
CPU time 2.97 seconds
Started Jul 18 05:14:38 PM PDT 24
Finished Jul 18 05:14:43 PM PDT 24
Peak memory 217776 kb
Host smart-376ab0cc-97a1-44f8-986a-716b6958fd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223739953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.4223739953
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1344437454
Short name T513
Test name
Test status
Simulation time 650612041 ps
CPU time 18.88 seconds
Started Jul 18 05:14:31 PM PDT 24
Finished Jul 18 05:14:50 PM PDT 24
Peak memory 218532 kb
Host smart-66a5fce6-5501-44b3-a5da-6f33cc965c07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344437454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1344437454
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.4074169808
Short name T507
Test name
Test status
Simulation time 3749798175 ps
CPU time 23.79 seconds
Started Jul 18 05:14:40 PM PDT 24
Finished Jul 18 05:15:07 PM PDT 24
Peak memory 217836 kb
Host smart-2fccaa87-6f42-47d1-b6de-c0ec9e955c5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074169808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.4074169808
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1729150930
Short name T361
Test name
Test status
Simulation time 403328170 ps
CPU time 9.45 seconds
Started Jul 18 05:14:39 PM PDT 24
Finished Jul 18 05:14:51 PM PDT 24
Peak memory 225504 kb
Host smart-7214cb80-53fc-41ea-b34a-23ca8b379699
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729150930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1729150930
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1940258804
Short name T304
Test name
Test status
Simulation time 405099471 ps
CPU time 9.26 seconds
Started Jul 18 05:14:38 PM PDT 24
Finished Jul 18 05:14:49 PM PDT 24
Peak memory 225540 kb
Host smart-52d6db14-7435-4a9a-8002-a9a7087b83e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940258804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1940258804
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.413704024
Short name T73
Test name
Test status
Simulation time 70166288 ps
CPU time 2.59 seconds
Started Jul 18 05:14:34 PM PDT 24
Finished Jul 18 05:14:37 PM PDT 24
Peak memory 222984 kb
Host smart-25255b56-d887-46ca-a9db-f49b4fdbe12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413704024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.413704024
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.4208566032
Short name T249
Test name
Test status
Simulation time 222920591 ps
CPU time 25.29 seconds
Started Jul 18 05:14:34 PM PDT 24
Finished Jul 18 05:15:00 PM PDT 24
Peak memory 250540 kb
Host smart-c0d8f3bf-5328-4807-985e-0c084b1383e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208566032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.4208566032
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3879191704
Short name T742
Test name
Test status
Simulation time 268511413 ps
CPU time 8.56 seconds
Started Jul 18 05:14:38 PM PDT 24
Finished Jul 18 05:14:49 PM PDT 24
Peak memory 250536 kb
Host smart-d3a53d33-fa34-4a97-89d7-eb9673ed2708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879191704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3879191704
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1550897948
Short name T664
Test name
Test status
Simulation time 13250973847 ps
CPU time 169.49 seconds
Started Jul 18 05:14:35 PM PDT 24
Finished Jul 18 05:17:26 PM PDT 24
Peak memory 252072 kb
Host smart-520d6d69-7cb6-4056-80d7-b094aae32feb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550897948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1550897948
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.2326464668
Short name T144
Test name
Test status
Simulation time 64377545244 ps
CPU time 539.2 seconds
Started Jul 18 05:14:40 PM PDT 24
Finished Jul 18 05:23:42 PM PDT 24
Peak memory 283328 kb
Host smart-d393c4e4-fdb9-49fa-929d-1c44ea615c9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2326464668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.2326464668
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1071317612
Short name T157
Test name
Test status
Simulation time 23726451 ps
CPU time 1 seconds
Started Jul 18 05:14:38 PM PDT 24
Finished Jul 18 05:14:41 PM PDT 24
Peak memory 208648 kb
Host smart-35d9356f-77de-4c09-b6d8-350297f21908
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071317612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1071317612
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1969265972
Short name T313
Test name
Test status
Simulation time 84581143 ps
CPU time 1.13 seconds
Started Jul 18 05:15:00 PM PDT 24
Finished Jul 18 05:15:03 PM PDT 24
Peak memory 208412 kb
Host smart-97fc5cc5-6939-4df6-afdb-b24b099ecf38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969265972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1969265972
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.4176523199
Short name T393
Test name
Test status
Simulation time 976213027 ps
CPU time 19.33 seconds
Started Jul 18 05:14:56 PM PDT 24
Finished Jul 18 05:15:18 PM PDT 24
Peak memory 217800 kb
Host smart-320891f9-e917-4cba-8976-0d1e91764190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176523199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.4176523199
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1091665672
Short name T694
Test name
Test status
Simulation time 341969267 ps
CPU time 9.92 seconds
Started Jul 18 05:14:53 PM PDT 24
Finished Jul 18 05:15:05 PM PDT 24
Peak memory 216988 kb
Host smart-aace8591-deee-4480-806f-18b2bd628486
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091665672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1091665672
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1089300451
Short name T725
Test name
Test status
Simulation time 156848600 ps
CPU time 1.42 seconds
Started Jul 18 05:14:51 PM PDT 24
Finished Jul 18 05:14:54 PM PDT 24
Peak memory 217800 kb
Host smart-b38ce660-1d7a-4a26-a356-6fff0f908ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089300451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1089300451
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.4029455946
Short name T155
Test name
Test status
Simulation time 3470706184 ps
CPU time 20.02 seconds
Started Jul 18 05:14:52 PM PDT 24
Finished Jul 18 05:15:13 PM PDT 24
Peak memory 219528 kb
Host smart-5af7eee8-9682-467d-8408-c08ad8f9aba5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029455946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.4029455946
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1421613849
Short name T805
Test name
Test status
Simulation time 878220042 ps
CPU time 13.52 seconds
Started Jul 18 05:14:50 PM PDT 24
Finished Jul 18 05:15:05 PM PDT 24
Peak memory 217760 kb
Host smart-60cc5e73-6307-43f6-ad42-37917cd53502
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421613849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1421613849
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.381617721
Short name T629
Test name
Test status
Simulation time 694030830 ps
CPU time 8.52 seconds
Started Jul 18 05:14:54 PM PDT 24
Finished Jul 18 05:15:05 PM PDT 24
Peak memory 225464 kb
Host smart-43736b0c-de4a-4e76-af29-3129e319613d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381617721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.381617721
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1093117600
Short name T318
Test name
Test status
Simulation time 270570418 ps
CPU time 7.61 seconds
Started Jul 18 05:14:54 PM PDT 24
Finished Jul 18 05:15:04 PM PDT 24
Peak memory 218060 kb
Host smart-20345949-0fdc-4f06-b7b9-ba95cc5f5a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093117600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1093117600
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2883806559
Short name T300
Test name
Test status
Simulation time 103952086 ps
CPU time 3.91 seconds
Started Jul 18 05:14:53 PM PDT 24
Finished Jul 18 05:14:58 PM PDT 24
Peak memory 217188 kb
Host smart-b993dd09-ed5b-4394-889a-de4eec0d1c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883806559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2883806559
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1582350689
Short name T608
Test name
Test status
Simulation time 1142914820 ps
CPU time 28.26 seconds
Started Jul 18 05:14:55 PM PDT 24
Finished Jul 18 05:15:26 PM PDT 24
Peak memory 250512 kb
Host smart-da95eff9-f237-4cf4-9fdc-529732793db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582350689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1582350689
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.276064317
Short name T322
Test name
Test status
Simulation time 194313372 ps
CPU time 5.69 seconds
Started Jul 18 05:14:58 PM PDT 24
Finished Jul 18 05:15:06 PM PDT 24
Peak memory 246480 kb
Host smart-309a74ae-b18a-415a-9d41-6ed454cc37d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276064317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.276064317
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3557209074
Short name T224
Test name
Test status
Simulation time 36132412755 ps
CPU time 148.02 seconds
Started Jul 18 05:14:53 PM PDT 24
Finished Jul 18 05:17:22 PM PDT 24
Peak memory 266932 kb
Host smart-103ad39b-5297-4e70-9b41-023c288fda07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557209074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3557209074
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.2513857969
Short name T314
Test name
Test status
Simulation time 68184772672 ps
CPU time 621.79 seconds
Started Jul 18 05:14:53 PM PDT 24
Finished Jul 18 05:25:16 PM PDT 24
Peak memory 283444 kb
Host smart-5a924fcc-7e3b-42ef-8d2b-8e73841d8524
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2513857969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.2513857969
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1203288973
Short name T711
Test name
Test status
Simulation time 33353585 ps
CPU time 1.02 seconds
Started Jul 18 05:14:55 PM PDT 24
Finished Jul 18 05:14:59 PM PDT 24
Peak memory 211344 kb
Host smart-74f52120-b8ac-4b29-a4b9-5fe8825eb63e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203288973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1203288973
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3002437073
Short name T328
Test name
Test status
Simulation time 15816990 ps
CPU time 0.89 seconds
Started Jul 18 05:14:53 PM PDT 24
Finished Jul 18 05:14:55 PM PDT 24
Peak memory 208316 kb
Host smart-c0de50d2-e7b2-4b7f-9078-d545f4ab1ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002437073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3002437073
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2059436611
Short name T525
Test name
Test status
Simulation time 230604140 ps
CPU time 12.47 seconds
Started Jul 18 05:14:51 PM PDT 24
Finished Jul 18 05:15:05 PM PDT 24
Peak memory 217852 kb
Host smart-f17077c2-14ac-4e12-a8ae-5f8e3e0d736c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059436611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2059436611
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2455278482
Short name T29
Test name
Test status
Simulation time 169121303 ps
CPU time 3.03 seconds
Started Jul 18 05:14:51 PM PDT 24
Finished Jul 18 05:14:55 PM PDT 24
Peak memory 216756 kb
Host smart-808abe49-ba63-443b-bf56-5c3f900abbf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455278482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2455278482
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1142476069
Short name T603
Test name
Test status
Simulation time 109715248 ps
CPU time 4.76 seconds
Started Jul 18 05:14:57 PM PDT 24
Finished Jul 18 05:15:05 PM PDT 24
Peak memory 217772 kb
Host smart-485292ab-456c-4200-ba0c-edc441609912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142476069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1142476069
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2943742142
Short name T769
Test name
Test status
Simulation time 1044605137 ps
CPU time 12.12 seconds
Started Jul 18 05:14:55 PM PDT 24
Finished Jul 18 05:15:10 PM PDT 24
Peak memory 217828 kb
Host smart-1840e2c0-ef18-4c78-b000-d07b98c41a8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943742142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2943742142
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1229228119
Short name T825
Test name
Test status
Simulation time 376636227 ps
CPU time 9.21 seconds
Started Jul 18 05:14:55 PM PDT 24
Finished Jul 18 05:15:07 PM PDT 24
Peak memory 225504 kb
Host smart-66ea5f7b-3dfa-455d-9615-78125d1fe2df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229228119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1229228119
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1888405988
Short name T308
Test name
Test status
Simulation time 1622678540 ps
CPU time 10.03 seconds
Started Jul 18 05:14:55 PM PDT 24
Finished Jul 18 05:15:08 PM PDT 24
Peak memory 225588 kb
Host smart-0240d0a9-8c2f-4537-86fa-a343a0c5e8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888405988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1888405988
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1077606500
Short name T810
Test name
Test status
Simulation time 14989761 ps
CPU time 1.1 seconds
Started Jul 18 05:14:53 PM PDT 24
Finished Jul 18 05:14:56 PM PDT 24
Peak memory 211672 kb
Host smart-8b5688a2-fd53-42d1-aab4-5771baa686b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077606500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1077606500
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.2339037613
Short name T38
Test name
Test status
Simulation time 887099360 ps
CPU time 25.54 seconds
Started Jul 18 05:14:53 PM PDT 24
Finished Jul 18 05:15:21 PM PDT 24
Peak memory 250460 kb
Host smart-835057fe-d5ca-437d-8846-2ef6e992dad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339037613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2339037613
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.4122425158
Short name T767
Test name
Test status
Simulation time 101987130 ps
CPU time 3.07 seconds
Started Jul 18 05:14:50 PM PDT 24
Finished Jul 18 05:14:54 PM PDT 24
Peak memory 221796 kb
Host smart-087f6838-d382-41b5-87f3-919a363e326f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122425158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.4122425158
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3257931495
Short name T514
Test name
Test status
Simulation time 54549653657 ps
CPU time 173.45 seconds
Started Jul 18 05:14:58 PM PDT 24
Finished Jul 18 05:17:54 PM PDT 24
Peak memory 283360 kb
Host smart-0c5afe96-c6b6-4363-b654-2402e8fa8d94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257931495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3257931495
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.3537510198
Short name T171
Test name
Test status
Simulation time 81217933360 ps
CPU time 491.46 seconds
Started Jul 18 05:14:54 PM PDT 24
Finished Jul 18 05:23:09 PM PDT 24
Peak memory 442732 kb
Host smart-7f51bd28-3e64-41e2-8f57-5f6af05cd730
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3537510198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.3537510198
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1636132188
Short name T222
Test name
Test status
Simulation time 11336936 ps
CPU time 0.95 seconds
Started Jul 18 05:14:55 PM PDT 24
Finished Jul 18 05:14:59 PM PDT 24
Peak memory 208640 kb
Host smart-b75338c2-d628-4ecf-b998-a8f925c0132d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636132188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1636132188
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.586292841
Short name T81
Test name
Test status
Simulation time 13390376 ps
CPU time 1.04 seconds
Started Jul 18 05:14:55 PM PDT 24
Finished Jul 18 05:14:59 PM PDT 24
Peak memory 208380 kb
Host smart-446fc28f-988f-4dbd-be55-b9e87e36035c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586292841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.586292841
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2310980912
Short name T543
Test name
Test status
Simulation time 3406059147 ps
CPU time 19.99 seconds
Started Jul 18 05:14:55 PM PDT 24
Finished Jul 18 05:15:18 PM PDT 24
Peak memory 217932 kb
Host smart-dc2ab9ab-e13a-4072-b74f-44d91c55434e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310980912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2310980912
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.887625289
Short name T329
Test name
Test status
Simulation time 886775605 ps
CPU time 10.29 seconds
Started Jul 18 05:14:52 PM PDT 24
Finished Jul 18 05:15:03 PM PDT 24
Peak memory 217040 kb
Host smart-6f0c9cb1-31fd-4b3c-b60f-fe9f3afdf878
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887625289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.887625289
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1183706408
Short name T778
Test name
Test status
Simulation time 1093517929 ps
CPU time 3.6 seconds
Started Jul 18 05:14:54 PM PDT 24
Finished Jul 18 05:14:59 PM PDT 24
Peak memory 217792 kb
Host smart-0e31a33a-590c-4ab2-a2d6-e50e791a5363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183706408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1183706408
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2989672113
Short name T370
Test name
Test status
Simulation time 465169525 ps
CPU time 14.34 seconds
Started Jul 18 05:14:53 PM PDT 24
Finished Jul 18 05:15:08 PM PDT 24
Peak memory 218376 kb
Host smart-21f5bfe7-d832-4cde-b0fc-25fc63bfc968
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989672113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2989672113
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1821688455
Short name T379
Test name
Test status
Simulation time 1392524174 ps
CPU time 8.41 seconds
Started Jul 18 05:14:55 PM PDT 24
Finished Jul 18 05:15:07 PM PDT 24
Peak memory 217764 kb
Host smart-257d5c0a-9e4e-4853-b522-194a255a0de7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821688455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1821688455
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1370325212
Short name T257
Test name
Test status
Simulation time 913061111 ps
CPU time 9.8 seconds
Started Jul 18 05:14:52 PM PDT 24
Finished Jul 18 05:15:03 PM PDT 24
Peak memory 224672 kb
Host smart-7f49a85e-6e83-4bd1-9cfe-c9af42175340
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370325212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1370325212
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2642240516
Short name T854
Test name
Test status
Simulation time 340018714 ps
CPU time 12.94 seconds
Started Jul 18 05:14:54 PM PDT 24
Finished Jul 18 05:15:08 PM PDT 24
Peak memory 225536 kb
Host smart-f8490c8e-f99f-4965-9af5-f512089e8865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642240516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2642240516
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1324904357
Short name T237
Test name
Test status
Simulation time 67423951 ps
CPU time 1.27 seconds
Started Jul 18 05:14:57 PM PDT 24
Finished Jul 18 05:15:01 PM PDT 24
Peak memory 213132 kb
Host smart-30477f86-9ff2-497d-9365-41cc5de89135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324904357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1324904357
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.4041848613
Short name T823
Test name
Test status
Simulation time 347609089 ps
CPU time 21.64 seconds
Started Jul 18 05:14:54 PM PDT 24
Finished Jul 18 05:15:18 PM PDT 24
Peak memory 250748 kb
Host smart-132870f4-1dd2-49f9-b691-e1a513fcc17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041848613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4041848613
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3646009564
Short name T772
Test name
Test status
Simulation time 68575135 ps
CPU time 7.52 seconds
Started Jul 18 05:14:55 PM PDT 24
Finished Jul 18 05:15:06 PM PDT 24
Peak memory 250560 kb
Host smart-a03c0c15-ccf1-4ee1-a361-76d6bc3a4a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646009564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3646009564
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3917137306
Short name T860
Test name
Test status
Simulation time 8632875371 ps
CPU time 80.31 seconds
Started Jul 18 05:14:54 PM PDT 24
Finished Jul 18 05:16:17 PM PDT 24
Peak memory 250556 kb
Host smart-a1d339e3-8c31-4f44-9f71-f2cb9ed8bc85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917137306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3917137306
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1187645248
Short name T216
Test name
Test status
Simulation time 17013909 ps
CPU time 1.02 seconds
Started Jul 18 05:14:58 PM PDT 24
Finished Jul 18 05:15:01 PM PDT 24
Peak memory 211412 kb
Host smart-662fa02f-c7d3-479b-9a4c-e1b95ee648b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187645248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1187645248
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.166698320
Short name T800
Test name
Test status
Simulation time 27555098 ps
CPU time 1.28 seconds
Started Jul 18 05:14:55 PM PDT 24
Finished Jul 18 05:15:00 PM PDT 24
Peak memory 208504 kb
Host smart-105d6398-4d37-4909-bd69-58189b27c27f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166698320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.166698320
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1253911237
Short name T606
Test name
Test status
Simulation time 291269541 ps
CPU time 12.39 seconds
Started Jul 18 05:14:52 PM PDT 24
Finished Jul 18 05:15:05 PM PDT 24
Peak memory 217804 kb
Host smart-bfd0d498-ccb5-458f-9eb2-4069ebb89ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253911237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1253911237
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3260136637
Short name T463
Test name
Test status
Simulation time 472984032 ps
CPU time 12.77 seconds
Started Jul 18 05:14:52 PM PDT 24
Finished Jul 18 05:15:06 PM PDT 24
Peak memory 216852 kb
Host smart-3bff94b3-8ce2-40bf-97a2-f3a5e80d24bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260136637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3260136637
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1768837639
Short name T478
Test name
Test status
Simulation time 46025687 ps
CPU time 1.58 seconds
Started Jul 18 05:14:56 PM PDT 24
Finished Jul 18 05:15:01 PM PDT 24
Peak memory 217796 kb
Host smart-3a86ba21-b52c-43c4-a290-c5a79a0fdffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768837639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1768837639
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.667305972
Short name T57
Test name
Test status
Simulation time 1627701863 ps
CPU time 11.97 seconds
Started Jul 18 05:14:59 PM PDT 24
Finished Jul 18 05:15:13 PM PDT 24
Peak memory 218416 kb
Host smart-9b7fb1d8-6d16-452a-bc65-9fed4511798d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667305972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.667305972
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.4090793012
Short name T421
Test name
Test status
Simulation time 2624752687 ps
CPU time 11.47 seconds
Started Jul 18 05:14:54 PM PDT 24
Finished Jul 18 05:15:08 PM PDT 24
Peak memory 217808 kb
Host smart-0e080e33-77ec-4c97-bd29-dd4b986cb234
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090793012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.4090793012
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.808261579
Short name T828
Test name
Test status
Simulation time 369879009 ps
CPU time 13.94 seconds
Started Jul 18 05:14:56 PM PDT 24
Finished Jul 18 05:15:13 PM PDT 24
Peak memory 225464 kb
Host smart-d4c4e78c-02d4-487f-ab38-de6fb2a99f47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808261579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.808261579
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2174761581
Short name T452
Test name
Test status
Simulation time 1074261768 ps
CPU time 8.31 seconds
Started Jul 18 05:14:55 PM PDT 24
Finished Jul 18 05:15:07 PM PDT 24
Peak memory 217836 kb
Host smart-0e39a279-3d6a-4a59-8040-a659ed0571fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174761581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2174761581
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2227992123
Short name T625
Test name
Test status
Simulation time 79970370 ps
CPU time 2.95 seconds
Started Jul 18 05:14:56 PM PDT 24
Finished Jul 18 05:15:02 PM PDT 24
Peak memory 214068 kb
Host smart-e0a40bd6-0bbf-4354-b682-2e4fb16b7cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227992123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2227992123
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2175008257
Short name T785
Test name
Test status
Simulation time 164247430 ps
CPU time 18.25 seconds
Started Jul 18 05:14:53 PM PDT 24
Finished Jul 18 05:15:13 PM PDT 24
Peak memory 250520 kb
Host smart-f5b381c0-e457-4c3f-8844-42a2aeb0a5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175008257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2175008257
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3591521717
Short name T310
Test name
Test status
Simulation time 239422746 ps
CPU time 6.52 seconds
Started Jul 18 05:14:57 PM PDT 24
Finished Jul 18 05:15:07 PM PDT 24
Peak memory 249928 kb
Host smart-9e9b810b-aa5c-46b0-805f-c0fcc2de4ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591521717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3591521717
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3960059331
Short name T652
Test name
Test status
Simulation time 8606782397 ps
CPU time 294.41 seconds
Started Jul 18 05:14:55 PM PDT 24
Finished Jul 18 05:19:53 PM PDT 24
Peak memory 269828 kb
Host smart-973b1a6b-4cdf-43b9-80d5-77efa25ee010
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960059331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3960059331
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3983354076
Short name T519
Test name
Test status
Simulation time 30436217 ps
CPU time 1.29 seconds
Started Jul 18 05:14:56 PM PDT 24
Finished Jul 18 05:15:01 PM PDT 24
Peak memory 217204 kb
Host smart-ceb9f4ab-5f49-4f8d-ab8d-09e2042c5dbb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983354076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3983354076
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1901857800
Short name T713
Test name
Test status
Simulation time 25123100 ps
CPU time 0.9 seconds
Started Jul 18 05:15:10 PM PDT 24
Finished Jul 18 05:15:13 PM PDT 24
Peak memory 208208 kb
Host smart-9af19978-3d1e-4b91-bbd3-599ae6f43cd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901857800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1901857800
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.4194599335
Short name T782
Test name
Test status
Simulation time 1508105842 ps
CPU time 16.88 seconds
Started Jul 18 05:15:00 PM PDT 24
Finished Jul 18 05:15:18 PM PDT 24
Peak memory 217804 kb
Host smart-429b1488-8701-42d7-8748-0a257962a747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194599335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.4194599335
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3949276872
Short name T457
Test name
Test status
Simulation time 1250056849 ps
CPU time 28.87 seconds
Started Jul 18 05:14:55 PM PDT 24
Finished Jul 18 05:15:27 PM PDT 24
Peak memory 216984 kb
Host smart-b6e5818c-c230-4478-8d2b-43bc9ee484d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949276872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3949276872
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3154179627
Short name T333
Test name
Test status
Simulation time 51399360 ps
CPU time 2.35 seconds
Started Jul 18 05:14:52 PM PDT 24
Finished Jul 18 05:14:56 PM PDT 24
Peak memory 217748 kb
Host smart-bf2ca916-31d6-4011-a07a-308ed27a51cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154179627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3154179627
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3313748895
Short name T564
Test name
Test status
Simulation time 2384844511 ps
CPU time 23.09 seconds
Started Jul 18 05:14:53 PM PDT 24
Finished Jul 18 05:15:19 PM PDT 24
Peak memory 219580 kb
Host smart-515ee1ca-caac-4226-b782-b9b4e8ece252
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313748895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3313748895
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.95982893
Short name T439
Test name
Test status
Simulation time 447808488 ps
CPU time 12.15 seconds
Started Jul 18 05:14:50 PM PDT 24
Finished Jul 18 05:15:03 PM PDT 24
Peak memory 217876 kb
Host smart-e94d85ae-ca90-4d29-8cb6-b188ff229b06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95982893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_dig
est.95982893
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.89056646
Short name T773
Test name
Test status
Simulation time 687916768 ps
CPU time 6.94 seconds
Started Jul 18 05:14:56 PM PDT 24
Finished Jul 18 05:15:06 PM PDT 24
Peak memory 224780 kb
Host smart-1569d96e-50f4-4903-9977-f1fd03cb6111
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89056646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.89056646
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.305686740
Short name T739
Test name
Test status
Simulation time 459127071 ps
CPU time 10.82 seconds
Started Jul 18 05:14:57 PM PDT 24
Finished Jul 18 05:15:11 PM PDT 24
Peak memory 225556 kb
Host smart-b9cba6a9-1ff2-48ec-9163-cef45ebd79d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305686740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.305686740
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2296959159
Short name T530
Test name
Test status
Simulation time 29725826 ps
CPU time 1.8 seconds
Started Jul 18 05:14:58 PM PDT 24
Finished Jul 18 05:15:02 PM PDT 24
Peak memory 217180 kb
Host smart-6982aace-c8c9-4b36-825e-e9a1d55078c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296959159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2296959159
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.4028382377
Short name T685
Test name
Test status
Simulation time 269315536 ps
CPU time 27.78 seconds
Started Jul 18 05:15:00 PM PDT 24
Finished Jul 18 05:15:29 PM PDT 24
Peak memory 250540 kb
Host smart-b742fb26-3693-4e2a-9300-b39730fd3ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028382377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.4028382377
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3831768946
Short name T697
Test name
Test status
Simulation time 72835235 ps
CPU time 4.01 seconds
Started Jul 18 05:14:55 PM PDT 24
Finished Jul 18 05:15:02 PM PDT 24
Peak memory 222016 kb
Host smart-7a48dda0-409a-4c35-a161-d22064a59b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831768946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3831768946
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.720567939
Short name T554
Test name
Test status
Simulation time 1249412922 ps
CPU time 13.47 seconds
Started Jul 18 05:14:55 PM PDT 24
Finished Jul 18 05:15:11 PM PDT 24
Peak memory 227096 kb
Host smart-4330fefd-fa03-4e9a-801c-4b564ca5dc2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720567939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.720567939
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.2404880759
Short name T147
Test name
Test status
Simulation time 7464325140 ps
CPU time 162.9 seconds
Started Jul 18 05:15:11 PM PDT 24
Finished Jul 18 05:17:56 PM PDT 24
Peak memory 279212 kb
Host smart-d3309839-8fd2-42b8-8be5-7901ac15781e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2404880759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.2404880759
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.666714529
Short name T16
Test name
Test status
Simulation time 13387169 ps
CPU time 1 seconds
Started Jul 18 05:14:56 PM PDT 24
Finished Jul 18 05:15:00 PM PDT 24
Peak memory 208440 kb
Host smart-1e075764-c3e4-47b5-a56a-34bff007af81
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666714529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.666714529
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1969408388
Short name T714
Test name
Test status
Simulation time 45798318 ps
CPU time 0.99 seconds
Started Jul 18 05:15:10 PM PDT 24
Finished Jul 18 05:15:13 PM PDT 24
Peak memory 208400 kb
Host smart-d4e548f6-714d-4127-bf7b-421186890c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969408388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1969408388
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3589750750
Short name T374
Test name
Test status
Simulation time 221220411 ps
CPU time 9.8 seconds
Started Jul 18 05:15:07 PM PDT 24
Finished Jul 18 05:15:18 PM PDT 24
Peak memory 225568 kb
Host smart-68fbcff1-f35d-4e95-a02b-eb29ed0e7cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589750750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3589750750
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1648312303
Short name T846
Test name
Test status
Simulation time 232693294 ps
CPU time 2.8 seconds
Started Jul 18 05:15:13 PM PDT 24
Finished Jul 18 05:15:19 PM PDT 24
Peak memory 216684 kb
Host smart-e8299b07-fd00-461f-abf3-79cdd5284956
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648312303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1648312303
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.4226600634
Short name T460
Test name
Test status
Simulation time 413497796 ps
CPU time 4.58 seconds
Started Jul 18 05:15:14 PM PDT 24
Finished Jul 18 05:15:22 PM PDT 24
Peak memory 217324 kb
Host smart-ef6fe34e-7c3b-4660-9c24-6b841c0555ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226600634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.4226600634
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3515291957
Short name T466
Test name
Test status
Simulation time 3071771173 ps
CPU time 11.14 seconds
Started Jul 18 05:15:09 PM PDT 24
Finished Jul 18 05:15:21 PM PDT 24
Peak memory 218504 kb
Host smart-2568efcd-ba0e-417d-928c-959f6385c461
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515291957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3515291957
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3889915737
Short name T585
Test name
Test status
Simulation time 290065661 ps
CPU time 9.9 seconds
Started Jul 18 05:15:10 PM PDT 24
Finished Jul 18 05:15:21 PM PDT 24
Peak memory 217784 kb
Host smart-ba5e8b8c-9b3a-4980-ae6f-a848fc766a32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889915737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3889915737
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1491734818
Short name T633
Test name
Test status
Simulation time 2187193796 ps
CPU time 10.91 seconds
Started Jul 18 05:15:07 PM PDT 24
Finished Jul 18 05:15:19 PM PDT 24
Peak memory 225524 kb
Host smart-cbe45d1f-5d64-42c3-b79d-2e0fe5e21255
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491734818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1491734818
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3079895291
Short name T752
Test name
Test status
Simulation time 1850252287 ps
CPU time 17.43 seconds
Started Jul 18 05:15:08 PM PDT 24
Finished Jul 18 05:15:27 PM PDT 24
Peak memory 217828 kb
Host smart-9f216996-fec1-4fb1-b843-38a28ecfc1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079895291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3079895291
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1581312993
Short name T275
Test name
Test status
Simulation time 103368408 ps
CPU time 3.14 seconds
Started Jul 18 05:15:13 PM PDT 24
Finished Jul 18 05:15:19 PM PDT 24
Peak memory 214572 kb
Host smart-8b64bf88-fecf-4432-bdb4-fdb0d52d203a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581312993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1581312993
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.4009724296
Short name T265
Test name
Test status
Simulation time 504112586 ps
CPU time 28.81 seconds
Started Jul 18 05:15:12 PM PDT 24
Finished Jul 18 05:15:43 PM PDT 24
Peak memory 250516 kb
Host smart-bae6187e-073b-4ea8-99b0-d4861cfa94da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009724296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.4009724296
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.62431553
Short name T231
Test name
Test status
Simulation time 175278049 ps
CPU time 6.25 seconds
Started Jul 18 05:15:08 PM PDT 24
Finished Jul 18 05:15:16 PM PDT 24
Peak memory 242860 kb
Host smart-7d43e0e4-3e3a-4343-913e-11b7306c5df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62431553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.62431553
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3477210870
Short name T162
Test name
Test status
Simulation time 7189019615 ps
CPU time 78.82 seconds
Started Jul 18 05:15:06 PM PDT 24
Finished Jul 18 05:16:26 PM PDT 24
Peak memory 274752 kb
Host smart-38ba8326-4a6e-4756-a689-c0a4ed4861fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477210870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3477210870
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.4139970657
Short name T283
Test name
Test status
Simulation time 34380637 ps
CPU time 1.13 seconds
Started Jul 18 05:15:07 PM PDT 24
Finished Jul 18 05:15:10 PM PDT 24
Peak memory 211424 kb
Host smart-7fa5762a-98a5-4154-b76c-6ae0f07e66e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139970657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.4139970657
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1019887511
Short name T658
Test name
Test status
Simulation time 129306915 ps
CPU time 0.99 seconds
Started Jul 18 05:15:12 PM PDT 24
Finished Jul 18 05:15:15 PM PDT 24
Peak memory 208632 kb
Host smart-c4f07698-f610-4ab0-bd8d-9a5dc9d0a740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019887511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1019887511
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.845941802
Short name T459
Test name
Test status
Simulation time 916488429 ps
CPU time 9.67 seconds
Started Jul 18 05:15:10 PM PDT 24
Finished Jul 18 05:15:22 PM PDT 24
Peak memory 217836 kb
Host smart-d430fe74-88fd-4ce3-9c1b-2f2b4596cef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845941802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.845941802
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2502864826
Short name T760
Test name
Test status
Simulation time 1218690123 ps
CPU time 15.03 seconds
Started Jul 18 05:15:07 PM PDT 24
Finished Jul 18 05:15:23 PM PDT 24
Peak memory 216832 kb
Host smart-43dacf26-dbc0-446c-99f8-4188f4910bf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502864826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2502864826
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2945695236
Short name T548
Test name
Test status
Simulation time 384589127 ps
CPU time 3.98 seconds
Started Jul 18 05:15:15 PM PDT 24
Finished Jul 18 05:15:23 PM PDT 24
Peak memory 222420 kb
Host smart-40597d4e-1fe8-4306-bd0d-7bde7c28f953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945695236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2945695236
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3601258241
Short name T780
Test name
Test status
Simulation time 1585743873 ps
CPU time 16.82 seconds
Started Jul 18 05:15:08 PM PDT 24
Finished Jul 18 05:15:27 PM PDT 24
Peak memory 217840 kb
Host smart-acfe4b38-c1d4-4ef5-b590-023ed28df63b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601258241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3601258241
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3669069037
Short name T239
Test name
Test status
Simulation time 217174360 ps
CPU time 9.23 seconds
Started Jul 18 05:15:08 PM PDT 24
Finished Jul 18 05:15:18 PM PDT 24
Peak memory 225596 kb
Host smart-ec8bb30a-caa7-4784-af82-4d515750dc5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669069037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3669069037
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.413654025
Short name T587
Test name
Test status
Simulation time 1025023368 ps
CPU time 11.03 seconds
Started Jul 18 05:15:10 PM PDT 24
Finished Jul 18 05:15:24 PM PDT 24
Peak memory 217872 kb
Host smart-eee820a9-e246-4f06-8a93-92e884a5ce11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413654025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.413654025
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2584818666
Short name T343
Test name
Test status
Simulation time 51371964 ps
CPU time 1.23 seconds
Started Jul 18 05:15:10 PM PDT 24
Finished Jul 18 05:15:13 PM PDT 24
Peak memory 217208 kb
Host smart-9577dbac-8abb-484c-bc43-5a5fefee8552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584818666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2584818666
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2572746770
Short name T722
Test name
Test status
Simulation time 808755196 ps
CPU time 24.55 seconds
Started Jul 18 05:15:10 PM PDT 24
Finished Jul 18 05:15:37 PM PDT 24
Peak memory 250512 kb
Host smart-bd359b73-730d-4d24-9e82-2744819c8a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572746770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2572746770
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3574311086
Short name T806
Test name
Test status
Simulation time 146446904 ps
CPU time 6.78 seconds
Started Jul 18 05:15:06 PM PDT 24
Finished Jul 18 05:15:14 PM PDT 24
Peak memory 246832 kb
Host smart-1ca4ca2a-b005-4b4c-8757-1f0417ba5a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574311086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3574311086
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3685165341
Short name T488
Test name
Test status
Simulation time 1512724792 ps
CPU time 31.17 seconds
Started Jul 18 05:15:12 PM PDT 24
Finished Jul 18 05:15:46 PM PDT 24
Peak memory 225524 kb
Host smart-345f082f-cc24-4290-8578-4f12e457eab7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685165341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3685165341
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3106121607
Short name T809
Test name
Test status
Simulation time 17147861 ps
CPU time 0.96 seconds
Started Jul 18 05:15:10 PM PDT 24
Finished Jul 18 05:15:13 PM PDT 24
Peak memory 208396 kb
Host smart-34677593-c8a6-476f-92c9-45be1f78bdcc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106121607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3106121607
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.4062223967
Short name T440
Test name
Test status
Simulation time 21913126 ps
CPU time 0.97 seconds
Started Jul 18 05:15:11 PM PDT 24
Finished Jul 18 05:15:14 PM PDT 24
Peak memory 208588 kb
Host smart-a6bef1fe-6421-4008-ac63-f6c0b57b6b6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062223967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.4062223967
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3522781350
Short name T738
Test name
Test status
Simulation time 481795132 ps
CPU time 11.24 seconds
Started Jul 18 05:15:09 PM PDT 24
Finished Jul 18 05:15:22 PM PDT 24
Peak memory 217780 kb
Host smart-fa9529d6-0274-48f8-91a2-f65cad2bdf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522781350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3522781350
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.535995525
Short name T604
Test name
Test status
Simulation time 333960170 ps
CPU time 10.01 seconds
Started Jul 18 05:15:09 PM PDT 24
Finished Jul 18 05:15:21 PM PDT 24
Peak memory 216872 kb
Host smart-a158fcaa-2596-476b-8e64-df3b36c283a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535995525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.535995525
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.690156979
Short name T505
Test name
Test status
Simulation time 728213423 ps
CPU time 4.07 seconds
Started Jul 18 05:15:11 PM PDT 24
Finished Jul 18 05:15:18 PM PDT 24
Peak memory 217736 kb
Host smart-48a1d5a0-fd24-4d0f-9bca-e10f2aeb90ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690156979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.690156979
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.943786209
Short name T847
Test name
Test status
Simulation time 1353881882 ps
CPU time 13.77 seconds
Started Jul 18 05:15:14 PM PDT 24
Finished Jul 18 05:15:31 PM PDT 24
Peak memory 218016 kb
Host smart-bf1a8a7f-fe4c-46c6-8406-686212ae0a91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943786209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.943786209
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3478092198
Short name T731
Test name
Test status
Simulation time 980933354 ps
CPU time 8.66 seconds
Started Jul 18 05:15:07 PM PDT 24
Finished Jul 18 05:15:17 PM PDT 24
Peak memory 217764 kb
Host smart-621b3a55-f463-4392-bf0f-406ab86f464b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478092198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3478092198
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.808304012
Short name T64
Test name
Test status
Simulation time 1111450858 ps
CPU time 10.42 seconds
Started Jul 18 05:15:12 PM PDT 24
Finished Jul 18 05:15:25 PM PDT 24
Peak memory 217996 kb
Host smart-ebffa6c1-dfe7-4883-bad7-4add4a310a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808304012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.808304012
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1349556248
Short name T551
Test name
Test status
Simulation time 23108616 ps
CPU time 1.62 seconds
Started Jul 18 05:15:08 PM PDT 24
Finished Jul 18 05:15:11 PM PDT 24
Peak memory 213296 kb
Host smart-160821a7-b9c3-48bc-88aa-cc62c18a93cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349556248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1349556248
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.108778324
Short name T384
Test name
Test status
Simulation time 219142003 ps
CPU time 25.16 seconds
Started Jul 18 05:15:08 PM PDT 24
Finished Jul 18 05:15:35 PM PDT 24
Peak memory 250512 kb
Host smart-63bf982a-cf06-4a96-adc3-1bd4a4f79785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108778324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.108778324
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3468410920
Short name T567
Test name
Test status
Simulation time 98225768 ps
CPU time 3.35 seconds
Started Jul 18 05:15:11 PM PDT 24
Finished Jul 18 05:15:17 PM PDT 24
Peak memory 217764 kb
Host smart-6eed7c5f-73da-4085-b87b-17a24e837363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468410920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3468410920
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3643920644
Short name T360
Test name
Test status
Simulation time 627194161 ps
CPU time 23.98 seconds
Started Jul 18 05:15:08 PM PDT 24
Finished Jul 18 05:15:34 PM PDT 24
Peak memory 225568 kb
Host smart-196db214-7352-4abf-b018-1c24c3613c13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643920644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3643920644
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.246967710
Short name T596
Test name
Test status
Simulation time 48106650 ps
CPU time 0.95 seconds
Started Jul 18 05:15:10 PM PDT 24
Finished Jul 18 05:15:13 PM PDT 24
Peak memory 211392 kb
Host smart-ff11d48b-adb1-4d02-8ffd-ba2eb30034d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246967710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.246967710
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.902721974
Short name T638
Test name
Test status
Simulation time 55674646 ps
CPU time 1.04 seconds
Started Jul 18 05:13:08 PM PDT 24
Finished Jul 18 05:13:12 PM PDT 24
Peak memory 208440 kb
Host smart-9901e571-c450-4261-ae40-19a1843044e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902721974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.902721974
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2472247347
Short name T269
Test name
Test status
Simulation time 17219417 ps
CPU time 0.85 seconds
Started Jul 18 05:13:07 PM PDT 24
Finished Jul 18 05:13:11 PM PDT 24
Peak memory 208048 kb
Host smart-3e785aee-1f16-4c7c-a77d-08416990b4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472247347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2472247347
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3056269085
Short name T53
Test name
Test status
Simulation time 531497389 ps
CPU time 12.47 seconds
Started Jul 18 05:13:06 PM PDT 24
Finished Jul 18 05:13:22 PM PDT 24
Peak memory 217776 kb
Host smart-7c828457-911b-4599-9f9b-8f7c3f608534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056269085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3056269085
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1946769974
Short name T544
Test name
Test status
Simulation time 706949609 ps
CPU time 18.5 seconds
Started Jul 18 05:13:05 PM PDT 24
Finished Jul 18 05:13:26 PM PDT 24
Peak memory 216916 kb
Host smart-ad669dca-ec2f-4be1-bdd6-1d6854e55d55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946769974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1946769974
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3175457854
Short name T557
Test name
Test status
Simulation time 3877116153 ps
CPU time 59.11 seconds
Started Jul 18 05:13:07 PM PDT 24
Finished Jul 18 05:14:09 PM PDT 24
Peak memory 218280 kb
Host smart-d0651aef-2fa1-45c9-ab00-b668641558ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175457854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3175457854
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2934044456
Short name T75
Test name
Test status
Simulation time 2688964717 ps
CPU time 4.98 seconds
Started Jul 18 05:13:03 PM PDT 24
Finished Jul 18 05:13:09 PM PDT 24
Peak memory 217304 kb
Host smart-e2f1c815-df3a-49fa-96cf-a7f1da456a9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934044456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
934044456
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1440673373
Short name T662
Test name
Test status
Simulation time 91283713 ps
CPU time 2.57 seconds
Started Jul 18 05:13:00 PM PDT 24
Finished Jul 18 05:13:04 PM PDT 24
Peak memory 221384 kb
Host smart-da37ea6c-187a-4105-b910-c0c9063862f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440673373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1440673373
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3966635906
Short name T86
Test name
Test status
Simulation time 957006672 ps
CPU time 26.02 seconds
Started Jul 18 05:13:03 PM PDT 24
Finished Jul 18 05:13:30 PM PDT 24
Peak memory 217084 kb
Host smart-fb99124f-037e-4a57-9e1a-df8940189f3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966635906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3966635906
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1187992924
Short name T804
Test name
Test status
Simulation time 478818452 ps
CPU time 2.42 seconds
Started Jul 18 05:13:07 PM PDT 24
Finished Jul 18 05:13:14 PM PDT 24
Peak memory 217108 kb
Host smart-297bea3d-3349-40a8-ae20-3bc5994e4971
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187992924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1187992924
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.193259318
Short name T764
Test name
Test status
Simulation time 13950860684 ps
CPU time 103.77 seconds
Started Jul 18 05:13:06 PM PDT 24
Finished Jul 18 05:14:53 PM PDT 24
Peak memory 283236 kb
Host smart-696d9856-f0b3-481b-b639-ef12b86944fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193259318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.193259318
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.4256350179
Short name T245
Test name
Test status
Simulation time 628261461 ps
CPU time 15.43 seconds
Started Jul 18 05:13:04 PM PDT 24
Finished Jul 18 05:13:21 PM PDT 24
Peak memory 250180 kb
Host smart-33a47a9b-68ab-4c53-8459-f040354ba653
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256350179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.4256350179
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3363765858
Short name T499
Test name
Test status
Simulation time 26953458 ps
CPU time 2.08 seconds
Started Jul 18 05:13:05 PM PDT 24
Finished Jul 18 05:13:10 PM PDT 24
Peak memory 221628 kb
Host smart-c526b116-8193-4802-8a8c-47fc5d2eab09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363765858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3363765858
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.774124590
Short name T204
Test name
Test status
Simulation time 696460752 ps
CPU time 8.22 seconds
Started Jul 18 05:13:06 PM PDT 24
Finished Jul 18 05:13:17 PM PDT 24
Peak memory 217200 kb
Host smart-280e252a-f249-4f55-bcc3-ca8fcb06dad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774124590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.774124590
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2562023946
Short name T66
Test name
Test status
Simulation time 234262550 ps
CPU time 38.38 seconds
Started Jul 18 05:13:10 PM PDT 24
Finished Jul 18 05:13:52 PM PDT 24
Peak memory 282612 kb
Host smart-860a10a6-0396-49eb-8143-fe23960253cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562023946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2562023946
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2451710510
Short name T168
Test name
Test status
Simulation time 2507777566 ps
CPU time 16.53 seconds
Started Jul 18 05:13:11 PM PDT 24
Finished Jul 18 05:13:32 PM PDT 24
Peak memory 218708 kb
Host smart-ece5f575-a231-4ffb-990d-6d7125335dff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451710510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2451710510
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2544795895
Short name T334
Test name
Test status
Simulation time 228025777 ps
CPU time 7.87 seconds
Started Jul 18 05:13:05 PM PDT 24
Finished Jul 18 05:13:16 PM PDT 24
Peak memory 217772 kb
Host smart-5be58364-e65c-4cab-9dd9-09004e627c5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544795895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2544795895
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1869791488
Short name T831
Test name
Test status
Simulation time 4091132739 ps
CPU time 10.06 seconds
Started Jul 18 05:13:08 PM PDT 24
Finished Jul 18 05:13:21 PM PDT 24
Peak memory 225588 kb
Host smart-bd5f25b1-68f1-4f05-a11c-b8b706f6af78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869791488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
869791488
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.233363989
Short name T436
Test name
Test status
Simulation time 1114043880 ps
CPU time 9.4 seconds
Started Jul 18 05:13:05 PM PDT 24
Finished Jul 18 05:13:15 PM PDT 24
Peak memory 217812 kb
Host smart-c0bca357-40e7-4c69-8edb-793e45c81596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233363989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.233363989
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1503456609
Short name T87
Test name
Test status
Simulation time 107022541 ps
CPU time 4.06 seconds
Started Jul 18 05:13:04 PM PDT 24
Finished Jul 18 05:13:10 PM PDT 24
Peak memory 217192 kb
Host smart-d2edb544-ff79-40e2-b792-e0cc2519f6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503456609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1503456609
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2703120349
Short name T792
Test name
Test status
Simulation time 177159306 ps
CPU time 23.35 seconds
Started Jul 18 05:13:05 PM PDT 24
Finished Jul 18 05:13:31 PM PDT 24
Peak memory 250504 kb
Host smart-aaf38727-d19f-414e-b532-9c771edf8b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703120349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2703120349
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3852173210
Short name T607
Test name
Test status
Simulation time 88891372 ps
CPU time 3.4 seconds
Started Jul 18 05:13:08 PM PDT 24
Finished Jul 18 05:13:15 PM PDT 24
Peak memory 222080 kb
Host smart-128ab99b-be16-4f14-9573-f76d3687b26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852173210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3852173210
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3177589502
Short name T410
Test name
Test status
Simulation time 26484990529 ps
CPU time 207.46 seconds
Started Jul 18 05:13:06 PM PDT 24
Finished Jul 18 05:16:37 PM PDT 24
Peak memory 316072 kb
Host smart-afc21afa-bad5-4e02-b1b2-82566b1c7943
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177589502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3177589502
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.2713513358
Short name T145
Test name
Test status
Simulation time 147628223200 ps
CPU time 693.62 seconds
Started Jul 18 05:13:14 PM PDT 24
Finished Jul 18 05:24:50 PM PDT 24
Peak memory 512880 kb
Host smart-e3c5c566-f43a-49be-983a-ff48fdf638ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2713513358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.2713513358
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2807999825
Short name T164
Test name
Test status
Simulation time 19648229 ps
CPU time 0.8 seconds
Started Jul 18 05:13:03 PM PDT 24
Finished Jul 18 05:13:05 PM PDT 24
Peak memory 208228 kb
Host smart-450fce92-a40e-4d48-9a89-15190037e513
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807999825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2807999825
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.620363593
Short name T849
Test name
Test status
Simulation time 62060493 ps
CPU time 0.83 seconds
Started Jul 18 05:15:15 PM PDT 24
Finished Jul 18 05:15:19 PM PDT 24
Peak memory 208588 kb
Host smart-a04d3b78-f4ee-458b-b0d6-56c1473b6b46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620363593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.620363593
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.227035730
Short name T425
Test name
Test status
Simulation time 1247500797 ps
CPU time 13.02 seconds
Started Jul 18 05:15:14 PM PDT 24
Finished Jul 18 05:15:30 PM PDT 24
Peak memory 217676 kb
Host smart-e664d01a-059d-47e6-8dd3-2afd1f9d848a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227035730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.227035730
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3014811329
Short name T454
Test name
Test status
Simulation time 86320487 ps
CPU time 1.59 seconds
Started Jul 18 05:15:14 PM PDT 24
Finished Jul 18 05:15:19 PM PDT 24
Peak memory 216532 kb
Host smart-5e80dd8c-dfc5-4b58-8d32-9ffe8b0cc32d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014811329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3014811329
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3294090573
Short name T799
Test name
Test status
Simulation time 53461988 ps
CPU time 3.07 seconds
Started Jul 18 05:15:07 PM PDT 24
Finished Jul 18 05:15:11 PM PDT 24
Peak memory 217772 kb
Host smart-12356f19-3391-4f5f-b309-e9ed39098ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294090573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3294090573
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1739423362
Short name T472
Test name
Test status
Simulation time 225811584 ps
CPU time 11.07 seconds
Started Jul 18 05:15:16 PM PDT 24
Finished Jul 18 05:15:31 PM PDT 24
Peak memory 218412 kb
Host smart-a6406c98-9685-4c40-9c0a-1c448932165b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739423362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1739423362
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2398777998
Short name T40
Test name
Test status
Simulation time 1344213285 ps
CPU time 9.95 seconds
Started Jul 18 05:15:14 PM PDT 24
Finished Jul 18 05:15:28 PM PDT 24
Peak memory 217780 kb
Host smart-1fd98c18-a3e8-43e2-ace8-9e5872199a9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398777998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2398777998
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2004218477
Short name T391
Test name
Test status
Simulation time 1921843702 ps
CPU time 9.25 seconds
Started Jul 18 05:15:19 PM PDT 24
Finished Jul 18 05:15:31 PM PDT 24
Peak memory 225528 kb
Host smart-e5d7ed80-f00a-437c-8845-73c2355f5976
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004218477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2004218477
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3790965574
Short name T208
Test name
Test status
Simulation time 500450378 ps
CPU time 11.13 seconds
Started Jul 18 05:15:17 PM PDT 24
Finished Jul 18 05:15:32 PM PDT 24
Peak memory 217868 kb
Host smart-dd84bb05-5f03-43b0-8f18-ba1a48c7251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790965574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3790965574
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2909702392
Short name T600
Test name
Test status
Simulation time 39246302 ps
CPU time 2.07 seconds
Started Jul 18 05:15:06 PM PDT 24
Finished Jul 18 05:15:09 PM PDT 24
Peak memory 217192 kb
Host smart-7dadc593-a510-4642-b655-51be38e9e4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909702392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2909702392
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.990299355
Short name T152
Test name
Test status
Simulation time 2336100730 ps
CPU time 24.92 seconds
Started Jul 18 05:15:13 PM PDT 24
Finished Jul 18 05:15:42 PM PDT 24
Peak memory 250580 kb
Host smart-85efddff-5773-4ce0-972c-9228265f284d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990299355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.990299355
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2763256518
Short name T323
Test name
Test status
Simulation time 367265052 ps
CPU time 3.88 seconds
Started Jul 18 05:15:13 PM PDT 24
Finished Jul 18 05:15:20 PM PDT 24
Peak memory 225928 kb
Host smart-5bc7261e-f207-4a1d-8470-d2c47be55889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763256518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2763256518
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2057431405
Short name T726
Test name
Test status
Simulation time 1410418306 ps
CPU time 30.04 seconds
Started Jul 18 05:15:14 PM PDT 24
Finished Jul 18 05:15:48 PM PDT 24
Peak memory 250212 kb
Host smart-eb5dc78f-3619-4ad6-a034-a5e19bce72ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057431405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2057431405
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.259812055
Short name T82
Test name
Test status
Simulation time 20616160 ps
CPU time 1.29 seconds
Started Jul 18 05:15:12 PM PDT 24
Finished Jul 18 05:15:16 PM PDT 24
Peak memory 212404 kb
Host smart-8bf6cadc-6397-41ef-be0b-825d6b39905d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259812055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.259812055
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.4154893991
Short name T681
Test name
Test status
Simulation time 305643022 ps
CPU time 0.97 seconds
Started Jul 18 05:15:20 PM PDT 24
Finished Jul 18 05:15:23 PM PDT 24
Peak memory 208484 kb
Host smart-c62ce679-eceb-4d3c-ad77-e423b198898d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154893991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.4154893991
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3385700531
Short name T179
Test name
Test status
Simulation time 759005080 ps
CPU time 8.25 seconds
Started Jul 18 05:15:17 PM PDT 24
Finished Jul 18 05:15:29 PM PDT 24
Peak memory 217780 kb
Host smart-7b3d6bd1-393c-419d-bee7-6c30d0bcd762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385700531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3385700531
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2640121414
Short name T33
Test name
Test status
Simulation time 2845919614 ps
CPU time 7.61 seconds
Started Jul 18 05:15:17 PM PDT 24
Finished Jul 18 05:15:28 PM PDT 24
Peak memory 217036 kb
Host smart-ce434aea-64d4-433c-be52-0802d35bfc6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640121414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2640121414
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1311943348
Short name T751
Test name
Test status
Simulation time 16152530 ps
CPU time 1.63 seconds
Started Jul 18 05:15:12 PM PDT 24
Finished Jul 18 05:15:17 PM PDT 24
Peak memory 217796 kb
Host smart-1ac05539-1712-41f0-a7c8-0095ae52039d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311943348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1311943348
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2150701081
Short name T220
Test name
Test status
Simulation time 188514029 ps
CPU time 10.16 seconds
Started Jul 18 05:15:09 PM PDT 24
Finished Jul 18 05:15:21 PM PDT 24
Peak memory 217920 kb
Host smart-19b9cfff-a7c8-4424-9db4-0f7bfd6ddfae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150701081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2150701081
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.140064548
Short name T451
Test name
Test status
Simulation time 557068297 ps
CPU time 14.62 seconds
Started Jul 18 05:15:16 PM PDT 24
Finished Jul 18 05:15:35 PM PDT 24
Peak memory 217684 kb
Host smart-174a58b8-86fb-4ebb-998d-cfe857b3616b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140064548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.140064548
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2042645437
Short name T754
Test name
Test status
Simulation time 1724401888 ps
CPU time 8.71 seconds
Started Jul 18 05:15:08 PM PDT 24
Finished Jul 18 05:15:19 PM PDT 24
Peak memory 225500 kb
Host smart-3df62d86-4933-44cf-b690-16efa48293be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042645437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2042645437
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.373985447
Short name T535
Test name
Test status
Simulation time 1433814896 ps
CPU time 6.41 seconds
Started Jul 18 05:15:15 PM PDT 24
Finished Jul 18 05:15:25 PM PDT 24
Peak memory 217844 kb
Host smart-2fbe7a4a-6196-4561-800c-dbadbbb8c7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373985447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.373985447
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3947692855
Short name T851
Test name
Test status
Simulation time 755545369 ps
CPU time 3.25 seconds
Started Jul 18 05:15:13 PM PDT 24
Finished Jul 18 05:15:19 PM PDT 24
Peak memory 217468 kb
Host smart-ddb0aeeb-e0e5-47aa-9115-cfa63f2d2992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947692855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3947692855
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.103501442
Short name T758
Test name
Test status
Simulation time 468273380 ps
CPU time 23.11 seconds
Started Jul 18 05:15:13 PM PDT 24
Finished Jul 18 05:15:39 PM PDT 24
Peak memory 250540 kb
Host smart-7c04bc01-3fd1-4a05-b9c5-4d63113a15b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103501442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.103501442
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1319348088
Short name T615
Test name
Test status
Simulation time 258372059 ps
CPU time 3.02 seconds
Started Jul 18 05:15:12 PM PDT 24
Finished Jul 18 05:15:18 PM PDT 24
Peak memory 221916 kb
Host smart-9ccd3a4f-9659-4d6b-8625-3a87d9e74c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319348088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1319348088
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.85666040
Short name T83
Test name
Test status
Simulation time 16805864013 ps
CPU time 32.61 seconds
Started Jul 18 05:15:10 PM PDT 24
Finished Jul 18 05:15:44 PM PDT 24
Peak memory 250336 kb
Host smart-ff5a109b-2ceb-43a8-a2ee-5efc15d4ac91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85666040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.lc_ctrl_stress_all.85666040
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.556154231
Short name T143
Test name
Test status
Simulation time 23075354620 ps
CPU time 185.13 seconds
Started Jul 18 05:15:13 PM PDT 24
Finished Jul 18 05:18:22 PM PDT 24
Peak memory 270412 kb
Host smart-19c5d6a1-afa0-4667-bb65-09884d0ba71e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=556154231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.556154231
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2140089749
Short name T477
Test name
Test status
Simulation time 44507982 ps
CPU time 0.82 seconds
Started Jul 18 05:15:16 PM PDT 24
Finished Jul 18 05:15:20 PM PDT 24
Peak memory 208352 kb
Host smart-391d284a-25e3-4acb-a52b-c7fcca282a92
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140089749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2140089749
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2082547744
Short name T251
Test name
Test status
Simulation time 29526512 ps
CPU time 0.92 seconds
Started Jul 18 05:15:12 PM PDT 24
Finished Jul 18 05:15:16 PM PDT 24
Peak memory 208644 kb
Host smart-b4c5908d-851e-4c9b-8f04-6c9ee2563756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082547744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2082547744
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2331400283
Short name T735
Test name
Test status
Simulation time 487713773 ps
CPU time 13.91 seconds
Started Jul 18 05:15:15 PM PDT 24
Finished Jul 18 05:15:33 PM PDT 24
Peak memory 217804 kb
Host smart-40c7e995-8274-4c3a-abf5-1ebb61dbd08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331400283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2331400283
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2727863653
Short name T716
Test name
Test status
Simulation time 2499096334 ps
CPU time 12.55 seconds
Started Jul 18 05:15:18 PM PDT 24
Finished Jul 18 05:15:34 PM PDT 24
Peak memory 217060 kb
Host smart-a6e05b4a-ca97-40a5-a299-bdf26404af2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727863653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2727863653
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3037573031
Short name T635
Test name
Test status
Simulation time 135828578 ps
CPU time 3.63 seconds
Started Jul 18 05:15:15 PM PDT 24
Finished Jul 18 05:15:22 PM PDT 24
Peak memory 222232 kb
Host smart-7bac22ce-d8cd-4a6f-9d19-3b98e7166627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037573031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3037573031
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.122423551
Short name T671
Test name
Test status
Simulation time 182842952 ps
CPU time 9.29 seconds
Started Jul 18 05:15:14 PM PDT 24
Finished Jul 18 05:15:26 PM PDT 24
Peak memory 217740 kb
Host smart-c547a36a-4d8a-4120-9243-4642f1953fb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122423551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.122423551
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1489896479
Short name T797
Test name
Test status
Simulation time 3832368151 ps
CPU time 9.42 seconds
Started Jul 18 05:15:17 PM PDT 24
Finished Jul 18 05:15:30 PM PDT 24
Peak memory 225592 kb
Host smart-3cae20ef-07dc-4a1b-b3b3-d4169031a484
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489896479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1489896479
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2132306257
Short name T643
Test name
Test status
Simulation time 466991301 ps
CPU time 6.41 seconds
Started Jul 18 05:15:12 PM PDT 24
Finished Jul 18 05:15:21 PM PDT 24
Peak memory 217996 kb
Host smart-526c6514-417e-45b1-ac59-0f829f96667b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132306257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2132306257
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2457362089
Short name T39
Test name
Test status
Simulation time 359393529 ps
CPU time 2.99 seconds
Started Jul 18 05:15:10 PM PDT 24
Finished Jul 18 05:15:15 PM PDT 24
Peak memory 214128 kb
Host smart-d4a69cfc-c126-49b4-9ae2-543c35a036c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457362089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2457362089
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2742247718
Short name T576
Test name
Test status
Simulation time 432639799 ps
CPU time 25.39 seconds
Started Jul 18 05:15:12 PM PDT 24
Finished Jul 18 05:15:40 PM PDT 24
Peak memory 250512 kb
Host smart-6d761cbb-c0be-4ff4-9fda-de44173579bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742247718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2742247718
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1434000556
Short name T297
Test name
Test status
Simulation time 73025045 ps
CPU time 11.47 seconds
Started Jul 18 05:15:15 PM PDT 24
Finished Jul 18 05:15:30 PM PDT 24
Peak memory 250488 kb
Host smart-5925d093-c4e1-4dc6-8fc6-626d7715aa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434000556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1434000556
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.4008823609
Short name T480
Test name
Test status
Simulation time 11829214278 ps
CPU time 175.1 seconds
Started Jul 18 05:15:14 PM PDT 24
Finished Jul 18 05:18:13 PM PDT 24
Peak memory 281320 kb
Host smart-b90bcf1f-c23f-4149-a81d-b6c7d9fe91ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008823609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.4008823609
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1575178719
Short name T476
Test name
Test status
Simulation time 37529379 ps
CPU time 0.95 seconds
Started Jul 18 05:15:08 PM PDT 24
Finished Jul 18 05:15:10 PM PDT 24
Peak memory 208404 kb
Host smart-959f3ca4-ca90-4efe-9941-6a3029285c9c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575178719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1575178719
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3829978033
Short name T324
Test name
Test status
Simulation time 56463385 ps
CPU time 0.89 seconds
Started Jul 18 05:15:25 PM PDT 24
Finished Jul 18 05:15:27 PM PDT 24
Peak memory 208332 kb
Host smart-73c2ccba-aa1a-4b5b-8974-117a8047ef2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829978033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3829978033
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3868451206
Short name T696
Test name
Test status
Simulation time 2110145428 ps
CPU time 14.19 seconds
Started Jul 18 05:15:32 PM PDT 24
Finished Jul 18 05:15:48 PM PDT 24
Peak memory 217780 kb
Host smart-b198369d-55df-4b66-bff7-2225233f9033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868451206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3868451206
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2814405898
Short name T565
Test name
Test status
Simulation time 368460002 ps
CPU time 4.9 seconds
Started Jul 18 05:15:29 PM PDT 24
Finished Jul 18 05:15:35 PM PDT 24
Peak memory 216748 kb
Host smart-371edb47-01c1-4d1a-9ab4-c54c7325b6ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814405898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2814405898
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1038915277
Short name T601
Test name
Test status
Simulation time 55862313 ps
CPU time 2.02 seconds
Started Jul 18 05:15:36 PM PDT 24
Finished Jul 18 05:15:40 PM PDT 24
Peak memory 217732 kb
Host smart-ec661076-ab72-4022-a207-0b508d204d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038915277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1038915277
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1138132460
Short name T790
Test name
Test status
Simulation time 1407793065 ps
CPU time 14.55 seconds
Started Jul 18 05:15:25 PM PDT 24
Finished Jul 18 05:15:42 PM PDT 24
Peak memory 217928 kb
Host smart-9ff1d21a-f218-4fac-925d-001305994a17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138132460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1138132460
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.70830866
Short name T159
Test name
Test status
Simulation time 845826574 ps
CPU time 10.5 seconds
Started Jul 18 05:15:37 PM PDT 24
Finished Jul 18 05:15:49 PM PDT 24
Peak memory 225488 kb
Host smart-257bb170-1d12-4f50-aae2-265bdbc03b82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70830866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_dig
est.70830866
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2001538051
Short name T529
Test name
Test status
Simulation time 1242431839 ps
CPU time 8.87 seconds
Started Jul 18 05:15:25 PM PDT 24
Finished Jul 18 05:15:35 PM PDT 24
Peak memory 225480 kb
Host smart-27928988-9981-4e61-90ed-bcd52c20b395
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001538051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2001538051
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3930588743
Short name T700
Test name
Test status
Simulation time 1233967285 ps
CPU time 11.02 seconds
Started Jul 18 05:15:32 PM PDT 24
Finished Jul 18 05:15:44 PM PDT 24
Peak memory 217840 kb
Host smart-561c2486-1a72-40a7-b0fa-ec5082e46266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930588743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3930588743
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.211427449
Short name T469
Test name
Test status
Simulation time 780258951 ps
CPU time 6.17 seconds
Started Jul 18 05:15:14 PM PDT 24
Finished Jul 18 05:15:24 PM PDT 24
Peak memory 217184 kb
Host smart-e7bd6c3d-67db-4c46-aad0-9cf32ea81600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211427449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.211427449
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1588915844
Short name T455
Test name
Test status
Simulation time 1175186845 ps
CPU time 26.22 seconds
Started Jul 18 05:15:26 PM PDT 24
Finished Jul 18 05:15:54 PM PDT 24
Peak memory 250532 kb
Host smart-9008e784-4da9-4a46-b91f-234d61c0fd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588915844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1588915844
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3527298234
Short name T644
Test name
Test status
Simulation time 194619705 ps
CPU time 6.65 seconds
Started Jul 18 05:15:27 PM PDT 24
Finished Jul 18 05:15:35 PM PDT 24
Peak memory 250508 kb
Host smart-b63b4816-5856-432a-9777-755617fa51bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527298234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3527298234
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3255359182
Short name T432
Test name
Test status
Simulation time 20579527900 ps
CPU time 369.08 seconds
Started Jul 18 05:15:28 PM PDT 24
Finished Jul 18 05:21:38 PM PDT 24
Peak memory 266968 kb
Host smart-b3e9c1a8-6bcf-4040-84a5-e974155acecd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255359182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3255359182
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1710849748
Short name T292
Test name
Test status
Simulation time 36021039 ps
CPU time 0.86 seconds
Started Jul 18 05:15:17 PM PDT 24
Finished Jul 18 05:15:21 PM PDT 24
Peak memory 208408 kb
Host smart-628eb817-187c-4450-be79-fcdf2cd73458
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710849748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1710849748
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1493403969
Short name T385
Test name
Test status
Simulation time 109851350 ps
CPU time 0.99 seconds
Started Jul 18 05:15:29 PM PDT 24
Finished Jul 18 05:15:31 PM PDT 24
Peak memory 208328 kb
Host smart-0e4b8c08-c80b-4709-92cf-3c7cdb9a6e71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493403969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1493403969
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.3858252993
Short name T299
Test name
Test status
Simulation time 309323067 ps
CPU time 8.89 seconds
Started Jul 18 05:15:28 PM PDT 24
Finished Jul 18 05:15:38 PM PDT 24
Peak memory 217752 kb
Host smart-2f8f869f-f3bc-4486-9a99-b1749afc105f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858252993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3858252993
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.946212002
Short name T32
Test name
Test status
Simulation time 291696132 ps
CPU time 8.1 seconds
Started Jul 18 05:15:32 PM PDT 24
Finished Jul 18 05:15:41 PM PDT 24
Peak memory 216784 kb
Host smart-855980c2-ea11-406d-afee-2fe57d16cbbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946212002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.946212002
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3863269003
Short name T616
Test name
Test status
Simulation time 35741015 ps
CPU time 1.99 seconds
Started Jul 18 05:15:32 PM PDT 24
Finished Jul 18 05:15:36 PM PDT 24
Peak memory 217796 kb
Host smart-3ec374ef-b8d3-4591-98ae-bb2ad6149113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863269003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3863269003
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2363966714
Short name T524
Test name
Test status
Simulation time 415686768 ps
CPU time 18.47 seconds
Started Jul 18 05:15:29 PM PDT 24
Finished Jul 18 05:15:48 PM PDT 24
Peak memory 218508 kb
Host smart-0f5db716-bc57-4e4d-b6e8-0e632067c77e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363966714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2363966714
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.502136310
Short name T175
Test name
Test status
Simulation time 341364077 ps
CPU time 13.28 seconds
Started Jul 18 05:15:26 PM PDT 24
Finished Jul 18 05:15:40 PM PDT 24
Peak memory 217728 kb
Host smart-aa47d6d3-a805-4fd7-9595-9adc8276db4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502136310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.502136310
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.4151624394
Short name T411
Test name
Test status
Simulation time 286988890 ps
CPU time 10.95 seconds
Started Jul 18 05:15:30 PM PDT 24
Finished Jul 18 05:15:43 PM PDT 24
Peak memory 225332 kb
Host smart-bf021bb3-53d4-4855-89f1-c76b7b0623b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151624394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
4151624394
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.560871372
Short name T69
Test name
Test status
Simulation time 3402532446 ps
CPU time 8.69 seconds
Started Jul 18 05:15:27 PM PDT 24
Finished Jul 18 05:15:37 PM PDT 24
Peak memory 217904 kb
Host smart-6375292d-dd26-4ba3-8f95-9c63712f3fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560871372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.560871372
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1967950469
Short name T270
Test name
Test status
Simulation time 413246295 ps
CPU time 3.59 seconds
Started Jul 18 05:15:31 PM PDT 24
Finished Jul 18 05:15:36 PM PDT 24
Peak memory 217164 kb
Host smart-ce883ee3-c72e-432a-bfdb-35ec5f663b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967950469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1967950469
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2199929037
Short name T447
Test name
Test status
Simulation time 783598620 ps
CPU time 24.54 seconds
Started Jul 18 05:15:33 PM PDT 24
Finished Jul 18 05:15:59 PM PDT 24
Peak memory 250512 kb
Host smart-e605892f-d1a5-44c3-818d-baa622f3ca83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199929037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2199929037
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3428758624
Short name T512
Test name
Test status
Simulation time 76434993 ps
CPU time 7.25 seconds
Started Jul 18 05:15:28 PM PDT 24
Finished Jul 18 05:15:36 PM PDT 24
Peak memory 246456 kb
Host smart-acf6f2d1-783e-4bdf-ba55-7bff1903e88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428758624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3428758624
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.360690831
Short name T91
Test name
Test status
Simulation time 6899056218 ps
CPU time 244.71 seconds
Started Jul 18 05:15:33 PM PDT 24
Finished Jul 18 05:19:39 PM PDT 24
Peak memory 278168 kb
Host smart-239a2879-3039-4e61-a4a3-6e400c640f25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360690831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.360690831
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.2092777686
Short name T108
Test name
Test status
Simulation time 89354791995 ps
CPU time 1222.17 seconds
Started Jul 18 05:15:28 PM PDT 24
Finished Jul 18 05:35:51 PM PDT 24
Peak memory 267112 kb
Host smart-bfcf64ba-50d5-49f1-86ed-35a489fdead4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2092777686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.2092777686
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2081297885
Short name T522
Test name
Test status
Simulation time 115159264 ps
CPU time 0.79 seconds
Started Jul 18 05:15:31 PM PDT 24
Finished Jul 18 05:15:34 PM PDT 24
Peak memory 208460 kb
Host smart-7cc4b1f0-eb95-4341-acb6-5c097f65e2b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081297885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2081297885
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2844673488
Short name T326
Test name
Test status
Simulation time 14634286 ps
CPU time 1.02 seconds
Started Jul 18 05:15:31 PM PDT 24
Finished Jul 18 05:15:33 PM PDT 24
Peak memory 208388 kb
Host smart-9e55ba00-658f-4549-bf7f-15683ec4bf79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844673488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2844673488
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.4246800470
Short name T743
Test name
Test status
Simulation time 223686174 ps
CPU time 9.81 seconds
Started Jul 18 05:15:28 PM PDT 24
Finished Jul 18 05:15:39 PM PDT 24
Peak memory 217852 kb
Host smart-9c4e3568-fb9e-42e6-ae6b-003d951198ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246800470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.4246800470
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3428687108
Short name T11
Test name
Test status
Simulation time 1187380769 ps
CPU time 8.19 seconds
Started Jul 18 05:15:33 PM PDT 24
Finished Jul 18 05:15:43 PM PDT 24
Peak memory 216796 kb
Host smart-74e2a86f-66bb-4bad-b6c7-3eff6a1561d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428687108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3428687108
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3771754838
Short name T648
Test name
Test status
Simulation time 175407845 ps
CPU time 2.87 seconds
Started Jul 18 05:15:30 PM PDT 24
Finished Jul 18 05:15:34 PM PDT 24
Peak memory 217692 kb
Host smart-806efd0d-37ea-4e89-a670-25bb6edf3855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771754838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3771754838
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.535636474
Short name T348
Test name
Test status
Simulation time 441977313 ps
CPU time 16.53 seconds
Started Jul 18 05:15:26 PM PDT 24
Finished Jul 18 05:15:44 PM PDT 24
Peak memory 225556 kb
Host smart-bc6f5edb-5c1f-4e46-a48b-d81987e180d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535636474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.535636474
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.563771911
Short name T332
Test name
Test status
Simulation time 1495085901 ps
CPU time 13.48 seconds
Started Jul 18 05:15:32 PM PDT 24
Finished Jul 18 05:15:47 PM PDT 24
Peak memory 217776 kb
Host smart-6057625b-5f8e-4b5d-b5cd-1d0a51fc457b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563771911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.563771911
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1259687488
Short name T156
Test name
Test status
Simulation time 319075307 ps
CPU time 11.2 seconds
Started Jul 18 05:15:31 PM PDT 24
Finished Jul 18 05:15:43 PM PDT 24
Peak memory 225508 kb
Host smart-24bbcba3-384a-4410-b596-c91691b20eee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259687488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1259687488
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1457517163
Short name T816
Test name
Test status
Simulation time 57195189 ps
CPU time 2.5 seconds
Started Jul 18 05:15:29 PM PDT 24
Finished Jul 18 05:15:33 PM PDT 24
Peak memory 217160 kb
Host smart-882610fd-2c8d-41a6-8163-b68c987ccbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457517163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1457517163
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.537409950
Short name T238
Test name
Test status
Simulation time 315756749 ps
CPU time 30.02 seconds
Started Jul 18 05:15:31 PM PDT 24
Finished Jul 18 05:16:02 PM PDT 24
Peak memory 250540 kb
Host smart-ed36ff99-12fa-4f96-b0f4-28d04a8a3f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537409950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.537409950
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3014726143
Short name T99
Test name
Test status
Simulation time 477366586 ps
CPU time 9.22 seconds
Started Jul 18 05:15:26 PM PDT 24
Finished Jul 18 05:15:36 PM PDT 24
Peak memory 250532 kb
Host smart-64f48c3a-5e7a-4433-a9fd-652baba7297c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014726143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3014726143
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3518984270
Short name T830
Test name
Test status
Simulation time 28555956355 ps
CPU time 231.13 seconds
Started Jul 18 05:15:27 PM PDT 24
Finished Jul 18 05:19:19 PM PDT 24
Peak memory 269908 kb
Host smart-cdbb3f1c-3ffa-4698-b005-02fdc87c87de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518984270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3518984270
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3077452566
Short name T856
Test name
Test status
Simulation time 12862062 ps
CPU time 1.01 seconds
Started Jul 18 05:15:36 PM PDT 24
Finished Jul 18 05:15:39 PM PDT 24
Peak memory 211348 kb
Host smart-3bc863eb-1152-4f4b-b6bf-9416b91e772a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077452566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3077452566
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3889080500
Short name T704
Test name
Test status
Simulation time 197929318 ps
CPU time 1.22 seconds
Started Jul 18 05:15:37 PM PDT 24
Finished Jul 18 05:15:39 PM PDT 24
Peak memory 208456 kb
Host smart-a9c4b35e-4881-4650-a50a-cfee0f639f86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889080500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3889080500
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3261941998
Short name T605
Test name
Test status
Simulation time 224558085 ps
CPU time 8.31 seconds
Started Jul 18 05:15:29 PM PDT 24
Finished Jul 18 05:15:39 PM PDT 24
Peak memory 217940 kb
Host smart-d91f23db-c163-43df-9b95-7f3516a69c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261941998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3261941998
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1667339375
Short name T102
Test name
Test status
Simulation time 153113707 ps
CPU time 1.81 seconds
Started Jul 18 05:15:34 PM PDT 24
Finished Jul 18 05:15:37 PM PDT 24
Peak memory 216652 kb
Host smart-0eb2cdce-517e-4e52-a793-50f2fa8df954
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667339375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1667339375
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2088555673
Short name T661
Test name
Test status
Simulation time 127233729 ps
CPU time 2.37 seconds
Started Jul 18 05:15:28 PM PDT 24
Finished Jul 18 05:15:32 PM PDT 24
Peak memory 221680 kb
Host smart-66e7f121-1fc5-4423-82e7-28213279d4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088555673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2088555673
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1684985889
Short name T498
Test name
Test status
Simulation time 3253433888 ps
CPU time 15.05 seconds
Started Jul 18 05:15:37 PM PDT 24
Finished Jul 18 05:15:53 PM PDT 24
Peak memory 219504 kb
Host smart-abd4f8a9-fd5d-45cd-a27b-af657a21f46c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684985889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1684985889
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.618280376
Short name T521
Test name
Test status
Simulation time 844500479 ps
CPU time 8.72 seconds
Started Jul 18 05:15:36 PM PDT 24
Finished Jul 18 05:15:46 PM PDT 24
Peak memory 217776 kb
Host smart-e4c46b7a-3e27-4041-9303-4268cde91e98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618280376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.618280376
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2015657909
Short name T660
Test name
Test status
Simulation time 504245421 ps
CPU time 8.84 seconds
Started Jul 18 05:15:32 PM PDT 24
Finished Jul 18 05:15:43 PM PDT 24
Peak memory 225184 kb
Host smart-365dd461-5c89-43b3-9ba2-ab1c38425b29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015657909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2015657909
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3740440579
Short name T325
Test name
Test status
Simulation time 1139010669 ps
CPU time 11.24 seconds
Started Jul 18 05:15:29 PM PDT 24
Finished Jul 18 05:15:42 PM PDT 24
Peak memory 217772 kb
Host smart-4105b841-007c-44be-b90f-5417b77d60e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740440579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3740440579
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2371154086
Short name T321
Test name
Test status
Simulation time 184326428 ps
CPU time 4.9 seconds
Started Jul 18 05:15:28 PM PDT 24
Finished Jul 18 05:15:34 PM PDT 24
Peak memory 217156 kb
Host smart-b5b10144-6cdb-4a00-86d0-c6fac8dec9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371154086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2371154086
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1668146980
Short name T863
Test name
Test status
Simulation time 598439544 ps
CPU time 31.33 seconds
Started Jul 18 05:15:30 PM PDT 24
Finished Jul 18 05:16:03 PM PDT 24
Peak memory 250376 kb
Host smart-b5eb4029-285f-4d83-a21f-258c3979e014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668146980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1668146980
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3918112134
Short name T259
Test name
Test status
Simulation time 442756479 ps
CPU time 8.02 seconds
Started Jul 18 05:15:30 PM PDT 24
Finished Jul 18 05:15:40 PM PDT 24
Peak memory 250536 kb
Host smart-5c422ad5-d071-4b0a-b4b1-d73379a76742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918112134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3918112134
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.4202691990
Short name T501
Test name
Test status
Simulation time 8403710850 ps
CPU time 103.51 seconds
Started Jul 18 05:15:29 PM PDT 24
Finished Jul 18 05:17:14 PM PDT 24
Peak memory 226760 kb
Host smart-5f2512cd-a03e-4548-8c25-e86c50c78fec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202691990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.4202691990
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3466002418
Short name T261
Test name
Test status
Simulation time 22488457 ps
CPU time 0.82 seconds
Started Jul 18 05:15:28 PM PDT 24
Finished Jul 18 05:15:30 PM PDT 24
Peak memory 208364 kb
Host smart-bcf45f3c-990c-4c65-8dec-a47d63dd91db
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466002418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3466002418
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2530239784
Short name T273
Test name
Test status
Simulation time 47310432 ps
CPU time 1 seconds
Started Jul 18 05:15:43 PM PDT 24
Finished Jul 18 05:15:46 PM PDT 24
Peak memory 208340 kb
Host smart-9528fb32-6541-4040-a75d-e58a19f39982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530239784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2530239784
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2195724388
Short name T547
Test name
Test status
Simulation time 400828029 ps
CPU time 17.69 seconds
Started Jul 18 05:15:46 PM PDT 24
Finished Jul 18 05:16:07 PM PDT 24
Peak memory 217784 kb
Host smart-e9ba58fd-d0ad-418d-96be-0f1ee3b2e0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195724388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2195724388
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1881608437
Short name T465
Test name
Test status
Simulation time 1953745626 ps
CPU time 6.43 seconds
Started Jul 18 05:15:44 PM PDT 24
Finished Jul 18 05:15:52 PM PDT 24
Peak memory 216948 kb
Host smart-a1305d67-f1e3-4475-b1bf-c15b670209ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881608437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1881608437
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3718649421
Short name T545
Test name
Test status
Simulation time 479977113 ps
CPU time 3.83 seconds
Started Jul 18 05:15:43 PM PDT 24
Finished Jul 18 05:15:48 PM PDT 24
Peak memory 222032 kb
Host smart-06c87a37-6fe1-4ebc-9a4f-22881e3a7cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718649421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3718649421
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.522589156
Short name T285
Test name
Test status
Simulation time 443216028 ps
CPU time 12.81 seconds
Started Jul 18 05:15:45 PM PDT 24
Finished Jul 18 05:16:01 PM PDT 24
Peak memory 225588 kb
Host smart-bc12ba6c-6c20-4dff-8381-138d5b022296
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522589156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.522589156
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1370936956
Short name T641
Test name
Test status
Simulation time 360028694 ps
CPU time 13.63 seconds
Started Jul 18 05:15:44 PM PDT 24
Finished Jul 18 05:15:59 PM PDT 24
Peak memory 225524 kb
Host smart-aed48203-dc0b-4a9f-8191-c04caeca3fee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370936956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1370936956
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3730941818
Short name T178
Test name
Test status
Simulation time 611865007 ps
CPU time 6.19 seconds
Started Jul 18 05:15:46 PM PDT 24
Finished Jul 18 05:15:55 PM PDT 24
Peak memory 217692 kb
Host smart-d1f2f486-05dc-4a83-a87e-57818bcd1aaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730941818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3730941818
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3592200066
Short name T482
Test name
Test status
Simulation time 1232619747 ps
CPU time 9.05 seconds
Started Jul 18 05:15:43 PM PDT 24
Finished Jul 18 05:15:54 PM PDT 24
Peak memory 217836 kb
Host smart-ffc22bb7-0909-4cda-9fbf-9ed73fede80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592200066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3592200066
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3179481064
Short name T90
Test name
Test status
Simulation time 92548146 ps
CPU time 3.02 seconds
Started Jul 18 05:15:30 PM PDT 24
Finished Jul 18 05:15:34 PM PDT 24
Peak memory 214412 kb
Host smart-41ff414c-553f-4d4c-adcb-b89da6ded264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179481064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3179481064
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1124063862
Short name T470
Test name
Test status
Simulation time 221201922 ps
CPU time 28.48 seconds
Started Jul 18 05:15:45 PM PDT 24
Finished Jul 18 05:16:16 PM PDT 24
Peak memory 250512 kb
Host smart-53966793-ddc5-40c6-bb15-51a1117e9cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124063862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1124063862
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.227329288
Short name T574
Test name
Test status
Simulation time 213203369 ps
CPU time 7.33 seconds
Started Jul 18 05:15:46 PM PDT 24
Finished Jul 18 05:15:56 PM PDT 24
Peak memory 250040 kb
Host smart-5b316546-5995-4e0c-98ea-17b4603cb9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227329288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.227329288
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.773734290
Short name T717
Test name
Test status
Simulation time 12707122108 ps
CPU time 75.22 seconds
Started Jul 18 05:15:45 PM PDT 24
Finished Jul 18 05:17:03 PM PDT 24
Peak memory 267328 kb
Host smart-c3d68297-7f63-4234-8833-d67de8716adc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773734290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.773734290
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2493211356
Short name T793
Test name
Test status
Simulation time 38287454 ps
CPU time 0.81 seconds
Started Jul 18 05:15:46 PM PDT 24
Finished Jul 18 05:15:50 PM PDT 24
Peak memory 208352 kb
Host smart-f6849487-5d76-4b05-be26-256e11ed9d42
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493211356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.2493211356
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.875883991
Short name T438
Test name
Test status
Simulation time 56756148 ps
CPU time 1.08 seconds
Started Jul 18 05:15:52 PM PDT 24
Finished Jul 18 05:15:54 PM PDT 24
Peak memory 208476 kb
Host smart-f2524670-fd8e-4d07-9dcc-d739d6aefd50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875883991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.875883991
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.660379235
Short name T427
Test name
Test status
Simulation time 880522279 ps
CPU time 10.84 seconds
Started Jul 18 05:15:58 PM PDT 24
Finished Jul 18 05:16:09 PM PDT 24
Peak memory 217800 kb
Host smart-709f42d2-d2b7-4a15-b871-2a2b5b3ed117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660379235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.660379235
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3104843000
Short name T302
Test name
Test status
Simulation time 1778623398 ps
CPU time 11.48 seconds
Started Jul 18 05:15:48 PM PDT 24
Finished Jul 18 05:16:02 PM PDT 24
Peak memory 217192 kb
Host smart-5fec4c46-f7ba-47d8-a998-c10c91e84a86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104843000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3104843000
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1417273138
Short name T416
Test name
Test status
Simulation time 120231452 ps
CPU time 1.99 seconds
Started Jul 18 05:15:44 PM PDT 24
Finished Jul 18 05:15:48 PM PDT 24
Peak memory 221664 kb
Host smart-c8f296db-c581-4f0b-b82f-cbd2f841aac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417273138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1417273138
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.342207673
Short name T284
Test name
Test status
Simulation time 365385593 ps
CPU time 14.92 seconds
Started Jul 18 05:15:43 PM PDT 24
Finished Jul 18 05:15:58 PM PDT 24
Peak memory 217748 kb
Host smart-6234df9d-eb82-4c2d-be32-a531456d569e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342207673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di
gest.342207673
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3220835849
Short name T234
Test name
Test status
Simulation time 941748401 ps
CPU time 10.48 seconds
Started Jul 18 05:15:43 PM PDT 24
Finished Jul 18 05:15:55 PM PDT 24
Peak memory 224464 kb
Host smart-7dca51c7-caaa-4abb-a4c4-e526c2713f35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220835849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3220835849
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1570394476
Short name T296
Test name
Test status
Simulation time 286968811 ps
CPU time 7.3 seconds
Started Jul 18 05:15:46 PM PDT 24
Finished Jul 18 05:15:56 PM PDT 24
Peak memory 217812 kb
Host smart-5a92eaef-f3d3-448b-b490-6335094cd24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570394476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1570394476
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3677120358
Short name T670
Test name
Test status
Simulation time 682445386 ps
CPU time 2.6 seconds
Started Jul 18 05:15:48 PM PDT 24
Finished Jul 18 05:15:53 PM PDT 24
Peak memory 213980 kb
Host smart-b4953d5e-74da-4a3d-b1fa-c136f7536782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677120358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3677120358
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2889159720
Short name T732
Test name
Test status
Simulation time 971612437 ps
CPU time 28.13 seconds
Started Jul 18 05:15:43 PM PDT 24
Finished Jul 18 05:16:12 PM PDT 24
Peak memory 250512 kb
Host smart-5db04b23-4b94-4403-bb35-54712bd0acde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889159720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2889159720
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1189288238
Short name T572
Test name
Test status
Simulation time 325842313 ps
CPU time 3.53 seconds
Started Jul 18 05:15:47 PM PDT 24
Finished Jul 18 05:15:54 PM PDT 24
Peak memory 222512 kb
Host smart-47e12023-466f-43b9-95fe-abf623549fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189288238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1189288238
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.986635082
Short name T490
Test name
Test status
Simulation time 6702568961 ps
CPU time 215.06 seconds
Started Jul 18 05:15:42 PM PDT 24
Finished Jul 18 05:19:18 PM PDT 24
Peak memory 258736 kb
Host smart-5fe61d73-21fc-4335-930a-1b541ba0a6cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986635082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.986635082
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.4169094549
Short name T161
Test name
Test status
Simulation time 31304359754 ps
CPU time 341.38 seconds
Started Jul 18 05:15:46 PM PDT 24
Finished Jul 18 05:21:31 PM PDT 24
Peak memory 496452 kb
Host smart-af301499-ea11-4e34-b879-ff0a24aa65f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4169094549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.4169094549
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.860589571
Short name T842
Test name
Test status
Simulation time 41655040 ps
CPU time 1.07 seconds
Started Jul 18 05:15:43 PM PDT 24
Finished Jul 18 05:15:46 PM PDT 24
Peak memory 211372 kb
Host smart-0df8688a-4e85-4c84-82ec-1cf05d653db4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860589571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.860589571
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2048698596
Short name T734
Test name
Test status
Simulation time 30131047 ps
CPU time 1.03 seconds
Started Jul 18 05:16:01 PM PDT 24
Finished Jul 18 05:16:02 PM PDT 24
Peak memory 208412 kb
Host smart-ed1792f5-1216-420c-917d-cfad4181727e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048698596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2048698596
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2815678332
Short name T665
Test name
Test status
Simulation time 589946276 ps
CPU time 16.18 seconds
Started Jul 18 05:15:54 PM PDT 24
Finished Jul 18 05:16:11 PM PDT 24
Peak memory 217784 kb
Host smart-8af5ae55-c030-41b9-b9a7-30c65440a969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815678332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2815678332
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1663004654
Short name T759
Test name
Test status
Simulation time 185656584 ps
CPU time 3.16 seconds
Started Jul 18 05:15:46 PM PDT 24
Finished Jul 18 05:15:52 PM PDT 24
Peak memory 216688 kb
Host smart-cf4aa152-743e-4529-a41b-c92f4f700f5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663004654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1663004654
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.318146856
Short name T753
Test name
Test status
Simulation time 182976639 ps
CPU time 2.34 seconds
Started Jul 18 05:15:47 PM PDT 24
Finished Jul 18 05:15:53 PM PDT 24
Peak memory 217772 kb
Host smart-7c6982b7-c86d-4bb3-b04a-8df1b2b2a14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318146856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.318146856
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3576679700
Short name T573
Test name
Test status
Simulation time 729779728 ps
CPU time 14.95 seconds
Started Jul 18 05:15:44 PM PDT 24
Finished Jul 18 05:16:00 PM PDT 24
Peak memory 218432 kb
Host smart-3e0049df-b763-4805-ad0e-6d58614c1ae3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576679700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3576679700
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1539824969
Short name T861
Test name
Test status
Simulation time 751783486 ps
CPU time 9.5 seconds
Started Jul 18 05:15:46 PM PDT 24
Finished Jul 18 05:15:58 PM PDT 24
Peak memory 217764 kb
Host smart-6f13d816-ac40-4156-a402-ef4b52a61037
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539824969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1539824969
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.123722877
Short name T588
Test name
Test status
Simulation time 1114327661 ps
CPU time 7.14 seconds
Started Jul 18 05:15:47 PM PDT 24
Finished Jul 18 05:15:58 PM PDT 24
Peak memory 225512 kb
Host smart-0d3f03ca-1fdf-4676-b2a8-315c89b74d2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123722877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.123722877
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3731236035
Short name T577
Test name
Test status
Simulation time 3031816008 ps
CPU time 7.73 seconds
Started Jul 18 05:15:48 PM PDT 24
Finished Jul 18 05:15:59 PM PDT 24
Peak memory 217884 kb
Host smart-3ab7d4ae-ca90-4c11-a71b-1759b30ed154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731236035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3731236035
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.956637966
Short name T76
Test name
Test status
Simulation time 221617769 ps
CPU time 3.26 seconds
Started Jul 18 05:15:51 PM PDT 24
Finished Jul 18 05:15:55 PM PDT 24
Peak memory 217184 kb
Host smart-b5de36d4-f03e-424c-a713-f54a9e763c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956637966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.956637966
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.4165244416
Short name T353
Test name
Test status
Simulation time 1776300239 ps
CPU time 27.74 seconds
Started Jul 18 05:15:46 PM PDT 24
Finished Jul 18 05:16:17 PM PDT 24
Peak memory 250520 kb
Host smart-5cf9ac71-fc93-42d2-b9c8-f7d611cad810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165244416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.4165244416
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.903347856
Short name T654
Test name
Test status
Simulation time 323258658 ps
CPU time 3.55 seconds
Started Jul 18 05:15:56 PM PDT 24
Finished Jul 18 05:16:00 PM PDT 24
Peak memory 221828 kb
Host smart-ca8f9c3b-0f8c-430b-9b15-bd51eff37edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903347856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.903347856
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1251620353
Short name T253
Test name
Test status
Simulation time 10890962206 ps
CPU time 211.25 seconds
Started Jul 18 05:15:44 PM PDT 24
Finished Jul 18 05:19:17 PM PDT 24
Peak memory 272800 kb
Host smart-f877d494-dac4-413c-a7ec-03dea89591af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251620353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1251620353
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.2311593831
Short name T748
Test name
Test status
Simulation time 40712843810 ps
CPU time 180.42 seconds
Started Jul 18 05:15:44 PM PDT 24
Finished Jul 18 05:18:47 PM PDT 24
Peak memory 275776 kb
Host smart-c8429fec-4772-4697-8ee3-46e02a12dc1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2311593831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.2311593831
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1458032991
Short name T869
Test name
Test status
Simulation time 55181338 ps
CPU time 0.85 seconds
Started Jul 18 05:15:54 PM PDT 24
Finished Jul 18 05:15:56 PM PDT 24
Peak memory 207728 kb
Host smart-830028af-4228-4390-af07-c569a1be7a45
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458032991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1458032991
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.4067307104
Short name T679
Test name
Test status
Simulation time 27914242 ps
CPU time 0.99 seconds
Started Jul 18 05:13:12 PM PDT 24
Finished Jul 18 05:13:17 PM PDT 24
Peak memory 208396 kb
Host smart-451d33e4-fab2-40f8-91f1-053f428f1ebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067307104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.4067307104
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.4164897587
Short name T553
Test name
Test status
Simulation time 424390437 ps
CPU time 13.21 seconds
Started Jul 18 05:13:05 PM PDT 24
Finished Jul 18 05:13:20 PM PDT 24
Peak memory 217836 kb
Host smart-74a5bfbe-1793-46ff-89c9-b60fd3036792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164897587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.4164897587
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.744086661
Short name T31
Test name
Test status
Simulation time 1374929832 ps
CPU time 10.08 seconds
Started Jul 18 05:13:10 PM PDT 24
Finished Jul 18 05:13:24 PM PDT 24
Peak memory 216908 kb
Host smart-df3a8e8a-ac04-4a83-854e-faa974e14b9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744086661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.744086661
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.830204506
Short name T406
Test name
Test status
Simulation time 26514585121 ps
CPU time 40.05 seconds
Started Jul 18 05:13:06 PM PDT 24
Finished Jul 18 05:13:50 PM PDT 24
Peak memory 218384 kb
Host smart-df3e221c-8364-4f2e-9ea2-bfb3f1e2c6e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830204506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.830204506
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1531406858
Short name T7
Test name
Test status
Simulation time 81854271 ps
CPU time 2.94 seconds
Started Jul 18 05:13:07 PM PDT 24
Finished Jul 18 05:13:14 PM PDT 24
Peak memory 217164 kb
Host smart-bf4928ea-a87f-4c23-87d4-e81a960bb725
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531406858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
531406858
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1501572872
Short name T225
Test name
Test status
Simulation time 486358343 ps
CPU time 14.42 seconds
Started Jul 18 05:13:10 PM PDT 24
Finished Jul 18 05:13:28 PM PDT 24
Peak memory 223948 kb
Host smart-fde8e296-2b77-4ec0-aa0c-4521d355b938
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501572872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1501572872
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3196271423
Short name T727
Test name
Test status
Simulation time 4563947908 ps
CPU time 17.78 seconds
Started Jul 18 05:13:07 PM PDT 24
Finished Jul 18 05:13:29 PM PDT 24
Peak memory 217196 kb
Host smart-2570f5e6-becf-410e-96a5-57cb541b426b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196271423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3196271423
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.11528016
Short name T865
Test name
Test status
Simulation time 194944534 ps
CPU time 2.32 seconds
Started Jul 18 05:13:06 PM PDT 24
Finished Jul 18 05:13:12 PM PDT 24
Peak memory 217116 kb
Host smart-dc200ac1-9490-4b23-b18d-820a7c658dee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11528016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.11528016
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2580789593
Short name T160
Test name
Test status
Simulation time 1292029723 ps
CPU time 43.71 seconds
Started Jul 18 05:13:10 PM PDT 24
Finished Jul 18 05:13:58 PM PDT 24
Peak memory 250672 kb
Host smart-ab463dd5-ab10-4e40-bad3-a654e8ed047a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580789593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2580789593
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3607496270
Short name T23
Test name
Test status
Simulation time 1137789418 ps
CPU time 21.27 seconds
Started Jul 18 05:13:06 PM PDT 24
Finished Jul 18 05:13:30 PM PDT 24
Peak memory 247480 kb
Host smart-aafa1029-7ce0-4f11-a158-ce863b392ee3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607496270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3607496270
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3565480822
Short name T532
Test name
Test status
Simulation time 182271028 ps
CPU time 4.29 seconds
Started Jul 18 05:13:06 PM PDT 24
Finished Jul 18 05:13:13 PM PDT 24
Peak memory 217768 kb
Host smart-8f3577b2-47e6-4895-9cd1-b0b304fe8f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565480822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3565480822
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1552832696
Short name T569
Test name
Test status
Simulation time 4033526044 ps
CPU time 9.27 seconds
Started Jul 18 05:13:10 PM PDT 24
Finished Jul 18 05:13:24 PM PDT 24
Peak memory 217256 kb
Host smart-91d22b77-2683-4fea-8b37-cfb9fec53f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552832696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1552832696
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1771567521
Short name T68
Test name
Test status
Simulation time 226639284 ps
CPU time 35.93 seconds
Started Jul 18 05:13:12 PM PDT 24
Finished Jul 18 05:13:52 PM PDT 24
Peak memory 283060 kb
Host smart-1d1d0012-6b2c-4700-b68e-a3c68100e803
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771567521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1771567521
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2502018772
Short name T496
Test name
Test status
Simulation time 603983256 ps
CPU time 10.62 seconds
Started Jul 18 05:13:11 PM PDT 24
Finished Jul 18 05:13:25 PM PDT 24
Peak memory 225568 kb
Host smart-52206008-4b23-4657-8348-e3e56efed1f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502018772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2502018772
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2793155706
Short name T340
Test name
Test status
Simulation time 3076378659 ps
CPU time 11.21 seconds
Started Jul 18 05:13:12 PM PDT 24
Finished Jul 18 05:13:27 PM PDT 24
Peak memory 225580 kb
Host smart-57b74c58-a265-4aba-86ff-50ce0318869b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793155706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2793155706
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.40635207
Short name T449
Test name
Test status
Simulation time 339366931 ps
CPU time 12.24 seconds
Started Jul 18 05:13:08 PM PDT 24
Finished Jul 18 05:13:24 PM PDT 24
Peak memory 225476 kb
Host smart-a82f3bdd-bd40-44ec-8314-75e7179d4164
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40635207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.40635207
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.772503551
Short name T768
Test name
Test status
Simulation time 1240258932 ps
CPU time 6.69 seconds
Started Jul 18 05:13:11 PM PDT 24
Finished Jul 18 05:13:22 PM PDT 24
Peak memory 218060 kb
Host smart-b3f58d3c-dc6a-401b-8a61-bd9a1fd83c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772503551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.772503551
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1156320018
Short name T494
Test name
Test status
Simulation time 27342851 ps
CPU time 1.83 seconds
Started Jul 18 05:13:10 PM PDT 24
Finished Jul 18 05:13:16 PM PDT 24
Peak memory 217420 kb
Host smart-0454f932-8d88-4b2f-9820-c328ade441c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156320018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1156320018
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.4189994730
Short name T217
Test name
Test status
Simulation time 321634393 ps
CPU time 28.6 seconds
Started Jul 18 05:13:27 PM PDT 24
Finished Jul 18 05:14:00 PM PDT 24
Peak memory 250580 kb
Host smart-449fbff1-5fd9-4883-9350-10d99b259ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189994730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.4189994730
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3208119091
Short name T362
Test name
Test status
Simulation time 232259812 ps
CPU time 7.49 seconds
Started Jul 18 05:13:07 PM PDT 24
Finished Jul 18 05:13:18 PM PDT 24
Peak memory 250248 kb
Host smart-1d9a30df-815b-485d-9487-8f3625dcdce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208119091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3208119091
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.365369331
Short name T639
Test name
Test status
Simulation time 6539003939 ps
CPU time 131.38 seconds
Started Jul 18 05:13:11 PM PDT 24
Finished Jul 18 05:15:26 PM PDT 24
Peak memory 275180 kb
Host smart-9b4f3a75-8340-452a-be47-b744df4be052
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365369331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.365369331
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.4183467513
Short name T560
Test name
Test status
Simulation time 23655402 ps
CPU time 0.84 seconds
Started Jul 18 05:13:08 PM PDT 24
Finished Jul 18 05:13:13 PM PDT 24
Peak memory 208160 kb
Host smart-86c813dd-604a-44a5-922b-ac93976d1976
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183467513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.4183467513
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1574066535
Short name T599
Test name
Test status
Simulation time 16289723 ps
CPU time 1.09 seconds
Started Jul 18 05:16:10 PM PDT 24
Finished Jul 18 05:16:13 PM PDT 24
Peak memory 208564 kb
Host smart-e74f7f45-c8ae-4409-9576-50627f74f2a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574066535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1574066535
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3682078953
Short name T45
Test name
Test status
Simulation time 365182863 ps
CPU time 14.7 seconds
Started Jul 18 05:15:46 PM PDT 24
Finished Jul 18 05:16:05 PM PDT 24
Peak memory 217800 kb
Host smart-1276f6a2-6b47-4fb8-8537-3da93d43ae1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682078953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3682078953
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.329588008
Short name T413
Test name
Test status
Simulation time 542753889 ps
CPU time 7.17 seconds
Started Jul 18 05:15:48 PM PDT 24
Finished Jul 18 05:15:58 PM PDT 24
Peak memory 217204 kb
Host smart-a49f33ae-08fc-42fe-8ccd-a62930fa6938
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329588008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.329588008
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3252369327
Short name T369
Test name
Test status
Simulation time 205530822 ps
CPU time 3.64 seconds
Started Jul 18 05:15:47 PM PDT 24
Finished Jul 18 05:15:54 PM PDT 24
Peak memory 217788 kb
Host smart-3efbb345-823c-45e5-996e-40c90cf56922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252369327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3252369327
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.607967234
Short name T433
Test name
Test status
Simulation time 325558076 ps
CPU time 8.8 seconds
Started Jul 18 05:15:45 PM PDT 24
Finished Jul 18 05:15:57 PM PDT 24
Peak memory 217872 kb
Host smart-ec6f9e93-5fc2-4024-a952-d0c6bcfd5204
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607967234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.607967234
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1403751383
Short name T376
Test name
Test status
Simulation time 3000440518 ps
CPU time 19.14 seconds
Started Jul 18 05:15:45 PM PDT 24
Finished Jul 18 05:16:07 PM PDT 24
Peak memory 218044 kb
Host smart-8da8779c-f4a4-408e-adf5-d544a7d27609
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403751383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1403751383
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.4250923344
Short name T832
Test name
Test status
Simulation time 1000507161 ps
CPU time 8 seconds
Started Jul 18 05:15:49 PM PDT 24
Finished Jul 18 05:15:59 PM PDT 24
Peak memory 225168 kb
Host smart-9281680e-2dc7-4445-87d5-e69048c56d14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250923344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
4250923344
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1843094050
Short name T153
Test name
Test status
Simulation time 244729430 ps
CPU time 7.44 seconds
Started Jul 18 05:15:45 PM PDT 24
Finished Jul 18 05:15:54 PM PDT 24
Peak memory 217812 kb
Host smart-335dc05c-f6de-46e5-a9fc-cb3c2e447e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843094050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1843094050
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3421017054
Short name T549
Test name
Test status
Simulation time 56033177 ps
CPU time 2.5 seconds
Started Jul 18 05:15:47 PM PDT 24
Finished Jul 18 05:15:53 PM PDT 24
Peak memory 213976 kb
Host smart-ea08da1e-4e43-4c79-9468-7fbe164dbd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421017054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3421017054
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1440792120
Short name T456
Test name
Test status
Simulation time 150231183 ps
CPU time 22.72 seconds
Started Jul 18 05:15:48 PM PDT 24
Finished Jul 18 05:16:14 PM PDT 24
Peak memory 250208 kb
Host smart-762d248a-7685-4a8a-9320-bc88d83873b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440792120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1440792120
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2060993439
Short name T590
Test name
Test status
Simulation time 102523682 ps
CPU time 6.56 seconds
Started Jul 18 05:15:44 PM PDT 24
Finished Jul 18 05:15:53 PM PDT 24
Peak memory 250724 kb
Host smart-4cb8f277-d8ab-42ab-90d9-ef2544cf6d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060993439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2060993439
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.4200287695
Short name T771
Test name
Test status
Simulation time 21052955828 ps
CPU time 264.06 seconds
Started Jul 18 05:15:45 PM PDT 24
Finished Jul 18 05:20:10 PM PDT 24
Peak memory 221412 kb
Host smart-d38f9a42-492a-4777-9c62-65660b41ef07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200287695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.4200287695
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3282016263
Short name T276
Test name
Test status
Simulation time 33409743 ps
CPU time 0.92 seconds
Started Jul 18 05:15:46 PM PDT 24
Finished Jul 18 05:15:51 PM PDT 24
Peak memory 211376 kb
Host smart-c32956a6-0a35-4678-9f48-c9fa25908bb8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282016263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3282016263
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.956813846
Short name T844
Test name
Test status
Simulation time 13211454 ps
CPU time 0.86 seconds
Started Jul 18 05:16:09 PM PDT 24
Finished Jul 18 05:16:11 PM PDT 24
Peak memory 208168 kb
Host smart-5c98c3e2-87e8-44e0-a086-fa471bf55c37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956813846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.956813846
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.121957656
Short name T699
Test name
Test status
Simulation time 1003537420 ps
CPU time 8.61 seconds
Started Jul 18 05:16:11 PM PDT 24
Finished Jul 18 05:16:22 PM PDT 24
Peak memory 217780 kb
Host smart-61ab4c19-05bd-44ad-91f7-71f19550ab32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121957656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.121957656
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.74200610
Short name T61
Test name
Test status
Simulation time 555220589 ps
CPU time 1.7 seconds
Started Jul 18 05:16:16 PM PDT 24
Finished Jul 18 05:16:21 PM PDT 24
Peak memory 216576 kb
Host smart-a99c62a3-6942-430e-8184-37a8ea8bfad5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74200610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.74200610
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2945573186
Short name T434
Test name
Test status
Simulation time 245227022 ps
CPU time 2.78 seconds
Started Jul 18 05:16:09 PM PDT 24
Finished Jul 18 05:16:14 PM PDT 24
Peak memory 217788 kb
Host smart-ba2c57ae-8570-46cc-8444-bde215bcd8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945573186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2945573186
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3687777071
Short name T281
Test name
Test status
Simulation time 283786744 ps
CPU time 13.73 seconds
Started Jul 18 05:16:15 PM PDT 24
Finished Jul 18 05:16:32 PM PDT 24
Peak memory 218392 kb
Host smart-8b8432db-ad3f-45a7-aaaa-0240d53ca5f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687777071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3687777071
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2345998669
Short name T487
Test name
Test status
Simulation time 1337112319 ps
CPU time 12.86 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:16:29 PM PDT 24
Peak memory 217832 kb
Host smart-ce019877-a6c2-4c08-9aab-d8be841c69be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345998669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2345998669
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1167430456
Short name T264
Test name
Test status
Simulation time 1843817479 ps
CPU time 10.36 seconds
Started Jul 18 05:16:19 PM PDT 24
Finished Jul 18 05:16:31 PM PDT 24
Peak memory 225416 kb
Host smart-7b6c9bba-37d2-4e4c-a3aa-8a45fabc566e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167430456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1167430456
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.779331236
Short name T400
Test name
Test status
Simulation time 5098688077 ps
CPU time 10.41 seconds
Started Jul 18 05:16:10 PM PDT 24
Finished Jul 18 05:16:22 PM PDT 24
Peak memory 217924 kb
Host smart-18af988f-71d3-4018-9a1d-74f7accaf4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779331236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.779331236
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2331483639
Short name T858
Test name
Test status
Simulation time 69917822 ps
CPU time 3.09 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:16:18 PM PDT 24
Peak memory 214352 kb
Host smart-c31114a1-13d7-46d9-83c8-08d13752051b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331483639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2331483639
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.4236383164
Short name T839
Test name
Test status
Simulation time 267886642 ps
CPU time 31.76 seconds
Started Jul 18 05:16:19 PM PDT 24
Finished Jul 18 05:16:53 PM PDT 24
Peak memory 250360 kb
Host smart-71cfc267-1d5f-4583-b278-ca42d0a1321a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236383164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.4236383164
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3056773243
Short name T368
Test name
Test status
Simulation time 50672530 ps
CPU time 3.21 seconds
Started Jul 18 05:16:12 PM PDT 24
Finished Jul 18 05:16:17 PM PDT 24
Peak memory 217700 kb
Host smart-98eca449-c14a-4cc5-b415-4df3b4722373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056773243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3056773243
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1091645425
Short name T110
Test name
Test status
Simulation time 12143797909 ps
CPU time 156.15 seconds
Started Jul 18 05:16:16 PM PDT 24
Finished Jul 18 05:18:55 PM PDT 24
Peak memory 316184 kb
Host smart-83d2a4f7-3be6-4fa7-b22f-5256239b400c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091645425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1091645425
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2142033722
Short name T653
Test name
Test status
Simulation time 17230340 ps
CPU time 1.19 seconds
Started Jul 18 05:16:08 PM PDT 24
Finished Jul 18 05:16:10 PM PDT 24
Peak memory 217332 kb
Host smart-94e16be5-54c9-497e-a989-debe6bc66e71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142033722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2142033722
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1120559801
Short name T95
Test name
Test status
Simulation time 64784881 ps
CPU time 0.9 seconds
Started Jul 18 05:16:14 PM PDT 24
Finished Jul 18 05:16:18 PM PDT 24
Peak memory 208328 kb
Host smart-16bd48ca-d12c-4bda-98b0-7e613c8641d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120559801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1120559801
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1023839842
Short name T428
Test name
Test status
Simulation time 430011949 ps
CPU time 15.87 seconds
Started Jul 18 05:16:16 PM PDT 24
Finished Jul 18 05:16:35 PM PDT 24
Peak memory 217804 kb
Host smart-c7640508-5037-4a14-ac4d-dfe3e0534de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023839842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1023839842
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.2631470085
Short name T402
Test name
Test status
Simulation time 1285005681 ps
CPU time 10.99 seconds
Started Jul 18 05:16:09 PM PDT 24
Finished Jul 18 05:16:21 PM PDT 24
Peak memory 216824 kb
Host smart-4e8c4a7d-8618-4d7d-a510-b535c11cd19c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631470085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2631470085
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1894897024
Short name T489
Test name
Test status
Simulation time 5074843043 ps
CPU time 13.5 seconds
Started Jul 18 05:16:12 PM PDT 24
Finished Jul 18 05:16:28 PM PDT 24
Peak memory 225628 kb
Host smart-27abbe5a-ad24-4a51-8177-f6ae54e727c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894897024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1894897024
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2636095201
Short name T420
Test name
Test status
Simulation time 3328474754 ps
CPU time 9.55 seconds
Started Jul 18 05:16:19 PM PDT 24
Finished Jul 18 05:16:30 PM PDT 24
Peak memory 217544 kb
Host smart-a65bddf5-9243-4fac-86bd-bc1f43e550a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636095201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2636095201
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3589570534
Short name T226
Test name
Test status
Simulation time 2913079228 ps
CPU time 9.96 seconds
Started Jul 18 05:16:16 PM PDT 24
Finished Jul 18 05:16:29 PM PDT 24
Peak memory 225568 kb
Host smart-8e534994-4dfe-4280-adbc-3e2f1d331919
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589570534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3589570534
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2853762656
Short name T383
Test name
Test status
Simulation time 1011763937 ps
CPU time 10.51 seconds
Started Jul 18 05:16:15 PM PDT 24
Finished Jul 18 05:16:29 PM PDT 24
Peak memory 217844 kb
Host smart-d385f1d5-6fb7-4499-955d-a46004cb11ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853762656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2853762656
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.208573986
Short name T709
Test name
Test status
Simulation time 60461577 ps
CPU time 1.77 seconds
Started Jul 18 05:16:16 PM PDT 24
Finished Jul 18 05:16:21 PM PDT 24
Peak memory 213568 kb
Host smart-9d3bcaef-59a9-4654-8ce9-6c00c9242548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208573986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.208573986
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.2408365816
Short name T520
Test name
Test status
Simulation time 1142343488 ps
CPU time 24.55 seconds
Started Jul 18 05:16:11 PM PDT 24
Finished Jul 18 05:16:37 PM PDT 24
Peak memory 250612 kb
Host smart-ab6363dd-c370-472e-a552-5dd9c008fdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408365816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2408365816
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1695297751
Short name T756
Test name
Test status
Simulation time 1095245433 ps
CPU time 9.59 seconds
Started Jul 18 05:16:16 PM PDT 24
Finished Jul 18 05:16:29 PM PDT 24
Peak memory 250536 kb
Host smart-7148ef77-006a-4b72-ac3c-4050f0d2ae13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695297751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1695297751
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2313709221
Short name T678
Test name
Test status
Simulation time 4076794235 ps
CPU time 85.45 seconds
Started Jul 18 05:16:17 PM PDT 24
Finished Jul 18 05:17:45 PM PDT 24
Peak memory 276764 kb
Host smart-b6e135c7-d889-48d8-b0cd-9254028c88c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313709221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2313709221
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.4233189134
Short name T43
Test name
Test status
Simulation time 14255733 ps
CPU time 1.01 seconds
Started Jul 18 05:16:08 PM PDT 24
Finished Jul 18 05:16:10 PM PDT 24
Peak memory 211300 kb
Host smart-18f940b3-9691-4a72-b5a8-ae76e05e66ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233189134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.4233189134
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.104705182
Short name T415
Test name
Test status
Simulation time 56836717 ps
CPU time 1.08 seconds
Started Jul 18 05:16:16 PM PDT 24
Finished Jul 18 05:16:20 PM PDT 24
Peak memory 208444 kb
Host smart-f0c6aa44-8093-4c9e-a40e-4d7626c3ac68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104705182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.104705182
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3913429001
Short name T293
Test name
Test status
Simulation time 2896126103 ps
CPU time 17.97 seconds
Started Jul 18 05:16:15 PM PDT 24
Finished Jul 18 05:16:36 PM PDT 24
Peak memory 218520 kb
Host smart-4071a74e-9f57-4611-ab2b-a3b9b01a5b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913429001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3913429001
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.126814197
Short name T724
Test name
Test status
Simulation time 711624208 ps
CPU time 5.43 seconds
Started Jul 18 05:16:19 PM PDT 24
Finished Jul 18 05:16:26 PM PDT 24
Peak memory 216664 kb
Host smart-8a5c15bf-46f0-40a1-a2df-8f9a5f6aedbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126814197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.126814197
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.538773698
Short name T811
Test name
Test status
Simulation time 25822453 ps
CPU time 1.94 seconds
Started Jul 18 05:16:16 PM PDT 24
Finished Jul 18 05:16:21 PM PDT 24
Peak memory 217492 kb
Host smart-2f554caf-1e10-4aec-b251-eff6d70c16c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538773698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.538773698
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2450237000
Short name T568
Test name
Test status
Simulation time 589475658 ps
CPU time 19.71 seconds
Started Jul 18 05:16:14 PM PDT 24
Finished Jul 18 05:16:37 PM PDT 24
Peak memory 225592 kb
Host smart-2f2c2189-a8ba-4d31-831e-9dda2fe82796
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450237000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2450237000
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1473810752
Short name T835
Test name
Test status
Simulation time 732889010 ps
CPU time 9.34 seconds
Started Jul 18 05:16:12 PM PDT 24
Finished Jul 18 05:16:24 PM PDT 24
Peak memory 217760 kb
Host smart-afecc323-c118-4382-b139-6dff8f464805
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473810752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1473810752
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.766895593
Short name T62
Test name
Test status
Simulation time 583045775 ps
CPU time 11.21 seconds
Started Jul 18 05:16:10 PM PDT 24
Finished Jul 18 05:16:23 PM PDT 24
Peak memory 225240 kb
Host smart-4aed939a-f33c-47ab-b036-883672bd2569
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766895593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.766895593
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.624037680
Short name T484
Test name
Test status
Simulation time 162951700 ps
CPU time 5.54 seconds
Started Jul 18 05:16:08 PM PDT 24
Finished Jul 18 05:16:15 PM PDT 24
Peak memory 217816 kb
Host smart-3702ab27-a7d5-45a2-8724-652df966460d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624037680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.624037680
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2209957230
Short name T650
Test name
Test status
Simulation time 50255174 ps
CPU time 2.36 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:16:18 PM PDT 24
Peak memory 217184 kb
Host smart-302bc64e-ce13-4ac9-a64c-0f13de7c1eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209957230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2209957230
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.4226648525
Short name T479
Test name
Test status
Simulation time 722654471 ps
CPU time 24.68 seconds
Started Jul 18 05:16:08 PM PDT 24
Finished Jul 18 05:16:35 PM PDT 24
Peak memory 250488 kb
Host smart-25049141-1a1e-4c08-9d5a-0ccf52780d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226648525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.4226648525
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1818622394
Short name T254
Test name
Test status
Simulation time 143362354 ps
CPU time 6.58 seconds
Started Jul 18 05:16:14 PM PDT 24
Finished Jul 18 05:16:24 PM PDT 24
Peak memory 249928 kb
Host smart-a8610601-3d20-4335-8642-adad33134651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818622394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1818622394
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.764484494
Short name T401
Test name
Test status
Simulation time 10118670198 ps
CPU time 118.83 seconds
Started Jul 18 05:16:12 PM PDT 24
Finished Jul 18 05:18:13 PM PDT 24
Peak memory 280872 kb
Host smart-94ae105f-34c6-4a13-8fdd-3a76e2483169
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764484494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.764484494
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2623428994
Short name T817
Test name
Test status
Simulation time 90946735 ps
CPU time 0.98 seconds
Started Jul 18 05:16:15 PM PDT 24
Finished Jul 18 05:16:20 PM PDT 24
Peak memory 208408 kb
Host smart-d517ae14-75a6-4043-b6bd-b965c6635a26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623428994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2623428994
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3308634154
Short name T392
Test name
Test status
Simulation time 479178566 ps
CPU time 21.05 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:16:36 PM PDT 24
Peak memory 217852 kb
Host smart-2db3d5e4-7202-40fc-a1b0-57f40dd9e8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308634154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3308634154
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3409622002
Short name T500
Test name
Test status
Simulation time 5324206393 ps
CPU time 20.62 seconds
Started Jul 18 05:16:11 PM PDT 24
Finished Jul 18 05:16:33 PM PDT 24
Peak memory 217276 kb
Host smart-b3b835fd-69f7-4c62-93a5-09f0328f323a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409622002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3409622002
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2959522827
Short name T337
Test name
Test status
Simulation time 60624647 ps
CPU time 3.62 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:16:19 PM PDT 24
Peak memory 217804 kb
Host smart-9670a43b-049e-43d0-be00-95e99abd2d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959522827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2959522827
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1789340223
Short name T855
Test name
Test status
Simulation time 1502338257 ps
CPU time 12.11 seconds
Started Jul 18 05:16:11 PM PDT 24
Finished Jul 18 05:16:25 PM PDT 24
Peak memory 219452 kb
Host smart-d15f3d87-0f77-4680-812a-1ab05aa6ff1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789340223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1789340223
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.82155574
Short name T555
Test name
Test status
Simulation time 1173927726 ps
CPU time 11.63 seconds
Started Jul 18 05:16:10 PM PDT 24
Finished Jul 18 05:16:23 PM PDT 24
Peak memory 225476 kb
Host smart-6b0b2d66-8d76-40f3-9e1b-33bbfdd9f8c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82155574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_dig
est.82155574
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2377182897
Short name T63
Test name
Test status
Simulation time 613373326 ps
CPU time 9.24 seconds
Started Jul 18 05:16:15 PM PDT 24
Finished Jul 18 05:16:27 PM PDT 24
Peak memory 217692 kb
Host smart-d4ed9b63-1345-40c8-8d74-e09bef6c715e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377182897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2377182897
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2499113427
Short name T631
Test name
Test status
Simulation time 343956146 ps
CPU time 12.82 seconds
Started Jul 18 05:16:11 PM PDT 24
Finished Jul 18 05:16:25 PM PDT 24
Peak memory 217864 kb
Host smart-29a496a9-ef14-47fb-a31f-3edae78b44bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499113427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2499113427
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2738932763
Short name T618
Test name
Test status
Simulation time 2253469390 ps
CPU time 3.86 seconds
Started Jul 18 05:16:15 PM PDT 24
Finished Jul 18 05:16:22 PM PDT 24
Peak memory 222708 kb
Host smart-f84edd1e-ece8-4333-aabd-545e16d0ae50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738932763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2738932763
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2383585613
Short name T111
Test name
Test status
Simulation time 2688216371 ps
CPU time 19.76 seconds
Started Jul 18 05:16:14 PM PDT 24
Finished Jul 18 05:16:37 PM PDT 24
Peak memory 250548 kb
Host smart-0987db86-7e37-4a3e-b758-67bbcda358e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383585613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2383585613
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.731429901
Short name T707
Test name
Test status
Simulation time 228232501 ps
CPU time 8.5 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:16:23 PM PDT 24
Peak memory 250468 kb
Host smart-32294d95-bfb9-4577-bff4-f76603ae0efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731429901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.731429901
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1779064749
Short name T104
Test name
Test status
Simulation time 33975453784 ps
CPU time 254.5 seconds
Started Jul 18 05:16:16 PM PDT 24
Finished Jul 18 05:20:33 PM PDT 24
Peak memory 421564 kb
Host smart-192dcadf-04c9-4d21-bbae-8c6aa29d63ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779064749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1779064749
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.3122622393
Short name T583
Test name
Test status
Simulation time 68806880240 ps
CPU time 561.54 seconds
Started Jul 18 05:16:10 PM PDT 24
Finished Jul 18 05:25:34 PM PDT 24
Peak memory 301244 kb
Host smart-441f057b-ae35-4521-be57-eb6e5c61c397
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3122622393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.3122622393
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.269915460
Short name T309
Test name
Test status
Simulation time 24044090 ps
CPU time 0.96 seconds
Started Jul 18 05:16:08 PM PDT 24
Finished Jul 18 05:16:10 PM PDT 24
Peak memory 211336 kb
Host smart-7cc21b2c-01cc-444b-bde3-79228eef856a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269915460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.269915460
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.4076091549
Short name T240
Test name
Test status
Simulation time 89953924 ps
CPU time 1.08 seconds
Started Jul 18 05:16:11 PM PDT 24
Finished Jul 18 05:16:14 PM PDT 24
Peak memory 208664 kb
Host smart-07f9efbd-d06c-46c2-a040-fb578ebbf466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076091549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.4076091549
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.4117091129
Short name T579
Test name
Test status
Simulation time 738229241 ps
CPU time 12.6 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:16:28 PM PDT 24
Peak memory 217808 kb
Host smart-53801faa-7249-4640-a709-7c57f4e2156b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117091129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.4117091129
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2548942900
Short name T862
Test name
Test status
Simulation time 224761923 ps
CPU time 1.9 seconds
Started Jul 18 05:16:14 PM PDT 24
Finished Jul 18 05:16:19 PM PDT 24
Peak memory 217772 kb
Host smart-352f000c-e553-4d82-9abd-8b5546bcf501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548942900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2548942900
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.434277679
Short name T418
Test name
Test status
Simulation time 1681873667 ps
CPU time 9.79 seconds
Started Jul 18 05:16:10 PM PDT 24
Finished Jul 18 05:16:21 PM PDT 24
Peak memory 217968 kb
Host smart-0fa24847-d61a-47d1-b7e8-d82d060bc7fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434277679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.434277679
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2875749431
Short name T286
Test name
Test status
Simulation time 424852953 ps
CPU time 14.04 seconds
Started Jul 18 05:16:14 PM PDT 24
Finished Jul 18 05:16:31 PM PDT 24
Peak memory 225500 kb
Host smart-5e09f52f-d348-4ad8-b814-b1edd0e4fa3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875749431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2875749431
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1890449448
Short name T866
Test name
Test status
Simulation time 283175851 ps
CPU time 11.13 seconds
Started Jul 18 05:16:19 PM PDT 24
Finished Jul 18 05:16:32 PM PDT 24
Peak memory 225308 kb
Host smart-eaa05d15-cc2c-4883-b251-bd16e16b6a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890449448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1890449448
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2440011661
Short name T72
Test name
Test status
Simulation time 64962848 ps
CPU time 3.95 seconds
Started Jul 18 05:16:16 PM PDT 24
Finished Jul 18 05:16:23 PM PDT 24
Peak memory 216960 kb
Host smart-d7fcedb3-327d-4db2-9786-92cf7bc907ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440011661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2440011661
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.18668991
Short name T357
Test name
Test status
Simulation time 604994896 ps
CPU time 31.17 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:16:46 PM PDT 24
Peak memory 246832 kb
Host smart-65c69bcc-e9dd-4e85-8c2d-69dd42fa832a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18668991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.18668991
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.1546947509
Short name T841
Test name
Test status
Simulation time 64483432 ps
CPU time 6.25 seconds
Started Jul 18 05:16:15 PM PDT 24
Finished Jul 18 05:16:24 PM PDT 24
Peak memory 246276 kb
Host smart-35db179f-1f54-4f98-90dc-2601a6a774ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546947509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1546947509
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3099230898
Short name T492
Test name
Test status
Simulation time 18204847134 ps
CPU time 117.19 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:18:13 PM PDT 24
Peak memory 250592 kb
Host smart-5c8317ac-f422-414b-b894-16d9cf8aa07b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099230898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3099230898
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.1723476981
Short name T467
Test name
Test status
Simulation time 13027020123 ps
CPU time 315.6 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:21:31 PM PDT 24
Peak memory 284640 kb
Host smart-d8265dc9-538e-4f87-87fd-2ef621f95f62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1723476981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.1723476981
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2987192363
Short name T89
Test name
Test status
Simulation time 53333692 ps
CPU time 0.89 seconds
Started Jul 18 05:16:11 PM PDT 24
Finished Jul 18 05:16:14 PM PDT 24
Peak memory 211340 kb
Host smart-0a8b0994-1cb0-477d-8706-e1bc7d43581b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987192363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2987192363
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.4110686977
Short name T315
Test name
Test status
Simulation time 71396235 ps
CPU time 0.96 seconds
Started Jul 18 05:16:16 PM PDT 24
Finished Jul 18 05:16:21 PM PDT 24
Peak memory 208384 kb
Host smart-9a29fb1c-7308-4b6d-8fc7-8efad7145d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110686977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.4110686977
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2853712674
Short name T2
Test name
Test status
Simulation time 669489781 ps
CPU time 17.02 seconds
Started Jul 18 05:16:14 PM PDT 24
Finished Jul 18 05:16:34 PM PDT 24
Peak memory 217876 kb
Host smart-f9428021-81c9-4d08-8e99-33d9a5f7f66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853712674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2853712674
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.4202636641
Short name T628
Test name
Test status
Simulation time 308036961 ps
CPU time 4.74 seconds
Started Jul 18 05:16:11 PM PDT 24
Finished Jul 18 05:16:17 PM PDT 24
Peak memory 216696 kb
Host smart-42dd7c83-8301-4ebf-bd42-de2ce20cb017
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202636641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.4202636641
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2909262684
Short name T556
Test name
Test status
Simulation time 69113740 ps
CPU time 3.62 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:16:20 PM PDT 24
Peak memory 222196 kb
Host smart-b398048b-7c97-44b7-af05-834b21b329bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909262684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2909262684
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.878764125
Short name T408
Test name
Test status
Simulation time 1128516145 ps
CPU time 17.9 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:16:34 PM PDT 24
Peak memory 225564 kb
Host smart-ae52553a-4d8d-4630-8869-84148206661d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878764125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.878764125
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2421820183
Short name T826
Test name
Test status
Simulation time 1876605261 ps
CPU time 12.48 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:16:29 PM PDT 24
Peak memory 225524 kb
Host smart-c578042f-8adb-4f2c-a8ff-08d54589c4d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421820183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2421820183
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.4265094747
Short name T42
Test name
Test status
Simulation time 680639535 ps
CPU time 8.99 seconds
Started Jul 18 05:16:17 PM PDT 24
Finished Jul 18 05:16:29 PM PDT 24
Peak memory 225472 kb
Host smart-e5f68bd3-27d5-4949-bb18-872f8e176fae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265094747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
4265094747
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2561559306
Short name T442
Test name
Test status
Simulation time 194242603 ps
CPU time 8.7 seconds
Started Jul 18 05:16:14 PM PDT 24
Finished Jul 18 05:16:25 PM PDT 24
Peak memory 217864 kb
Host smart-32109a99-8c7e-4930-a08d-9343d9509576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561559306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2561559306
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2995737537
Short name T539
Test name
Test status
Simulation time 107196940 ps
CPU time 3.78 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:16:20 PM PDT 24
Peak memory 217256 kb
Host smart-d6fa58d6-9e65-4d92-9b59-57a70205ae36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995737537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2995737537
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.939066134
Short name T803
Test name
Test status
Simulation time 441822374 ps
CPU time 27.42 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:16:43 PM PDT 24
Peak memory 250520 kb
Host smart-296fca0d-1a8f-4d85-9d1c-d58c27de0e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939066134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.939066134
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3756302840
Short name T687
Test name
Test status
Simulation time 873810500 ps
CPU time 6.25 seconds
Started Jul 18 05:16:16 PM PDT 24
Finished Jul 18 05:16:25 PM PDT 24
Peak memory 246576 kb
Host smart-5d28348a-6c60-4391-a2e1-7bbfe5db3917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756302840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3756302840
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1402963748
Short name T689
Test name
Test status
Simulation time 2201029986 ps
CPU time 10.17 seconds
Started Jul 18 05:16:19 PM PDT 24
Finished Jul 18 05:16:31 PM PDT 24
Peak memory 225628 kb
Host smart-e1a189bc-2271-43eb-8a17-61c4c4f06c64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402963748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1402963748
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.94994254
Short name T148
Test name
Test status
Simulation time 9908390196 ps
CPU time 344.92 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:22:01 PM PDT 24
Peak memory 279760 kb
Host smart-63b3f9c8-d8aa-44e1-9230-28be73c9db15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=94994254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.94994254
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2611603493
Short name T563
Test name
Test status
Simulation time 20786171 ps
CPU time 0.88 seconds
Started Jul 18 05:16:15 PM PDT 24
Finished Jul 18 05:16:19 PM PDT 24
Peak memory 208428 kb
Host smart-8aa9e0ed-aa7b-47e4-b5a4-ca486fd8d5a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611603493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2611603493
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3135465315
Short name T213
Test name
Test status
Simulation time 66483515 ps
CPU time 0.98 seconds
Started Jul 18 05:16:59 PM PDT 24
Finished Jul 18 05:17:01 PM PDT 24
Peak memory 208524 kb
Host smart-381ccbe0-9c47-475b-8a82-b97cd368332b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135465315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3135465315
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3595661815
Short name T165
Test name
Test status
Simulation time 656942774 ps
CPU time 15.61 seconds
Started Jul 18 05:16:19 PM PDT 24
Finished Jul 18 05:16:37 PM PDT 24
Peak memory 217840 kb
Host smart-5fc22d0b-e7aa-49fc-bd01-ee259f3d04de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595661815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3595661815
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.184583114
Short name T101
Test name
Test status
Simulation time 1448147160 ps
CPU time 15.69 seconds
Started Jul 18 05:16:33 PM PDT 24
Finished Jul 18 05:16:54 PM PDT 24
Peak memory 216804 kb
Host smart-bdc7a162-5f39-478e-929d-343282ccb266
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184583114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.184583114
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.314492260
Short name T377
Test name
Test status
Simulation time 64922924 ps
CPU time 3.03 seconds
Started Jul 18 05:16:18 PM PDT 24
Finished Jul 18 05:16:23 PM PDT 24
Peak memory 217768 kb
Host smart-bfbe0299-b086-4507-b3c9-4e4f27e5a783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314492260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.314492260
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1916915307
Short name T850
Test name
Test status
Simulation time 832382503 ps
CPU time 22.32 seconds
Started Jul 18 05:16:33 PM PDT 24
Finished Jul 18 05:17:01 PM PDT 24
Peak memory 225532 kb
Host smart-2a61f987-e884-4110-beb5-7ccaf0bda7b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916915307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1916915307
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2825252046
Short name T366
Test name
Test status
Simulation time 1370687380 ps
CPU time 13.51 seconds
Started Jul 18 05:16:33 PM PDT 24
Finished Jul 18 05:16:52 PM PDT 24
Peak memory 217756 kb
Host smart-4afe5428-3cdf-4eb3-b498-09b808517191
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825252046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2825252046
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1966906711
Short name T320
Test name
Test status
Simulation time 1583901731 ps
CPU time 9.98 seconds
Started Jul 18 05:16:32 PM PDT 24
Finished Jul 18 05:16:47 PM PDT 24
Peak memory 225504 kb
Host smart-fa3c7816-0eca-4232-a615-e373b02c06d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966906711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1966906711
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1988757428
Short name T158
Test name
Test status
Simulation time 1422947571 ps
CPU time 9.48 seconds
Started Jul 18 05:16:30 PM PDT 24
Finished Jul 18 05:16:44 PM PDT 24
Peak memory 224344 kb
Host smart-60e8bbda-48bf-46c2-ae3d-b0a6235dd328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988757428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1988757428
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2770441375
Short name T729
Test name
Test status
Simulation time 57470907 ps
CPU time 1.32 seconds
Started Jul 18 05:16:13 PM PDT 24
Finished Jul 18 05:16:18 PM PDT 24
Peak memory 217212 kb
Host smart-a7c0f8d8-a396-461c-a76d-622716565ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770441375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2770441375
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3861277408
Short name T404
Test name
Test status
Simulation time 1882290802 ps
CPU time 20.6 seconds
Started Jul 18 05:16:19 PM PDT 24
Finished Jul 18 05:16:42 PM PDT 24
Peak memory 250508 kb
Host smart-6545e91b-9e48-4157-922a-190c40c6ed70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861277408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3861277408
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2313776548
Short name T221
Test name
Test status
Simulation time 311612421 ps
CPU time 6.68 seconds
Started Jul 18 05:16:17 PM PDT 24
Finished Jul 18 05:16:26 PM PDT 24
Peak memory 247432 kb
Host smart-863b43b6-951b-4300-b00f-a92194899eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313776548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2313776548
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3987958367
Short name T262
Test name
Test status
Simulation time 991868280 ps
CPU time 50.27 seconds
Started Jul 18 05:16:39 PM PDT 24
Finished Jul 18 05:17:33 PM PDT 24
Peak memory 250504 kb
Host smart-b6213287-a3aa-42a1-8202-19d1970fcf76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987958367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3987958367
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.704835135
Short name T278
Test name
Test status
Simulation time 46649906 ps
CPU time 0.92 seconds
Started Jul 18 05:16:19 PM PDT 24
Finished Jul 18 05:16:22 PM PDT 24
Peak memory 211380 kb
Host smart-005501cb-ae42-46a7-9c9b-02d3b4490f14
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704835135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.704835135
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1627156645
Short name T624
Test name
Test status
Simulation time 168714511 ps
CPU time 1.42 seconds
Started Jul 18 05:16:34 PM PDT 24
Finished Jul 18 05:16:41 PM PDT 24
Peak memory 208384 kb
Host smart-97121af4-1ae3-492f-abba-1cdc37cbe19c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627156645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1627156645
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.427960192
Short name T798
Test name
Test status
Simulation time 1071728900 ps
CPU time 12.57 seconds
Started Jul 18 05:16:35 PM PDT 24
Finished Jul 18 05:16:53 PM PDT 24
Peak memory 217824 kb
Host smart-b8ef0e97-1930-4558-bc34-14b9c2a379b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427960192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.427960192
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1362513117
Short name T642
Test name
Test status
Simulation time 168669566 ps
CPU time 2.98 seconds
Started Jul 18 05:16:32 PM PDT 24
Finished Jul 18 05:16:40 PM PDT 24
Peak memory 216712 kb
Host smart-abb39e53-ef47-4cf7-ba85-1194d17faa80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362513117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1362513117
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.472595517
Short name T626
Test name
Test status
Simulation time 137820824 ps
CPU time 1.85 seconds
Started Jul 18 05:16:30 PM PDT 24
Finished Jul 18 05:16:34 PM PDT 24
Peak memory 217744 kb
Host smart-d7e79b3f-aad9-4d92-9fea-e0d7e8645960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472595517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.472595517
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3532695698
Short name T172
Test name
Test status
Simulation time 1889277723 ps
CPU time 13.25 seconds
Started Jul 18 05:16:32 PM PDT 24
Finished Jul 18 05:16:50 PM PDT 24
Peak memory 219460 kb
Host smart-a665240a-4cd7-4f2b-9e6d-62baee57a233
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532695698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3532695698
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.4067417934
Short name T214
Test name
Test status
Simulation time 1607993934 ps
CPU time 14.98 seconds
Started Jul 18 05:16:39 PM PDT 24
Finished Jul 18 05:16:58 PM PDT 24
Peak memory 225476 kb
Host smart-49ea03c3-d361-400d-937e-6f30c68d2695
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067417934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.4067417934
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.154824499
Short name T546
Test name
Test status
Simulation time 324839628 ps
CPU time 7.4 seconds
Started Jul 18 05:16:29 PM PDT 24
Finished Jul 18 05:16:37 PM PDT 24
Peak memory 225488 kb
Host smart-4fae3906-bce4-4330-b3a9-22a263e98de3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154824499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.154824499
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3821996416
Short name T765
Test name
Test status
Simulation time 2812621571 ps
CPU time 11.99 seconds
Started Jul 18 05:16:29 PM PDT 24
Finished Jul 18 05:16:42 PM PDT 24
Peak memory 217848 kb
Host smart-1eca4b8a-287a-469a-90c1-e093e37bc571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821996416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3821996416
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1295407904
Short name T578
Test name
Test status
Simulation time 21294529 ps
CPU time 1.86 seconds
Started Jul 18 05:16:30 PM PDT 24
Finished Jul 18 05:16:36 PM PDT 24
Peak memory 213504 kb
Host smart-3f83484b-ce68-4d97-a2ba-3e403541e5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295407904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1295407904
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1974190697
Short name T723
Test name
Test status
Simulation time 272629357 ps
CPU time 33.1 seconds
Started Jul 18 05:16:28 PM PDT 24
Finished Jul 18 05:17:03 PM PDT 24
Peak memory 250556 kb
Host smart-ae0bb037-c6e7-4b87-bcc8-8d4b2a1d5c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974190697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1974190697
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.277352139
Short name T736
Test name
Test status
Simulation time 82251167 ps
CPU time 6.23 seconds
Started Jul 18 05:16:33 PM PDT 24
Finished Jul 18 05:16:45 PM PDT 24
Peak memory 246352 kb
Host smart-613547f3-a1d2-4454-96c0-91dce24a03ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277352139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.277352139
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1164882967
Short name T595
Test name
Test status
Simulation time 32320377143 ps
CPU time 277.65 seconds
Started Jul 18 05:16:31 PM PDT 24
Finished Jul 18 05:21:12 PM PDT 24
Peak memory 446972 kb
Host smart-0cb525a8-3363-46c1-8c92-39d2085e32ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164882967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1164882967
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3461866196
Short name T814
Test name
Test status
Simulation time 33596351 ps
CPU time 0.85 seconds
Started Jul 18 05:16:31 PM PDT 24
Finished Jul 18 05:16:36 PM PDT 24
Peak memory 211352 kb
Host smart-8a8e5440-1c2e-4516-aa8a-7575f2e76205
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461866196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3461866196
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3821807406
Short name T677
Test name
Test status
Simulation time 90398601 ps
CPU time 1.24 seconds
Started Jul 18 05:16:31 PM PDT 24
Finished Jul 18 05:16:36 PM PDT 24
Peak memory 208516 kb
Host smart-6f2bfe4e-97df-4902-a5c9-5fb4620ca6f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821807406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3821807406
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2623632096
Short name T720
Test name
Test status
Simulation time 440159206 ps
CPU time 9.72 seconds
Started Jul 18 05:16:33 PM PDT 24
Finished Jul 18 05:16:49 PM PDT 24
Peak memory 217708 kb
Host smart-ca7868fe-0189-4b8a-a999-1741409f9b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623632096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2623632096
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.427734519
Short name T443
Test name
Test status
Simulation time 813279450 ps
CPU time 2.6 seconds
Started Jul 18 05:16:31 PM PDT 24
Finished Jul 18 05:16:38 PM PDT 24
Peak memory 216560 kb
Host smart-fc770255-686e-4d5f-9274-a46126586925
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427734519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.427734519
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3325956218
Short name T154
Test name
Test status
Simulation time 201250586 ps
CPU time 2.9 seconds
Started Jul 18 05:16:29 PM PDT 24
Finished Jul 18 05:16:34 PM PDT 24
Peak memory 217796 kb
Host smart-0716cd16-78cf-484e-a71c-e08565a569d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325956218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3325956218
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.4059260290
Short name T706
Test name
Test status
Simulation time 1802093831 ps
CPU time 17.61 seconds
Started Jul 18 05:16:30 PM PDT 24
Finished Jul 18 05:16:51 PM PDT 24
Peak memory 218420 kb
Host smart-880b907c-164e-459a-a700-8c03f5d6cde1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059260290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.4059260290
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1846470572
Short name T174
Test name
Test status
Simulation time 1467738875 ps
CPU time 16.12 seconds
Started Jul 18 05:16:35 PM PDT 24
Finished Jul 18 05:16:57 PM PDT 24
Peak memory 217792 kb
Host smart-5268285d-75b3-42bb-8cc9-330cd2805d59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846470572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1846470572
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.4195224296
Short name T255
Test name
Test status
Simulation time 1039666203 ps
CPU time 7.09 seconds
Started Jul 18 05:16:30 PM PDT 24
Finished Jul 18 05:16:41 PM PDT 24
Peak memory 225504 kb
Host smart-48cc230f-22b5-49b8-b87f-13a159c23861
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195224296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
4195224296
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.4177803497
Short name T65
Test name
Test status
Simulation time 577412744 ps
CPU time 13.87 seconds
Started Jul 18 05:16:30 PM PDT 24
Finished Jul 18 05:16:48 PM PDT 24
Peak memory 217868 kb
Host smart-02b1823b-e47e-4544-ae59-70f4d5dc33d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177803497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.4177803497
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3464898639
Short name T701
Test name
Test status
Simulation time 27180069 ps
CPU time 1.34 seconds
Started Jul 18 05:16:34 PM PDT 24
Finished Jul 18 05:16:41 PM PDT 24
Peak memory 217192 kb
Host smart-670243df-5ed8-483a-ba0a-e7144bd84fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464898639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3464898639
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1150259847
Short name T412
Test name
Test status
Simulation time 735394039 ps
CPU time 30.89 seconds
Started Jul 18 05:16:31 PM PDT 24
Finished Jul 18 05:17:06 PM PDT 24
Peak memory 250524 kb
Host smart-a02f3c1b-9475-40df-ae42-ec846ef8ce1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150259847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1150259847
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3509534557
Short name T775
Test name
Test status
Simulation time 89185966 ps
CPU time 4.56 seconds
Started Jul 18 05:16:31 PM PDT 24
Finished Jul 18 05:16:39 PM PDT 24
Peak memory 221852 kb
Host smart-4e3e2174-078d-4a02-ad4d-e671255dd76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509534557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3509534557
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3399533454
Short name T458
Test name
Test status
Simulation time 122434245398 ps
CPU time 965.73 seconds
Started Jul 18 05:16:34 PM PDT 24
Finished Jul 18 05:32:45 PM PDT 24
Peak memory 282684 kb
Host smart-1e3fd45f-0403-4e4b-99c9-e4ac9c5bd82d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399533454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3399533454
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.2160738956
Short name T571
Test name
Test status
Simulation time 34494259259 ps
CPU time 228.74 seconds
Started Jul 18 05:16:35 PM PDT 24
Finished Jul 18 05:20:29 PM PDT 24
Peak memory 275712 kb
Host smart-ce163db9-0f7d-4177-ab5c-01d91498b782
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2160738956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.2160738956
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1415221846
Short name T37
Test name
Test status
Simulation time 14829333 ps
CPU time 1.02 seconds
Started Jul 18 05:16:30 PM PDT 24
Finished Jul 18 05:16:34 PM PDT 24
Peak memory 208456 kb
Host smart-1eb7491d-622d-4363-8684-5b41cd124757
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415221846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1415221846
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3022061523
Short name T241
Test name
Test status
Simulation time 55807278 ps
CPU time 0.92 seconds
Started Jul 18 05:13:21 PM PDT 24
Finished Jul 18 05:13:24 PM PDT 24
Peak memory 208416 kb
Host smart-74391306-04b6-4428-aa94-fffa2dd486cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022061523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3022061523
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2098127678
Short name T609
Test name
Test status
Simulation time 26078643 ps
CPU time 0.8 seconds
Started Jul 18 05:13:10 PM PDT 24
Finished Jul 18 05:13:15 PM PDT 24
Peak memory 208696 kb
Host smart-e292b27b-d818-48fa-be8c-ba2f5647adc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098127678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2098127678
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.158494885
Short name T610
Test name
Test status
Simulation time 1643849092 ps
CPU time 14.85 seconds
Started Jul 18 05:13:11 PM PDT 24
Finished Jul 18 05:13:30 PM PDT 24
Peak memory 217988 kb
Host smart-73e47065-2f98-4006-a282-e157ef83fb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158494885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.158494885
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2839021267
Short name T763
Test name
Test status
Simulation time 1833671082 ps
CPU time 15.41 seconds
Started Jul 18 05:13:12 PM PDT 24
Finished Jul 18 05:13:31 PM PDT 24
Peak memory 216816 kb
Host smart-537a570d-9032-4e58-aff7-d423ff3d857a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839021267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2839021267
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1482572161
Short name T621
Test name
Test status
Simulation time 5284697467 ps
CPU time 27.36 seconds
Started Jul 18 05:13:12 PM PDT 24
Finished Jul 18 05:13:43 PM PDT 24
Peak memory 225532 kb
Host smart-fc24b27d-d2ae-45dd-8d35-0f6bae82705f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482572161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1482572161
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1934591121
Short name T824
Test name
Test status
Simulation time 279342724 ps
CPU time 4.18 seconds
Started Jul 18 05:13:06 PM PDT 24
Finished Jul 18 05:13:14 PM PDT 24
Peak memory 217216 kb
Host smart-b53316fb-9c19-4c38-9117-28d03db946a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934591121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
934591121
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3618741875
Short name T586
Test name
Test status
Simulation time 1213253380 ps
CPU time 6.26 seconds
Started Jul 18 05:13:05 PM PDT 24
Finished Jul 18 05:13:15 PM PDT 24
Peak memory 221308 kb
Host smart-a784fec0-948b-4fac-8a5e-4966824b78b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618741875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3618741875
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2538990540
Short name T688
Test name
Test status
Simulation time 1326905995 ps
CPU time 20.72 seconds
Started Jul 18 05:13:08 PM PDT 24
Finished Jul 18 05:13:32 PM PDT 24
Peak memory 217136 kb
Host smart-cad0f2ce-ef4b-42e5-812f-39214b90a9f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538990540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2538990540
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3924857040
Short name T495
Test name
Test status
Simulation time 758008160 ps
CPU time 3.32 seconds
Started Jul 18 05:13:06 PM PDT 24
Finished Jul 18 05:13:13 PM PDT 24
Peak memory 217080 kb
Host smart-988c5501-ca7f-42ec-9f7b-871217770bff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924857040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3924857040
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.833438403
Short name T450
Test name
Test status
Simulation time 3470726246 ps
CPU time 52.39 seconds
Started Jul 18 05:13:05 PM PDT 24
Finished Jul 18 05:14:01 PM PDT 24
Peak memory 275108 kb
Host smart-70930e02-83b9-4dc0-8ea0-5bfd7b5891d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833438403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_state_failure.833438403
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3211094950
Short name T277
Test name
Test status
Simulation time 403393000 ps
CPU time 8.91 seconds
Started Jul 18 05:13:12 PM PDT 24
Finished Jul 18 05:13:25 PM PDT 24
Peak memory 222672 kb
Host smart-e4386489-2a41-4f4a-80bd-4aba20d1b1be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211094950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3211094950
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1976871624
Short name T516
Test name
Test status
Simulation time 30618238 ps
CPU time 2.18 seconds
Started Jul 18 05:13:12 PM PDT 24
Finished Jul 18 05:13:18 PM PDT 24
Peak memory 217748 kb
Host smart-71cca5a6-0d31-406b-bbe3-d8a6ef222dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976871624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1976871624
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1888586763
Short name T396
Test name
Test status
Simulation time 1147633956 ps
CPU time 7.35 seconds
Started Jul 18 05:13:11 PM PDT 24
Finished Jul 18 05:13:22 PM PDT 24
Peak memory 214308 kb
Host smart-534ae86e-43a5-4e1c-bcc8-7878f52f2c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888586763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1888586763
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2694743825
Short name T570
Test name
Test status
Simulation time 293718318 ps
CPU time 14.13 seconds
Started Jul 18 05:13:11 PM PDT 24
Finished Jul 18 05:13:29 PM PDT 24
Peak memory 218592 kb
Host smart-faee91d7-071b-49e8-ac65-2fd8aa2a2388
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694743825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2694743825
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2152870612
Short name T49
Test name
Test status
Simulation time 2299939104 ps
CPU time 16.38 seconds
Started Jul 18 05:13:05 PM PDT 24
Finished Jul 18 05:13:22 PM PDT 24
Peak memory 217792 kb
Host smart-95b91887-d9a7-4ad5-bfa7-3f726416880c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152870612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2152870612
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2313663782
Short name T517
Test name
Test status
Simulation time 1069727313 ps
CPU time 7.87 seconds
Started Jul 18 05:13:06 PM PDT 24
Finished Jul 18 05:13:18 PM PDT 24
Peak memory 225544 kb
Host smart-65225581-40dd-4f2c-a9b6-3d47d462808d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313663782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
313663782
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.723930832
Short name T852
Test name
Test status
Simulation time 325056288 ps
CPU time 12.68 seconds
Started Jul 18 05:13:09 PM PDT 24
Finished Jul 18 05:13:26 PM PDT 24
Peak memory 218028 kb
Host smart-3fabdbfd-8ad3-4f81-aab9-d44a8f9ffbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723930832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.723930832
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2231928806
Short name T695
Test name
Test status
Simulation time 85931308 ps
CPU time 6.1 seconds
Started Jul 18 05:13:09 PM PDT 24
Finished Jul 18 05:13:19 PM PDT 24
Peak memory 217188 kb
Host smart-d8f4ae82-e26b-488d-a18b-2643c7844f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231928806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2231928806
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.4111903679
Short name T372
Test name
Test status
Simulation time 1793399300 ps
CPU time 25.75 seconds
Started Jul 18 05:13:09 PM PDT 24
Finished Jul 18 05:13:39 PM PDT 24
Peak memory 250504 kb
Host smart-f3d95b52-c563-4b58-9648-d28b1a3b52e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111903679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.4111903679
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2275008842
Short name T351
Test name
Test status
Simulation time 321404925 ps
CPU time 6.66 seconds
Started Jul 18 05:13:11 PM PDT 24
Finished Jul 18 05:13:22 PM PDT 24
Peak memory 249988 kb
Host smart-ffc53454-0799-4d9f-a753-2d44160b591e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275008842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2275008842
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2281889159
Short name T327
Test name
Test status
Simulation time 24631385307 ps
CPU time 134.79 seconds
Started Jul 18 05:13:05 PM PDT 24
Finished Jul 18 05:15:21 PM PDT 24
Peak memory 404352 kb
Host smart-1e46c437-4423-4cd2-8a08-59650f1d988d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281889159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2281889159
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3179046901
Short name T774
Test name
Test status
Simulation time 14891110255 ps
CPU time 155.74 seconds
Started Jul 18 05:13:06 PM PDT 24
Finished Jul 18 05:15:44 PM PDT 24
Peak memory 283512 kb
Host smart-37728401-1477-41e7-9415-121573218feb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3179046901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.3179046901
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3538101674
Short name T833
Test name
Test status
Simulation time 146099777 ps
CPU time 0.91 seconds
Started Jul 18 05:13:12 PM PDT 24
Finished Jul 18 05:13:16 PM PDT 24
Peak memory 208616 kb
Host smart-c2b84fc4-33c0-4124-b2b5-f5968df43730
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538101674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3538101674
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.120286792
Short name T657
Test name
Test status
Simulation time 22515433 ps
CPU time 1.26 seconds
Started Jul 18 05:13:20 PM PDT 24
Finished Jul 18 05:13:22 PM PDT 24
Peak memory 208460 kb
Host smart-a0bc8803-7a90-40ed-b92b-77ee9a7b9c4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120286792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.120286792
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.692516233
Short name T423
Test name
Test status
Simulation time 11398205 ps
CPU time 0.82 seconds
Started Jul 18 05:13:21 PM PDT 24
Finished Jul 18 05:13:24 PM PDT 24
Peak memory 208348 kb
Host smart-97fddb14-5003-4637-9c02-dc2dc9c692ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692516233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.692516233
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3624813768
Short name T375
Test name
Test status
Simulation time 211433415 ps
CPU time 8.24 seconds
Started Jul 18 05:13:22 PM PDT 24
Finished Jul 18 05:13:33 PM PDT 24
Peak memory 217692 kb
Host smart-76c27336-7cdf-48db-a8b2-a84bbea7e2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624813768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3624813768
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2293333547
Short name T28
Test name
Test status
Simulation time 6513299888 ps
CPU time 13.97 seconds
Started Jul 18 05:13:28 PM PDT 24
Finished Jul 18 05:13:47 PM PDT 24
Peak memory 217216 kb
Host smart-7bff20b5-dc8c-45ca-bbc2-85b30f9ef100
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293333547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2293333547
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3502676624
Short name T740
Test name
Test status
Simulation time 5332614627 ps
CPU time 23.39 seconds
Started Jul 18 05:13:23 PM PDT 24
Finished Jul 18 05:13:49 PM PDT 24
Peak memory 218240 kb
Host smart-1ac2b794-d39d-4410-8244-9b8500294a99
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502676624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3502676624
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3596003811
Short name T674
Test name
Test status
Simulation time 14943804574 ps
CPU time 12.82 seconds
Started Jul 18 05:13:24 PM PDT 24
Finished Jul 18 05:13:40 PM PDT 24
Peak memory 217292 kb
Host smart-9b86458a-ccac-47ae-9f14-6461d9cef824
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596003811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3
596003811
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3440996935
Short name T592
Test name
Test status
Simulation time 769222659 ps
CPU time 8.73 seconds
Started Jul 18 05:13:25 PM PDT 24
Finished Jul 18 05:13:37 PM PDT 24
Peak memory 222700 kb
Host smart-b3ecd557-29fd-464d-b2c4-84812dda3608
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440996935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3440996935
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2552094262
Short name T741
Test name
Test status
Simulation time 1214882296 ps
CPU time 36.97 seconds
Started Jul 18 05:13:28 PM PDT 24
Finished Jul 18 05:14:10 PM PDT 24
Peak memory 217152 kb
Host smart-37a0d738-7476-4f9c-b455-ee5bd21ccd1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552094262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2552094262
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2730710574
Short name T562
Test name
Test status
Simulation time 206038270 ps
CPU time 4.34 seconds
Started Jul 18 05:13:21 PM PDT 24
Finished Jul 18 05:13:28 PM PDT 24
Peak memory 217124 kb
Host smart-f3665953-2a18-46c8-82a5-079dc13ddcaf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730710574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2730710574
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.386363393
Short name T566
Test name
Test status
Simulation time 10317130059 ps
CPU time 59.57 seconds
Started Jul 18 05:13:25 PM PDT 24
Finished Jul 18 05:14:29 PM PDT 24
Peak memory 267956 kb
Host smart-90896a3c-41c0-4688-8f25-5385d86b0c94
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386363393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.386363393
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.210115440
Short name T515
Test name
Test status
Simulation time 1429778529 ps
CPU time 15.33 seconds
Started Jul 18 05:13:24 PM PDT 24
Finished Jul 18 05:13:43 PM PDT 24
Peak memory 246744 kb
Host smart-886873b0-009c-403b-afef-a886eba2273e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210115440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.210115440
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3588718994
Short name T407
Test name
Test status
Simulation time 182428622 ps
CPU time 2.23 seconds
Started Jul 18 05:13:26 PM PDT 24
Finished Jul 18 05:13:32 PM PDT 24
Peak memory 217764 kb
Host smart-a1b6403c-3151-4ff9-94c2-376962e2ae4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588718994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3588718994
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3475764977
Short name T181
Test name
Test status
Simulation time 365455294 ps
CPU time 19.66 seconds
Started Jul 18 05:13:20 PM PDT 24
Finished Jul 18 05:13:41 PM PDT 24
Peak memory 225400 kb
Host smart-3c38f415-f8dd-412f-985a-57c81509b927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475764977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3475764977
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.2430615255
Short name T417
Test name
Test status
Simulation time 594657521 ps
CPU time 17.17 seconds
Started Jul 18 05:13:28 PM PDT 24
Finished Jul 18 05:13:50 PM PDT 24
Peak memory 218560 kb
Host smart-13b64baa-f581-45a6-aefd-7a9673684d59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430615255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2430615255
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.4003464870
Short name T12
Test name
Test status
Simulation time 1737810092 ps
CPU time 7.35 seconds
Started Jul 18 05:13:21 PM PDT 24
Finished Jul 18 05:13:30 PM PDT 24
Peak memory 217732 kb
Host smart-53838496-9337-47f9-9f93-6fadc1be9794
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003464870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.4003464870
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3927394828
Short name T770
Test name
Test status
Simulation time 980743316 ps
CPU time 6.77 seconds
Started Jul 18 05:13:29 PM PDT 24
Finished Jul 18 05:13:41 PM PDT 24
Peak memory 224960 kb
Host smart-9dbb0f89-8202-4eca-9bd8-362011066183
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927394828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
927394828
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1209065545
Short name T347
Test name
Test status
Simulation time 230576740 ps
CPU time 6.84 seconds
Started Jul 18 05:13:19 PM PDT 24
Finished Jul 18 05:13:27 PM PDT 24
Peak memory 217800 kb
Host smart-39030460-effb-4d36-9c26-7898573ba210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209065545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1209065545
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1509534097
Short name T395
Test name
Test status
Simulation time 50203440 ps
CPU time 1.12 seconds
Started Jul 18 05:13:22 PM PDT 24
Finished Jul 18 05:13:26 PM PDT 24
Peak memory 217208 kb
Host smart-7439e7e4-68c2-4370-ad5b-36be8ecbe032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509534097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1509534097
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2803739668
Short name T291
Test name
Test status
Simulation time 340236525 ps
CPU time 26.1 seconds
Started Jul 18 05:13:29 PM PDT 24
Finished Jul 18 05:14:00 PM PDT 24
Peak memory 250516 kb
Host smart-0dd17f94-15ba-48cc-ad15-09b9a3c5c2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803739668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2803739668
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2385071324
Short name T92
Test name
Test status
Simulation time 755223426 ps
CPU time 9.21 seconds
Started Jul 18 05:13:21 PM PDT 24
Finished Jul 18 05:13:32 PM PDT 24
Peak memory 250512 kb
Host smart-ec3ddba8-fe24-4405-852d-0c89a38eef62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385071324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2385071324
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2292237428
Short name T294
Test name
Test status
Simulation time 8574305157 ps
CPU time 78.2 seconds
Started Jul 18 05:13:21 PM PDT 24
Finished Jul 18 05:14:42 PM PDT 24
Peak memory 268500 kb
Host smart-72488782-e5bb-490f-a161-594ffc78f1f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292237428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2292237428
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2874694365
Short name T468
Test name
Test status
Simulation time 31351408 ps
CPU time 0.95 seconds
Started Jul 18 05:13:22 PM PDT 24
Finished Jul 18 05:13:26 PM PDT 24
Peak memory 211328 kb
Host smart-95de91eb-e8e7-4786-a5f7-faf66e9d6d4b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874694365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2874694365
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.4238894855
Short name T79
Test name
Test status
Simulation time 62137383 ps
CPU time 0.93 seconds
Started Jul 18 05:13:26 PM PDT 24
Finished Jul 18 05:13:30 PM PDT 24
Peak memory 208380 kb
Host smart-5161238e-a894-4e9a-ae7b-6aa67735621a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238894855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.4238894855
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2401479015
Short name T77
Test name
Test status
Simulation time 14072129 ps
CPU time 0.85 seconds
Started Jul 18 05:13:23 PM PDT 24
Finished Jul 18 05:13:27 PM PDT 24
Peak memory 208340 kb
Host smart-eb2ceebc-4e79-4c2f-ba86-37836d65da9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401479015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2401479015
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1478946222
Short name T388
Test name
Test status
Simulation time 308667476 ps
CPU time 11.95 seconds
Started Jul 18 05:13:21 PM PDT 24
Finished Jul 18 05:13:36 PM PDT 24
Peak memory 217856 kb
Host smart-aa4e508e-3352-466f-90c3-61cb6d270ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478946222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1478946222
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3533098806
Short name T34
Test name
Test status
Simulation time 1298174409 ps
CPU time 5.39 seconds
Started Jul 18 05:13:22 PM PDT 24
Finished Jul 18 05:13:30 PM PDT 24
Peak memory 216684 kb
Host smart-f6f8c923-020f-40f9-bcf1-35c0b1242a74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533098806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3533098806
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1135187028
Short name T22
Test name
Test status
Simulation time 1982443400 ps
CPU time 56.04 seconds
Started Jul 18 05:13:22 PM PDT 24
Finished Jul 18 05:14:21 PM PDT 24
Peak memory 218308 kb
Host smart-d23bbf45-744e-407a-8f8f-b9f8e21fe8cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135187028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1135187028
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1600357669
Short name T523
Test name
Test status
Simulation time 1276229838 ps
CPU time 7.14 seconds
Started Jul 18 05:13:22 PM PDT 24
Finished Jul 18 05:13:32 PM PDT 24
Peak memory 217256 kb
Host smart-b1bc3d37-9c98-4f96-923e-246550821254
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600357669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
600357669
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1016675289
Short name T619
Test name
Test status
Simulation time 226564041 ps
CPU time 7.51 seconds
Started Jul 18 05:13:25 PM PDT 24
Finished Jul 18 05:13:37 PM PDT 24
Peak memory 222764 kb
Host smart-21c8518c-2073-42be-8b64-3f86857fd488
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016675289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1016675289
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.802147299
Short name T506
Test name
Test status
Simulation time 890162618 ps
CPU time 12.59 seconds
Started Jul 18 05:13:28 PM PDT 24
Finished Jul 18 05:13:46 PM PDT 24
Peak memory 217200 kb
Host smart-74a144cb-6b03-46d7-b30f-34f8ec10d3c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802147299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.802147299
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3179001465
Short name T779
Test name
Test status
Simulation time 307710240 ps
CPU time 2 seconds
Started Jul 18 05:13:25 PM PDT 24
Finished Jul 18 05:13:31 PM PDT 24
Peak memory 217224 kb
Host smart-8d9a5e51-000a-4f8b-9b9d-7ce04c46d942
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179001465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3179001465
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2867043291
Short name T651
Test name
Test status
Simulation time 1801991969 ps
CPU time 36.41 seconds
Started Jul 18 05:13:25 PM PDT 24
Finished Jul 18 05:14:06 PM PDT 24
Peak memory 250484 kb
Host smart-76a2da73-1943-467f-b939-d04944113c95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867043291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2867043291
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3528150442
Short name T4
Test name
Test status
Simulation time 3424801266 ps
CPU time 17.6 seconds
Started Jul 18 05:13:24 PM PDT 24
Finished Jul 18 05:13:45 PM PDT 24
Peak memory 223232 kb
Host smart-15f3a3b0-4018-4a97-be93-608cb3d539d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528150442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3528150442
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1452590253
Short name T215
Test name
Test status
Simulation time 115910286 ps
CPU time 3.29 seconds
Started Jul 18 05:13:27 PM PDT 24
Finished Jul 18 05:13:36 PM PDT 24
Peak memory 217796 kb
Host smart-0c2b450b-115b-4da0-ab77-3351d1f9e44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452590253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1452590253
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2091217130
Short name T630
Test name
Test status
Simulation time 754524110 ps
CPU time 10.22 seconds
Started Jul 18 05:13:25 PM PDT 24
Finished Jul 18 05:13:39 PM PDT 24
Peak memory 217184 kb
Host smart-6fb6475f-ca31-4518-afa9-33f062e53072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091217130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2091217130
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2229574978
Short name T550
Test name
Test status
Simulation time 778227255 ps
CPU time 12.51 seconds
Started Jul 18 05:13:29 PM PDT 24
Finished Jul 18 05:13:46 PM PDT 24
Peak memory 218140 kb
Host smart-00b6df0b-9c5a-48d8-8856-0a266104278a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229574978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2229574978
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2222171706
Short name T584
Test name
Test status
Simulation time 171059867 ps
CPU time 8.9 seconds
Started Jul 18 05:13:26 PM PDT 24
Finished Jul 18 05:13:39 PM PDT 24
Peak memory 225496 kb
Host smart-632e95e1-9485-4890-959b-ff59351e4d8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222171706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2222171706
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1401538352
Short name T319
Test name
Test status
Simulation time 3518636482 ps
CPU time 6.95 seconds
Started Jul 18 05:13:21 PM PDT 24
Finished Jul 18 05:13:31 PM PDT 24
Peak memory 225560 kb
Host smart-50b8bd48-2557-49a7-a9bb-89c675d3b8d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401538352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
401538352
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3232144454
Short name T868
Test name
Test status
Simulation time 273649292 ps
CPU time 9.45 seconds
Started Jul 18 05:13:21 PM PDT 24
Finished Jul 18 05:13:33 PM PDT 24
Peak memory 217824 kb
Host smart-ff188311-cd8b-4507-9359-ba52254d5388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232144454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3232144454
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1768183539
Short name T74
Test name
Test status
Simulation time 157296495 ps
CPU time 2.76 seconds
Started Jul 18 05:13:20 PM PDT 24
Finished Jul 18 05:13:25 PM PDT 24
Peak memory 217208 kb
Host smart-e03fdf81-a8f9-44a0-bf70-85020d685c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768183539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1768183539
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1098228364
Short name T17
Test name
Test status
Simulation time 593561101 ps
CPU time 25.22 seconds
Started Jul 18 05:14:00 PM PDT 24
Finished Jul 18 05:14:26 PM PDT 24
Peak memory 250472 kb
Host smart-8d7bf83c-a1de-4f45-966a-f834c62b3db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098228364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1098228364
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1487161929
Short name T382
Test name
Test status
Simulation time 85990180 ps
CPU time 3.11 seconds
Started Jul 18 05:13:22 PM PDT 24
Finished Jul 18 05:13:28 PM PDT 24
Peak memory 222124 kb
Host smart-2c57d30c-474a-4d13-9536-cadd05b2a4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487161929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1487161929
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1425705701
Short name T656
Test name
Test status
Simulation time 22798863910 ps
CPU time 174.82 seconds
Started Jul 18 05:13:28 PM PDT 24
Finished Jul 18 05:16:27 PM PDT 24
Peak memory 250468 kb
Host smart-fa6377fc-dd69-437f-8160-bb6d39bd4aeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425705701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1425705701
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1774905099
Short name T632
Test name
Test status
Simulation time 57429624 ps
CPU time 1.09 seconds
Started Jul 18 05:13:24 PM PDT 24
Finished Jul 18 05:13:28 PM PDT 24
Peak memory 211468 kb
Host smart-70abf988-38de-42c7-8b80-a60ea8f6914a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774905099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1774905099
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.804140788
Short name T258
Test name
Test status
Simulation time 441476112 ps
CPU time 11.76 seconds
Started Jul 18 05:13:19 PM PDT 24
Finished Jul 18 05:13:33 PM PDT 24
Peak memory 217772 kb
Host smart-b79b9cb0-65aa-496e-90c4-f01615ccee8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804140788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.804140788
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.694283393
Short name T100
Test name
Test status
Simulation time 683704183 ps
CPU time 15.94 seconds
Started Jul 18 05:13:26 PM PDT 24
Finished Jul 18 05:13:45 PM PDT 24
Peak memory 216580 kb
Host smart-b834f987-c281-4871-bc8c-7c0a368ef1ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694283393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.694283393
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1857409473
Short name T21
Test name
Test status
Simulation time 6613204753 ps
CPU time 46.92 seconds
Started Jul 18 05:13:24 PM PDT 24
Finished Jul 18 05:14:14 PM PDT 24
Peak memory 217752 kb
Host smart-de997c61-a1f4-4c8a-8a52-6c45062cd2e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857409473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1857409473
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.3621267205
Short name T381
Test name
Test status
Simulation time 140427201 ps
CPU time 4.22 seconds
Started Jul 18 05:13:30 PM PDT 24
Finished Jul 18 05:13:38 PM PDT 24
Peak memory 217244 kb
Host smart-89e178b4-b0e0-40d0-abef-a922baf1441c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621267205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.3
621267205
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2760998783
Short name T41
Test name
Test status
Simulation time 1642712313 ps
CPU time 8.13 seconds
Started Jul 18 05:13:24 PM PDT 24
Finished Jul 18 05:13:36 PM PDT 24
Peak memory 223904 kb
Host smart-f80f523b-c826-40b6-bddb-ae621d3d2414
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760998783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2760998783
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3373914023
Short name T663
Test name
Test status
Simulation time 2591062902 ps
CPU time 23.77 seconds
Started Jul 18 05:13:31 PM PDT 24
Finished Jul 18 05:13:58 PM PDT 24
Peak memory 217164 kb
Host smart-ba20da73-f3ee-415f-8e66-24dca0158278
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373914023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3373914023
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2965993997
Short name T387
Test name
Test status
Simulation time 94573785 ps
CPU time 3.78 seconds
Started Jul 18 05:13:28 PM PDT 24
Finished Jul 18 05:13:36 PM PDT 24
Peak memory 217148 kb
Host smart-960d4ff8-34d4-4f91-94c0-dcd27f18e8ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965993997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2965993997
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2691308391
Short name T242
Test name
Test status
Simulation time 12337339756 ps
CPU time 60.62 seconds
Started Jul 18 05:13:28 PM PDT 24
Finished Jul 18 05:14:34 PM PDT 24
Peak memory 279220 kb
Host smart-38be53ee-ee36-4d8c-8517-1a8a1497678f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691308391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2691308391
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3093232675
Short name T24
Test name
Test status
Simulation time 913584064 ps
CPU time 13.01 seconds
Started Jul 18 05:13:30 PM PDT 24
Finished Jul 18 05:13:47 PM PDT 24
Peak memory 250580 kb
Host smart-6af539ab-6fcc-4975-9e7f-2fc312c3b1b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093232675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3093232675
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3945144019
Short name T378
Test name
Test status
Simulation time 267608111 ps
CPU time 3.62 seconds
Started Jul 18 05:13:26 PM PDT 24
Finished Jul 18 05:13:33 PM PDT 24
Peak memory 217792 kb
Host smart-cbaa8398-77a4-4426-ada5-8a48e0c38d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945144019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3945144019
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.4184222414
Short name T180
Test name
Test status
Simulation time 973401778 ps
CPU time 6.84 seconds
Started Jul 18 05:13:50 PM PDT 24
Finished Jul 18 05:13:59 PM PDT 24
Peak memory 213508 kb
Host smart-c33284d0-39b7-4dca-b5f4-1f8395e4a269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184222414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.4184222414
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.984478037
Short name T223
Test name
Test status
Simulation time 530367754 ps
CPU time 9.25 seconds
Started Jul 18 05:13:30 PM PDT 24
Finished Jul 18 05:13:43 PM PDT 24
Peak memory 225584 kb
Host smart-1c73844d-9142-49d3-a4e5-daefc675987a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984478037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.984478037
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3378318358
Short name T737
Test name
Test status
Simulation time 2334041214 ps
CPU time 15.61 seconds
Started Jul 18 05:13:29 PM PDT 24
Finished Jul 18 05:13:50 PM PDT 24
Peak memory 217892 kb
Host smart-a5add890-6694-4c26-8eda-540dcf8e5117
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378318358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3378318358
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2398859056
Short name T317
Test name
Test status
Simulation time 355967477 ps
CPU time 8.85 seconds
Started Jul 18 05:13:31 PM PDT 24
Finished Jul 18 05:13:43 PM PDT 24
Peak memory 225460 kb
Host smart-ade8fe3d-acf8-41e5-87a8-a27f01c800bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398859056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
398859056
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.26879108
Short name T580
Test name
Test status
Simulation time 187773978 ps
CPU time 9.26 seconds
Started Jul 18 05:13:28 PM PDT 24
Finished Jul 18 05:13:42 PM PDT 24
Peak memory 217868 kb
Host smart-6b66e715-8d72-4856-8db9-2d4aad5b0fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26879108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.26879108
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3384836242
Short name T306
Test name
Test status
Simulation time 109484018 ps
CPU time 3.96 seconds
Started Jul 18 05:13:22 PM PDT 24
Finished Jul 18 05:13:29 PM PDT 24
Peak memory 217188 kb
Host smart-d92f15f7-d762-435d-a71a-4e7dda92899f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384836242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3384836242
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3863919638
Short name T533
Test name
Test status
Simulation time 227572548 ps
CPU time 30.98 seconds
Started Jul 18 05:13:25 PM PDT 24
Finished Jul 18 05:14:00 PM PDT 24
Peak memory 250532 kb
Host smart-6b77f753-f041-4262-adfc-3b91d7f7a1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863919638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3863919638
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.661584924
Short name T431
Test name
Test status
Simulation time 167239693 ps
CPU time 7.19 seconds
Started Jul 18 05:13:21 PM PDT 24
Finished Jul 18 05:13:31 PM PDT 24
Peak memory 242328 kb
Host smart-8dd9d222-d30a-4548-8210-e9630bbadbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661584924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.661584924
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.656781607
Short name T54
Test name
Test status
Simulation time 25075109850 ps
CPU time 186.53 seconds
Started Jul 18 05:13:26 PM PDT 24
Finished Jul 18 05:16:36 PM PDT 24
Peak memory 277128 kb
Host smart-c2d9dbaf-bc86-4b63-b230-0f5e2284e70e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656781607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.656781607
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3063923027
Short name T680
Test name
Test status
Simulation time 260678062535 ps
CPU time 1278.9 seconds
Started Jul 18 05:13:31 PM PDT 24
Finished Jul 18 05:34:54 PM PDT 24
Peak memory 388800 kb
Host smart-65bdc1b0-cef3-4c5c-b88b-a6826fd53eb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3063923027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3063923027
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2284912073
Short name T52
Test name
Test status
Simulation time 13063659 ps
CPU time 0.96 seconds
Started Jul 18 05:13:24 PM PDT 24
Finished Jul 18 05:13:28 PM PDT 24
Peak memory 208488 kb
Host smart-09a6de3b-514c-4668-bf32-bdceda358f0b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284912073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2284912073
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.485773830
Short name T558
Test name
Test status
Simulation time 43488329 ps
CPU time 0.85 seconds
Started Jul 18 05:13:45 PM PDT 24
Finished Jul 18 05:13:48 PM PDT 24
Peak memory 208156 kb
Host smart-60d8227d-c1a6-459b-b27d-dbb36d6bb1fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485773830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.485773830
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3215826509
Short name T559
Test name
Test status
Simulation time 206235456 ps
CPU time 8.4 seconds
Started Jul 18 05:13:32 PM PDT 24
Finished Jul 18 05:13:43 PM PDT 24
Peak memory 217808 kb
Host smart-9de58e9d-999c-4c65-b7fa-17d92fdc228f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215826509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3215826509
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.474588438
Short name T30
Test name
Test status
Simulation time 1125280543 ps
CPU time 11.32 seconds
Started Jul 18 05:13:47 PM PDT 24
Finished Jul 18 05:14:01 PM PDT 24
Peak memory 217008 kb
Host smart-c9c3e20f-a324-4c13-adfc-51a0bd6ba38d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474588438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.474588438
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.410452961
Short name T266
Test name
Test status
Simulation time 3139523960 ps
CPU time 49.68 seconds
Started Jul 18 05:13:46 PM PDT 24
Finished Jul 18 05:14:38 PM PDT 24
Peak memory 225560 kb
Host smart-f17af371-9b43-48db-8583-acbc5030bb90
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410452961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.410452961
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1039773762
Short name T453
Test name
Test status
Simulation time 629655005 ps
CPU time 16.56 seconds
Started Jul 18 05:13:45 PM PDT 24
Finished Jul 18 05:14:04 PM PDT 24
Peak memory 217248 kb
Host smart-3838ce6f-af32-40c6-a5a3-11768bdb47a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039773762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
039773762
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.19625856
Short name T853
Test name
Test status
Simulation time 167059732 ps
CPU time 4.26 seconds
Started Jul 18 05:13:33 PM PDT 24
Finished Jul 18 05:13:39 PM PDT 24
Peak memory 222628 kb
Host smart-aee4889f-96f1-4b2f-9134-ef81fef25f1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19625856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_p
rog_failure.19625856
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3664111508
Short name T85
Test name
Test status
Simulation time 1015525630 ps
CPU time 16 seconds
Started Jul 18 05:13:46 PM PDT 24
Finished Jul 18 05:14:05 PM PDT 24
Peak memory 217168 kb
Host smart-f7ff156d-58cf-4ac9-b1cf-bc6a4ef953a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664111508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3664111508
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2100143201
Short name T509
Test name
Test status
Simulation time 1861135683 ps
CPU time 8.87 seconds
Started Jul 18 05:13:25 PM PDT 24
Finished Jul 18 05:13:37 PM PDT 24
Peak memory 217080 kb
Host smart-d0022381-1171-4533-abaa-df3201504e9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100143201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2100143201
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.856511530
Short name T510
Test name
Test status
Simulation time 6588387638 ps
CPU time 45.56 seconds
Started Jul 18 05:13:24 PM PDT 24
Finished Jul 18 05:14:13 PM PDT 24
Peak memory 266928 kb
Host smart-8d52e0fc-f9af-41a8-9377-cc52e26e95c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856511530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.856511530
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.354894918
Short name T746
Test name
Test status
Simulation time 912647162 ps
CPU time 18.7 seconds
Started Jul 18 05:13:27 PM PDT 24
Finished Jul 18 05:13:50 PM PDT 24
Peak memory 250460 kb
Host smart-df93fa77-8cd4-40e6-ae4f-421f7b346f43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354894918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.354894918
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.929385152
Short name T303
Test name
Test status
Simulation time 147718206 ps
CPU time 3.8 seconds
Started Jul 18 05:13:32 PM PDT 24
Finished Jul 18 05:13:39 PM PDT 24
Peak memory 217796 kb
Host smart-c5ba0f3b-34c8-4663-be7b-cbfe9e35aba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929385152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.929385152
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3832936655
Short name T71
Test name
Test status
Simulation time 388875226 ps
CPU time 22.76 seconds
Started Jul 18 05:13:27 PM PDT 24
Finished Jul 18 05:13:55 PM PDT 24
Peak memory 214292 kb
Host smart-ecbfa9a6-d128-4a3d-b00b-a5ef91882e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832936655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3832936655
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3281782174
Short name T56
Test name
Test status
Simulation time 338434393 ps
CPU time 11.17 seconds
Started Jul 18 05:13:48 PM PDT 24
Finished Jul 18 05:14:02 PM PDT 24
Peak memory 218416 kb
Host smart-4f920485-4488-424d-943b-8c376a19a2b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281782174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3281782174
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.4183594876
Short name T761
Test name
Test status
Simulation time 1189778818 ps
CPU time 20.43 seconds
Started Jul 18 05:13:51 PM PDT 24
Finished Jul 18 05:14:14 PM PDT 24
Peak memory 217872 kb
Host smart-91cf07e1-1107-48a9-9bf8-9da4867976b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183594876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.4183594876
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2557981886
Short name T712
Test name
Test status
Simulation time 922786311 ps
CPU time 9.36 seconds
Started Jul 18 05:13:45 PM PDT 24
Finished Jul 18 05:13:56 PM PDT 24
Peak memory 225500 kb
Host smart-efdf0a2d-10e9-4e9d-a883-530a463e1688
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557981886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
557981886
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.586993127
Short name T419
Test name
Test status
Simulation time 759310365 ps
CPU time 11.01 seconds
Started Jul 18 05:13:27 PM PDT 24
Finished Jul 18 05:13:42 PM PDT 24
Peak memory 217864 kb
Host smart-05525bec-87cb-43c1-9b15-83659383ac93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586993127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.586993127
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.264746532
Short name T511
Test name
Test status
Simulation time 14214319 ps
CPU time 1.15 seconds
Started Jul 18 05:13:30 PM PDT 24
Finished Jul 18 05:13:35 PM PDT 24
Peak memory 211936 kb
Host smart-2c6cb2d8-3fe2-40d5-a7ee-fdcf741aa256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264746532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.264746532
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.103092044
Short name T612
Test name
Test status
Simulation time 2201841281 ps
CPU time 31.71 seconds
Started Jul 18 05:13:26 PM PDT 24
Finished Jul 18 05:14:03 PM PDT 24
Peak memory 250608 kb
Host smart-6db0dfd1-cd1f-474e-ab18-dfccda84c4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103092044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.103092044
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.4291033368
Short name T218
Test name
Test status
Simulation time 187365855 ps
CPU time 2.69 seconds
Started Jul 18 05:13:27 PM PDT 24
Finished Jul 18 05:13:35 PM PDT 24
Peak memory 220964 kb
Host smart-a2bfe09c-7883-4b33-9d84-fb1137657496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291033368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.4291033368
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.517366802
Short name T784
Test name
Test status
Simulation time 3559297880 ps
CPU time 69.59 seconds
Started Jul 18 05:13:46 PM PDT 24
Finished Jul 18 05:14:58 PM PDT 24
Peak memory 250536 kb
Host smart-55529318-d6b7-4609-824a-5c1c6b8ce7bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517366802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.517366802
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1473401516
Short name T88
Test name
Test status
Simulation time 35325881631 ps
CPU time 297.83 seconds
Started Jul 18 05:13:45 PM PDT 24
Finished Jul 18 05:18:44 PM PDT 24
Peak memory 282752 kb
Host smart-df47d0fb-821f-4555-a97b-8451f3a543e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1473401516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.1473401516
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1848369718
Short name T845
Test name
Test status
Simulation time 49687248 ps
CPU time 0.81 seconds
Started Jul 18 05:14:02 PM PDT 24
Finished Jul 18 05:14:04 PM PDT 24
Peak memory 208544 kb
Host smart-53b7fbce-c68b-462a-9aa1-02ef5c7c06d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848369718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1848369718
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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