Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1214886	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1420148

1

T1

220

T2

1150

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2317518	1			T1	199		T2	991		T4	711
values[0x0]	158340	1			T1	82		T2	378		T3	9
values[0x1]	159176	1			T1	70		T2	382		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	963862	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1671172

1

T1

249

T2

1287

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7944	1			T1	1		T2	9		T4	5
valid_sources[0x01]	7732	1			T2	4		T4	4		T13	4
valid_sources[0x02]	6255	1			T2	8		T4	5		T13	4
valid_sources[0x03]	16909	1			T1	7		T2	6		T4	8
valid_sources[0x04]	6542	1			T2	8		T3	1		T4	4
valid_sources[0x05]	6159	1			T1	2		T2	7		T4	6
valid_sources[0x06]	6500	1			T1	3		T2	7		T4	4
valid_sources[0x07]	8939	1			T1	3		T2	12		T4	7
valid_sources[0x08]	7270	1			T2	5		T4	7		T13	3
valid_sources[0x09]	6742	1			T2	11		T4	7		T13	7
valid_sources[0x0a]	6519	1			T2	7		T4	6		T13	12
valid_sources[0x0b]	6174	1			T1	1		T2	2		T4	5
valid_sources[0x0c]	15350	1			T2	4		T4	7		T13	4
valid_sources[0x0d]	6558	1			T2	5		T4	2		T13	9
valid_sources[0x0e]	18534	1			T2	2		T4	3		T13	10
valid_sources[0x0f]	6334	1			T2	8		T4	5		T13	10
valid_sources[0x10]	6503	1			T1	2		T2	4		T4	6
valid_sources[0x11]	13725	1			T2	8		T4	4		T13	1
valid_sources[0x12]	6346	1			T2	5		T4	13		T13	5
valid_sources[0x13]	6859	1			T2	6		T4	4		T13	6
valid_sources[0x14]	6286	1			T2	8		T4	4		T13	2
valid_sources[0x15]	6386	1			T1	2		T2	7		T4	2
valid_sources[0x16]	6550	1			T2	6		T4	9		T13	1
valid_sources[0x17]	6595	1			T1	6		T2	8		T3	2
valid_sources[0x18]	6645	1			T2	12		T4	8		T13	4
valid_sources[0x19]	9859	1			T2	11		T4	7		T13	1
valid_sources[0x1a]	8750	1			T1	1		T2	8		T4	1
valid_sources[0x1b]	6503	1			T2	11		T4	6		T13	5
valid_sources[0x1c]	7036	1			T2	14		T4	8		T13	2
valid_sources[0x1d]	9278	1			T1	1		T2	4		T4	6
valid_sources[0x1e]	8536	1			T1	1		T2	2		T4	1
valid_sources[0x1f]	6473	1			T1	7		T2	14		T4	2
valid_sources[0x20]	6668	1			T1	1		T2	7		T4	3
valid_sources[0x21]	6336	1			T1	1		T2	3		T4	3
valid_sources[0x22]	7693	1			T1	1		T2	4		T4	3
valid_sources[0x23]	6584	1			T2	5		T4	7		T13	3
valid_sources[0x24]	7768	1			T1	1		T2	6		T4	7
valid_sources[0x25]	6444	1			T2	7		T4	4		T13	5
valid_sources[0x26]	6848	1			T2	11		T4	5		T13	5
valid_sources[0x27]	6278	1			T2	4		T4	7		T13	9
valid_sources[0x28]	6215	1			T1	2		T2	6		T3	1
valid_sources[0x29]	6263	1			T2	2		T4	5		T13	3
valid_sources[0x2a]	6283	1			T2	3		T4	4		T13	6
valid_sources[0x2b]	6457	1			T2	8		T4	7		T13	5
valid_sources[0x2c]	6411	1			T1	2		T2	6		T4	8
valid_sources[0x2d]	6323	1			T2	5		T4	2		T13	3
valid_sources[0x2e]	7573	1			T1	1		T2	15		T4	5
valid_sources[0x2f]	6240	1			T1	1		T2	4		T4	9
valid_sources[0x30]	6721	1			T1	1		T2	3		T4	2
valid_sources[0x31]	6449	1			T2	4		T4	6		T13	3
valid_sources[0x32]	9326	1			T2	5		T4	3		T13	4
valid_sources[0x33]	6341	1			T2	4		T4	5		T13	1
valid_sources[0x34]	6570	1			T2	9		T4	6		T11	1
valid_sources[0x35]	6715	1			T2	7		T4	10		T13	10
valid_sources[0x36]	6087	1			T1	2		T2	5		T4	9
valid_sources[0x37]	6111	1			T1	1		T2	6		T4	9
valid_sources[0x38]	7264	1			T2	11		T4	1		T13	2
valid_sources[0x39]	6334	1			T2	4		T4	5		T13	7
valid_sources[0x3a]	6628	1			T1	5		T2	6		T4	3
valid_sources[0x3b]	6485	1			T1	4		T2	6		T4	8
valid_sources[0x3c]	6422	1			T1	1		T2	10		T4	7
valid_sources[0x3d]	6514	1			T2	6		T4	6		T13	9
valid_sources[0x3e]	6452	1			T1	2		T2	5		T4	5
valid_sources[0x3f]	6362	1			T1	2		T2	5		T4	4
valid_sources[0x40]	7973	1			T2	6		T4	5		T13	7
valid_sources[0x41]	6344	1			T1	4		T2	4		T4	5
valid_sources[0x42]	6297	1			T1	1		T2	5		T4	5
valid_sources[0x43]	6748	1			T1	1		T2	6		T4	10
valid_sources[0x44]	6205	1			T1	1		T2	9		T4	2
valid_sources[0x45]	31512	1			T1	1		T2	10		T4	10
valid_sources[0x46]	20820	1			T2	10		T4	1		T13	4
valid_sources[0x47]	7323	1			T2	3		T4	2		T13	6
valid_sources[0x48]	6747	1			T2	6		T4	3		T13	6
valid_sources[0x49]	7795	1			T1	5		T2	8		T4	4
valid_sources[0x4a]	7757	1			T1	5		T2	5		T4	7
valid_sources[0x4b]	6656	1			T2	4		T4	6		T13	11
valid_sources[0x4c]	9623	1			T2	7		T4	4		T13	1
valid_sources[0x4d]	66192	1			T2	7		T4	9		T13	3
valid_sources[0x4e]	6189	1			T2	7		T4	4		T13	1
valid_sources[0x4f]	6429	1			T2	4		T4	5		T13	4
valid_sources[0x50]	6174	1			T1	1		T2	3		T4	8
valid_sources[0x51]	8496	1			T1	4		T2	2		T4	2
valid_sources[0x52]	44537	1			T1	4		T2	9		T4	4
valid_sources[0x53]	6784	1			T2	5		T4	10		T13	1
valid_sources[0x54]	6280	1			T1	1		T2	8		T4	5
valid_sources[0x55]	6506	1			T2	10		T4	5		T13	6
valid_sources[0x56]	7468	1			T2	2		T4	9		T13	7
valid_sources[0x57]	6232	1			T1	1		T2	6		T4	3
valid_sources[0x58]	6458	1			T2	12		T4	1		T13	3
valid_sources[0x59]	6337	1			T1	2		T2	10		T4	6
valid_sources[0x5a]	6356	1			T2	3		T4	4		T13	12
valid_sources[0x5b]	6294	1			T2	4		T4	3		T11	7
valid_sources[0x5c]	16439	1			T2	6		T4	7		T13	4
valid_sources[0x5d]	6641	1			T2	10		T4	5		T13	1
valid_sources[0x5e]	8152	1			T1	8		T2	8		T4	10
valid_sources[0x5f]	6829	1			T2	3		T3	1		T4	5
valid_sources[0x60]	42391	1			T2	4		T4	7		T13	4
valid_sources[0x61]	6347	1			T1	1		T2	5		T4	6
valid_sources[0x62]	7755	1			T1	1		T2	3		T4	8
valid_sources[0x63]	6648	1			T2	7		T4	10		T13	4
valid_sources[0x64]	7887	1			T1	5		T2	16		T4	4
valid_sources[0x65]	7499	1			T1	1		T2	4		T4	7
valid_sources[0x66]	9811	1			T1	2		T2	3		T4	3
valid_sources[0x67]	11834	1			T1	4		T2	14		T4	6
valid_sources[0x68]	16335	1			T2	9		T4	4		T13	5
valid_sources[0x69]	7519	1			T2	10		T4	6		T15	6
valid_sources[0x6a]	6211	1			T2	8		T4	8		T13	4
valid_sources[0x6b]	48274	1			T1	2		T2	6		T4	6
valid_sources[0x6c]	10521	1			T1	1		T2	4		T4	3
valid_sources[0x6d]	7407	1			T2	6		T4	5		T13	1
valid_sources[0x6e]	6774	1			T1	6		T2	7		T4	2
valid_sources[0x6f]	6433	1			T1	3		T2	7		T4	9
valid_sources[0x70]	6332	1			T2	3		T4	6		T13	3
valid_sources[0x71]	6635	1			T2	11		T4	5		T13	6
valid_sources[0x72]	6394	1			T2	11		T4	4		T13	2
valid_sources[0x73]	6434	1			T1	1		T2	14		T4	5
valid_sources[0x74]	6166	1			T1	2		T2	7		T4	6
valid_sources[0x75]	6611	1			T2	12		T4	6		T13	4
valid_sources[0x76]	8219	1			T2	7		T4	7		T13	5
valid_sources[0x77]	7800	1			T1	1		T2	9		T4	5
valid_sources[0x78]	6169	1			T1	1		T2	8		T4	5
valid_sources[0x79]	6263	1			T2	3		T4	3		T13	7
valid_sources[0x7a]	6527	1			T1	4		T2	1		T4	5
valid_sources[0x7b]	7645	1			T2	5		T4	4		T13	2
valid_sources[0x7c]	24218	1			T2	11		T4	6		T13	6
valid_sources[0x7d]	6527	1			T1	1		T2	3		T4	3
valid_sources[0x7e]	6463	1			T1	3		T2	7		T4	1
valid_sources[0x7f]	6403	1			T2	9		T4	4		T13	9
valid_sources[0x80]	8514	1			T2	3		T3	2		T4	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1146049

1

T1

89

T2

486

T4

354

values[0x0]

all_enables

biggest_size

137512

1

T1

72

T2

328

T3

5

values[0x1]

all_enables

biggest_size

136587

1

T1

59

T2

336

T3

1