Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	98784037	15651	0	0
claim_transition_if_regwen_rd_A	98784037	1510	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98784037	15651	0	0
T66	1822	0	0	0
T72	1073	0	0	0
T94	9825	0	0	0
T95	171556	1	0	0
T96	542358	3	0	0
T97	0	7	0	0
T105	0	2	0	0
T106	0	2	0	0
T109	0	11	0	0
T146	0	1	0	0
T147	0	3	0	0
T148	0	4	0	0
T149	0	10	0	0
T150	1507	0	0	0
T151	28523	0	0	0
T152	36028	0	0	0
T153	30770	0	0	0
T154	10263	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98784037	1510	0	0
T64	69578	0	0	0
T107	0	2	0	0
T117	0	86	0	0
T131	0	82	0	0
T147	206396	8	0	0
T155	0	5	0	0
T156	0	38	0	0
T157	0	58	0	0
T158	0	18	0	0
T159	0	10	0	0
T160	0	9	0	0
T161	49109	0	0	0
T162	19284	0	0	0
T163	13383	0	0	0
T164	1888	0	0	0
T165	16349	0	0	0
T166	227902	0	0	0
T167	57349	0	0	0
T168	4179	0	0	0