Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	958583	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1153344

1

T1

202

T2

11

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1804906	1			T1	181		T2	69		T3	7
values[0x0]	152701	1			T1	65		T2	6		T3	9
values[0x1]	154320	1			T1	86		T2	10		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	759438	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1352489

1

T1

234

T2

32

T3

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5351	1			T1	4		T4	5		T6	3
valid_sources[0x01]	5554	1			T4	7		T5	9		T6	4
valid_sources[0x02]	5262	1			T2	1		T4	3		T6	5
valid_sources[0x03]	5769	1			T1	4		T4	4		T14	2
valid_sources[0x04]	5330	1			T1	3		T4	7		T6	7
valid_sources[0x05]	5345	1			T1	1		T4	7		T5	12
valid_sources[0x06]	7310	1			T1	2		T4	5		T6	5
valid_sources[0x07]	5390	1			T1	3		T2	1		T4	7
valid_sources[0x08]	5542	1			T4	1		T6	9		T16	6
valid_sources[0x09]	7690	1			T4	1		T6	7		T16	1
valid_sources[0x0a]	5415	1			T1	1		T4	4		T14	1
valid_sources[0x0b]	5441	1			T2	1		T4	12		T13	1
valid_sources[0x0c]	8619	1			T1	1		T4	6		T5	5
valid_sources[0x0d]	5406	1			T1	2		T4	11		T14	5
valid_sources[0x0e]	5717	1			T2	1		T4	3		T14	2
valid_sources[0x0f]	5457	1			T1	2		T2	1		T6	6
valid_sources[0x10]	8146	1			T4	5		T6	4		T16	2
valid_sources[0x11]	5495	1			T2	2		T4	4		T6	2
valid_sources[0x12]	46193	1			T1	4		T4	4		T6	4
valid_sources[0x13]	5531	1			T1	1		T4	5		T6	8
valid_sources[0x14]	6576	1			T1	2		T4	5		T6	1
valid_sources[0x15]	5524	1			T1	1		T4	5		T13	1
valid_sources[0x16]	5425	1			T1	2		T4	10		T6	6
valid_sources[0x17]	5492	1			T1	2		T2	1		T4	1
valid_sources[0x18]	5542	1			T4	2		T6	10		T16	5
valid_sources[0x19]	6835	1			T4	2		T14	1		T6	5
valid_sources[0x1a]	5394	1			T1	4		T4	1		T13	1
valid_sources[0x1b]	5713	1			T1	2		T4	6		T6	9
valid_sources[0x1c]	11187	1			T4	10		T14	1		T6	5
valid_sources[0x1d]	5616	1			T2	3		T4	9		T13	2
valid_sources[0x1e]	5910	1			T4	4		T6	4		T16	6
valid_sources[0x1f]	5270	1			T4	7		T6	2		T16	12
valid_sources[0x20]	6934	1			T4	3		T6	8		T16	4
valid_sources[0x21]	5446	1			T1	1		T4	2		T6	7
valid_sources[0x22]	5493	1			T1	1		T4	9		T6	3
valid_sources[0x23]	5491	1			T6	11		T16	2		T8	1
valid_sources[0x24]	13559	1			T1	1		T4	2		T6	4
valid_sources[0x25]	5622	1			T4	5		T6	7		T16	5
valid_sources[0x26]	7958	1			T1	2		T4	5		T14	1
valid_sources[0x27]	76821	1			T4	10		T6	5		T16	7
valid_sources[0x28]	6007	1			T1	2		T4	3		T6	6
valid_sources[0x29]	5389	1			T4	6		T6	7		T16	11
valid_sources[0x2a]	7387	1			T4	10		T6	3		T16	2
valid_sources[0x2b]	5583	1			T1	2		T2	1		T4	7
valid_sources[0x2c]	5540	1			T1	2		T2	2		T4	4
valid_sources[0x2d]	5470	1			T1	3		T4	1		T6	11
valid_sources[0x2e]	6146	1			T4	6		T6	2		T16	4
valid_sources[0x2f]	7194	1			T4	5		T5	1		T6	2
valid_sources[0x30]	5466	1			T1	2		T4	2		T6	1
valid_sources[0x31]	6752	1			T1	2		T4	1		T6	5
valid_sources[0x32]	5600	1			T2	1		T4	6		T6	5
valid_sources[0x33]	5367	1			T1	3		T2	3		T4	5
valid_sources[0x34]	5076	1			T1	1		T4	1		T6	8
valid_sources[0x35]	5926	1			T1	2		T2	4		T4	10
valid_sources[0x36]	5575	1			T4	7		T6	5		T16	2
valid_sources[0x37]	6823	1			T4	5		T6	9		T16	7
valid_sources[0x38]	5490	1			T1	1		T4	6		T5	2
valid_sources[0x39]	5385	1			T1	1		T4	3		T6	2
valid_sources[0x3a]	50346	1			T4	8		T6	11		T16	4
valid_sources[0x3b]	5438	1			T2	3		T4	4		T6	9
valid_sources[0x3c]	5436	1			T1	4		T4	5		T6	6
valid_sources[0x3d]	6295	1			T1	2		T4	4		T6	3
valid_sources[0x3e]	5635	1			T1	1		T4	4		T16	5
valid_sources[0x3f]	5340	1			T1	1		T4	10		T13	1
valid_sources[0x40]	9434	1			T1	2		T4	4		T6	2
valid_sources[0x41]	5348	1			T4	3		T5	9		T6	11
valid_sources[0x42]	5342	1			T1	2		T4	2		T6	9
valid_sources[0x43]	5587	1			T1	1		T4	5		T6	11
valid_sources[0x44]	5819	1			T4	13		T6	8		T15	15
valid_sources[0x45]	5649	1			T1	2		T2	2		T4	2
valid_sources[0x46]	5531	1			T1	1		T6	6		T16	1
valid_sources[0x47]	5459	1			T1	3		T4	2		T6	10
valid_sources[0x48]	6842	1			T1	6		T4	3		T6	5
valid_sources[0x49]	7023	1			T2	2		T4	7		T6	9
valid_sources[0x4a]	5812	1			T1	2		T13	2		T6	15
valid_sources[0x4b]	5926	1			T1	2		T4	9		T5	33
valid_sources[0x4c]	5355	1			T1	3		T4	1		T6	3
valid_sources[0x4d]	8566	1			T1	4		T4	2		T6	5
valid_sources[0x4e]	5719	1			T1	1		T2	1		T4	3
valid_sources[0x4f]	9021	1			T1	4		T4	10		T6	6
valid_sources[0x50]	9590	1			T4	4		T6	6		T16	4
valid_sources[0x51]	5387	1			T1	1		T4	7		T6	7
valid_sources[0x52]	5611	1			T6	2		T16	3		T18	1
valid_sources[0x53]	5766	1			T1	3		T4	9		T6	7
valid_sources[0x54]	5421	1			T1	1		T4	5		T6	8
valid_sources[0x55]	11883	1			T4	2		T13	3		T6	3
valid_sources[0x56]	5343	1			T1	2		T2	1		T4	4
valid_sources[0x57]	5655	1			T1	1		T4	4		T6	5
valid_sources[0x58]	13306	1			T1	3		T2	1		T4	3
valid_sources[0x59]	5312	1			T2	3		T4	8		T6	5
valid_sources[0x5a]	5834	1			T4	2		T6	6		T16	4
valid_sources[0x5b]	5376	1			T1	3		T4	2		T6	6
valid_sources[0x5c]	5605	1			T1	1		T4	1		T16	2
valid_sources[0x5d]	7308	1			T1	1		T2	1		T4	1
valid_sources[0x5e]	6090	1			T1	1		T4	4		T6	11
valid_sources[0x5f]	5723	1			T1	2		T4	3		T6	19
valid_sources[0x60]	24941	1			T1	4		T4	3		T6	3
valid_sources[0x61]	5329	1			T1	1		T4	3		T6	7
valid_sources[0x62]	7427	1			T2	3		T4	6		T6	8
valid_sources[0x63]	6486	1			T1	1		T4	9		T6	8
valid_sources[0x64]	7773	1			T1	1		T4	7		T5	6
valid_sources[0x65]	5722	1			T1	2		T2	2		T4	7
valid_sources[0x66]	8525	1			T4	6		T6	12		T16	6
valid_sources[0x67]	5431	1			T4	8		T6	6		T16	6
valid_sources[0x68]	6948	1			T1	2		T4	3		T6	8
valid_sources[0x69]	5726	1			T2	1		T16	3		T17	1
valid_sources[0x6a]	6028	1			T1	3		T4	3		T6	7
valid_sources[0x6b]	5364	1			T1	1		T4	3		T6	5
valid_sources[0x6c]	5471	1			T1	1		T4	5		T6	2
valid_sources[0x6d]	5681	1			T4	5		T6	10		T16	1
valid_sources[0x6e]	5453	1			T1	1		T4	7		T6	7
valid_sources[0x6f]	5768	1			T6	22		T16	2		T19	9
valid_sources[0x70]	5408	1			T3	23		T4	2		T6	11
valid_sources[0x71]	5359	1			T1	1		T4	7		T6	13
valid_sources[0x72]	16916	1			T1	2		T4	14		T6	8
valid_sources[0x73]	5801	1			T1	2		T2	1		T4	10
valid_sources[0x74]	5552	1			T1	1		T4	12		T6	6
valid_sources[0x75]	9503	1			T1	1		T4	3		T6	2
valid_sources[0x76]	5309	1			T1	2		T2	1		T4	7
valid_sources[0x77]	5682	1			T1	2		T4	5		T6	3
valid_sources[0x78]	5824	1			T1	2		T6	3		T16	8
valid_sources[0x79]	5574	1			T1	2		T4	4		T6	6
valid_sources[0x7a]	5222	1			T1	1		T4	2		T6	8
valid_sources[0x7b]	5558	1			T1	2		T2	4		T4	5
valid_sources[0x7c]	7375	1			T4	7		T6	8		T16	2
valid_sources[0x7d]	5459	1			T1	1		T2	1		T4	4
valid_sources[0x7e]	6879	1			T1	3		T4	2		T13	2
valid_sources[0x7f]	5582	1			T1	3		T4	4		T6	5
valid_sources[0x80]	5477	1			T1	4		T2	7		T4	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

888690

1

T1

79

T2

1

T3

1

values[0x0]

all_enables

biggest_size

132572

1

T1

57

T2

5

T3

8

values[0x1]

all_enables

biggest_size

132082

1

T1

66

T2

5

T3

4