Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	87495046	12589	0	0
claim_transition_if_regwen_rd_A	87495046	1445	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87495046	12589	0	0
T49	0	6	0	0
T61	1566	0	0	0
T69	908	0	0	0
T85	539551	3	0	0
T106	31341	0	0	0
T107	1268	0	0	0
T112	0	5	0	0
T146	0	7	0	0
T148	0	2	0	0
T149	0	10	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	0	3	0	0
T153	0	4	0	0
T154	31583	0	0	0
T155	23942	0	0	0
T156	29248	0	0	0
T157	1030	0	0	0
T158	11712	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87495046	1445	0	0
T61	1566	0	0	0
T69	908	0	0	0
T85	539551	1	0	0
T106	31341	0	0	0
T107	1268	0	0	0
T126	0	17	0	0
T127	0	37	0	0
T128	0	76	0	0
T130	0	117	0	0
T131	0	74	0	0
T141	0	62	0	0
T152	0	8	0	0
T154	31583	0	0	0
T155	23942	0	0	0
T156	29248	0	0	0
T157	1030	0	0	0
T158	11712	0	0	0
T159	0	8	0	0
T160	0	496	0	0