Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1623453	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1837724

1

T1

6

T2

2125

T3

935

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3124112	1			T2	2879		T3	959		T4	15108
values[0x0]	168416	1			T1	14		T2	384		T3	273
values[0x1]	168649	1			T1	10		T2	392		T3	271

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1289650	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2171527

1

T1

7

T2

2441

T3

1056

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12722	1			T2	5		T3	5		T4	59
valid_sources[0x01]	9506	1			T2	22		T3	6		T4	87
valid_sources[0x02]	9468	1			T2	1		T3	8		T4	49
valid_sources[0x03]	9857	1			T2	5		T3	7		T4	79
valid_sources[0x04]	9873	1			T2	13		T3	1		T4	48
valid_sources[0x05]	11039	1			T2	14		T3	5		T4	60
valid_sources[0x06]	10603	1			T2	10		T3	4		T4	52
valid_sources[0x07]	9623	1			T2	17		T3	6		T4	96
valid_sources[0x08]	11799	1			T2	7		T3	5		T4	50
valid_sources[0x09]	9760	1			T2	8		T3	7		T4	98
valid_sources[0x0a]	145521	1			T2	25		T3	3		T4	40
valid_sources[0x0b]	9751	1			T2	6		T3	13		T4	73
valid_sources[0x0c]	9327	1			T2	21		T3	4		T4	82
valid_sources[0x0d]	9490	1			T2	17		T3	9		T4	48
valid_sources[0x0e]	43200	1			T2	18		T3	7		T4	46
valid_sources[0x0f]	9390	1			T2	26		T3	10		T4	50
valid_sources[0x10]	9800	1			T2	24		T3	13		T4	71
valid_sources[0x11]	9774	1			T2	12		T3	5		T4	71
valid_sources[0x12]	9652	1			T2	17		T3	3		T4	65
valid_sources[0x13]	9654	1			T2	2		T3	3		T4	61
valid_sources[0x14]	10818	1			T2	5		T3	11		T4	59
valid_sources[0x15]	9620	1			T2	17		T3	5		T4	80
valid_sources[0x16]	10192	1			T2	20		T3	14		T4	71
valid_sources[0x17]	15210	1			T2	21		T3	4		T4	94
valid_sources[0x18]	9558	1			T2	15		T3	4		T4	49
valid_sources[0x19]	10439	1			T2	9		T3	12		T4	58
valid_sources[0x1a]	10162	1			T2	14		T3	8		T4	63
valid_sources[0x1b]	9654	1			T2	25		T3	8		T4	57
valid_sources[0x1c]	9946	1			T2	15		T3	3		T4	62
valid_sources[0x1d]	10692	1			T2	17		T3	6		T4	42
valid_sources[0x1e]	11868	1			T2	4		T3	4		T4	37
valid_sources[0x1f]	9689	1			T2	28		T3	6		T4	37
valid_sources[0x20]	10640	1			T2	8		T3	4		T4	82
valid_sources[0x21]	9681	1			T2	24		T3	3		T4	72
valid_sources[0x22]	9469	1			T2	9		T3	1		T4	81
valid_sources[0x23]	10292	1			T2	9		T3	6		T4	88
valid_sources[0x24]	9550	1			T2	18		T3	5		T4	53
valid_sources[0x25]	9704	1			T2	7		T3	7		T4	50
valid_sources[0x26]	9946	1			T2	28		T3	9		T4	48
valid_sources[0x27]	12328	1			T2	19		T3	7		T4	70
valid_sources[0x28]	9536	1			T2	12		T3	4		T4	55
valid_sources[0x29]	9649	1			T2	12		T3	5		T4	86
valid_sources[0x2a]	9353	1			T2	13		T3	4		T4	46
valid_sources[0x2b]	9960	1			T2	13		T3	9		T4	90
valid_sources[0x2c]	20283	1			T2	30		T3	3		T4	47
valid_sources[0x2d]	11927	1			T2	7		T3	8		T4	87
valid_sources[0x2e]	9283	1			T2	11		T3	10		T4	43
valid_sources[0x2f]	98671	1			T2	18		T3	4		T4	63
valid_sources[0x30]	11051	1			T2	6		T3	3		T4	59
valid_sources[0x31]	9357	1			T2	15		T4	25		T15	201
valid_sources[0x32]	12540	1			T2	28		T3	4		T4	100
valid_sources[0x33]	9645	1			T2	22		T3	2		T4	65
valid_sources[0x34]	10287	1			T2	18		T3	6		T4	55
valid_sources[0x35]	9333	1			T2	21		T3	2		T4	51
valid_sources[0x36]	9783	1			T2	31		T3	2		T4	79
valid_sources[0x37]	9744	1			T2	14		T3	2		T4	55
valid_sources[0x38]	9606	1			T2	13		T3	6		T4	68
valid_sources[0x39]	10007	1			T2	7		T3	8		T4	68
valid_sources[0x3a]	10366	1			T2	17		T3	7		T4	61
valid_sources[0x3b]	9594	1			T2	11		T3	5		T4	63
valid_sources[0x3c]	9638	1			T2	7		T3	9		T4	85
valid_sources[0x3d]	12883	1			T2	7		T3	8		T4	59
valid_sources[0x3e]	9967	1			T2	15		T3	5		T4	66
valid_sources[0x3f]	9292	1			T2	6		T3	6		T4	74
valid_sources[0x40]	9542	1			T2	5		T3	18		T4	79
valid_sources[0x41]	9922	1			T2	6		T3	5		T4	109
valid_sources[0x42]	11504	1			T2	4		T3	4		T4	72
valid_sources[0x43]	9790	1			T2	17		T3	3		T4	39
valid_sources[0x44]	9629	1			T2	5		T3	7		T4	54
valid_sources[0x45]	9830	1			T2	11		T4	59		T7	4
valid_sources[0x46]	12217	1			T2	23		T3	7		T4	69
valid_sources[0x47]	11549	1			T2	26		T3	10		T4	59
valid_sources[0x48]	9893	1			T2	16		T3	1		T4	50
valid_sources[0x49]	14426	1			T2	4		T3	6		T4	67
valid_sources[0x4a]	9652	1			T2	24		T3	6		T4	65
valid_sources[0x4b]	10058	1			T2	5		T3	8		T4	69
valid_sources[0x4c]	9898	1			T2	22		T3	7		T4	70
valid_sources[0x4d]	10200	1			T2	24		T4	44		T7	3
valid_sources[0x4e]	10284	1			T2	7		T3	8		T4	55
valid_sources[0x4f]	12491	1			T2	6		T3	4		T4	51
valid_sources[0x50]	9537	1			T2	16		T3	2		T4	56
valid_sources[0x51]	9405	1			T2	19		T3	5		T4	53
valid_sources[0x52]	9404	1			T2	11		T3	6		T4	79
valid_sources[0x53]	14067	1			T2	15		T3	2		T4	58
valid_sources[0x54]	9618	1			T2	6		T3	11		T4	68
valid_sources[0x55]	15047	1			T2	3		T3	5		T4	103
valid_sources[0x56]	9603	1			T2	16		T3	7		T4	65
valid_sources[0x57]	9455	1			T2	14		T3	2		T4	44
valid_sources[0x58]	11327	1			T2	6		T3	5		T4	59
valid_sources[0x59]	9557	1			T1	24		T2	15		T3	6
valid_sources[0x5a]	10091	1			T2	16		T3	7		T4	70
valid_sources[0x5b]	9781	1			T2	10		T3	4		T4	51
valid_sources[0x5c]	10045	1			T2	14		T3	10		T4	62
valid_sources[0x5d]	35193	1			T2	24		T3	12		T4	48
valid_sources[0x5e]	10144	1			T2	11		T3	4		T4	68
valid_sources[0x5f]	10710	1			T2	8		T3	5		T4	44
valid_sources[0x60]	9452	1			T2	17		T3	7		T4	51
valid_sources[0x61]	9705	1			T2	17		T3	3		T4	134
valid_sources[0x62]	9434	1			T2	7		T3	2		T4	39
valid_sources[0x63]	9701	1			T2	2		T3	12		T4	50
valid_sources[0x64]	11388	1			T2	23		T3	11		T4	43
valid_sources[0x65]	11705	1			T2	14		T3	4		T4	71
valid_sources[0x66]	11518	1			T2	12		T3	7		T4	41
valid_sources[0x67]	9968	1			T2	11		T3	6		T4	47
valid_sources[0x68]	9683	1			T2	19		T3	8		T4	45
valid_sources[0x69]	9357	1			T2	18		T3	5		T4	58
valid_sources[0x6a]	9498	1			T2	17		T3	3		T4	119
valid_sources[0x6b]	9865	1			T2	8		T3	3		T4	58
valid_sources[0x6c]	9528	1			T2	20		T3	5		T4	40
valid_sources[0x6d]	9856	1			T2	9		T3	8		T4	76
valid_sources[0x6e]	9468	1			T2	19		T3	1		T4	49
valid_sources[0x6f]	9799	1			T2	5		T3	5		T4	58
valid_sources[0x70]	9482	1			T2	10		T3	9		T4	79
valid_sources[0x71]	9856	1			T2	12		T3	8		T4	75
valid_sources[0x72]	12388	1			T2	14		T3	13		T4	58
valid_sources[0x73]	9497	1			T2	4		T3	4		T4	60
valid_sources[0x74]	13034	1			T2	14		T3	4		T4	34
valid_sources[0x75]	9468	1			T2	7		T3	10		T4	40
valid_sources[0x76]	14367	1			T2	28		T3	4		T4	67
valid_sources[0x77]	10488	1			T2	24		T3	7		T4	60
valid_sources[0x78]	10478	1			T2	13		T3	13		T4	48
valid_sources[0x79]	9205	1			T2	9		T3	6		T4	36
valid_sources[0x7a]	24506	1			T2	18		T3	4		T4	61
valid_sources[0x7b]	9522	1			T2	18		T3	2		T4	52
valid_sources[0x7c]	9327	1			T2	8		T3	6		T4	32
valid_sources[0x7d]	9983	1			T2	15		T3	7		T4	61
valid_sources[0x7e]	10174	1			T2	35		T3	6		T4	63
valid_sources[0x7f]	9838	1			T2	12		T3	6		T4	70
valid_sources[0x80]	64662	1			T2	10		T3	11		T4	79

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1547147

1

T2

1449

T3

450

T4

7568

values[0x0]

all_enables

biggest_size

145903

1

T1

5

T2

329

T3

239

values[0x1]

all_enables

biggest_size

144674

1

T1

1

T2

347

T3

246