Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	105421968	13521	0	0
claim_transition_if_regwen_rd_A	105421968	1636	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105421968	13521	0	0
T8	52917	0	0	0
T18	220856	6	0	0
T34	1367	0	0	0
T37	6897	0	0	0
T42	131902	0	0	0
T50	27654	0	0	0
T58	0	11	0	0
T63	27943	0	0	0
T64	37764	0	0	0
T80	0	6	0	0
T94	0	4	0	0
T113	0	20	0	0
T149	0	1	0	0
T150	0	4	0	0
T151	0	5	0	0
T152	0	3	0	0
T153	0	9	0	0
T154	8523	0	0	0
T155	25743	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105421968	1636	0	0
T74	2656	0	0	0
T108	0	7	0	0
T110	0	55	0	0
T111	0	21	0	0
T118	0	6	0	0
T151	177215	1	0	0
T152	0	20	0	0
T156	0	12	0	0
T157	0	6	0	0
T158	0	1	0	0
T159	0	11	0	0
T160	18628	0	0	0
T161	1778	0	0	0
T162	9708	0	0	0
T163	1184	0	0	0
T164	26507	0	0	0
T165	176050	0	0	0
T166	1871	0	0	0
T167	23604	0	0	0