Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1470025	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1677198

1

T1

2946

T2

1113

T3

830

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2822504	1			T1	5006		T2	917		T3	642
values[0x0]	161188	1			T1	298		T2	407		T3	288
values[0x1]	163531	1			T1	270		T2	377		T3	296

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1167197	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1980026

1

T1

3504

T2

1248

T3

920

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10255	1			T1	22		T4	160		T12	4
valid_sources[0x01]	10164	1			T1	23		T4	170		T11	1
valid_sources[0x02]	10331	1			T1	23		T4	166		T12	3
valid_sources[0x03]	10739	1			T1	15		T4	128		T12	1
valid_sources[0x04]	10702	1			T1	15		T2	7		T4	173
valid_sources[0x05]	15318	1			T1	30		T4	133		T15	2
valid_sources[0x06]	9997	1			T1	19		T4	153		T12	3
valid_sources[0x07]	10272	1			T1	19		T2	5		T4	165
valid_sources[0x08]	11859	1			T1	13		T2	5		T4	140
valid_sources[0x09]	18926	1			T1	20		T2	36		T4	111
valid_sources[0x0a]	9906	1			T1	22		T4	184		T12	8
valid_sources[0x0b]	10242	1			T1	20		T4	171		T12	5
valid_sources[0x0c]	10372	1			T1	22		T4	172		T12	4
valid_sources[0x0d]	10529	1			T1	22		T4	123		T12	2
valid_sources[0x0e]	10330	1			T1	28		T4	157		T12	3
valid_sources[0x0f]	20108	1			T1	20		T4	157		T12	4
valid_sources[0x10]	11625	1			T1	19		T4	165		T12	1
valid_sources[0x11]	10112	1			T1	23		T4	148		T13	3
valid_sources[0x12]	15887	1			T1	18		T4	143		T12	5
valid_sources[0x13]	49771	1			T1	26		T4	167		T12	3
valid_sources[0x14]	10482	1			T1	17		T2	15		T4	169
valid_sources[0x15]	10129	1			T1	36		T2	21		T4	167
valid_sources[0x16]	10812	1			T1	27		T4	167		T12	4
valid_sources[0x17]	10288	1			T1	33		T4	136		T12	6
valid_sources[0x18]	12243	1			T1	39		T4	148		T12	4
valid_sources[0x19]	10181	1			T1	24		T4	162		T12	4
valid_sources[0x1a]	10321	1			T1	29		T4	186		T12	9
valid_sources[0x1b]	12666	1			T1	26		T4	144		T12	9
valid_sources[0x1c]	10393	1			T1	20		T4	125		T12	2
valid_sources[0x1d]	10779	1			T1	27		T4	173		T12	10
valid_sources[0x1e]	11837	1			T1	20		T4	116		T11	1
valid_sources[0x1f]	11853	1			T1	19		T2	5		T4	139
valid_sources[0x20]	12780	1			T1	24		T2	8		T4	136
valid_sources[0x21]	10383	1			T1	20		T4	150		T12	11
valid_sources[0x22]	26278	1			T1	12		T4	184		T12	13
valid_sources[0x23]	13238	1			T1	24		T4	149		T12	1
valid_sources[0x24]	10557	1			T1	20		T2	17		T4	128
valid_sources[0x25]	27415	1			T1	27		T2	16		T4	134
valid_sources[0x26]	10381	1			T1	13		T2	5		T4	163
valid_sources[0x27]	10190	1			T1	12		T4	144		T12	3
valid_sources[0x28]	10407	1			T1	16		T2	50		T4	154
valid_sources[0x29]	10276	1			T1	14		T4	182		T12	1
valid_sources[0x2a]	10047	1			T1	27		T4	156		T13	3
valid_sources[0x2b]	10124	1			T1	15		T4	132		T12	4
valid_sources[0x2c]	10147	1			T1	13		T4	154		T12	4
valid_sources[0x2d]	11626	1			T1	22		T4	141		T12	6
valid_sources[0x2e]	15258	1			T1	19		T4	148		T12	2
valid_sources[0x2f]	13479	1			T1	26		T2	1		T4	150
valid_sources[0x30]	10238	1			T1	25		T4	151		T12	1
valid_sources[0x31]	136218	1			T1	29		T4	141		T12	1
valid_sources[0x32]	10307	1			T1	28		T4	146		T12	2
valid_sources[0x33]	10532	1			T1	20		T4	139		T12	2
valid_sources[0x34]	12256	1			T1	15		T4	143		T12	6
valid_sources[0x35]	10561	1			T1	24		T2	1		T4	214
valid_sources[0x36]	11614	1			T1	26		T2	10		T4	133
valid_sources[0x37]	13421	1			T1	21		T2	33		T4	181
valid_sources[0x38]	10454	1			T1	28		T4	168		T13	1
valid_sources[0x39]	10940	1			T1	23		T4	134		T11	2
valid_sources[0x3a]	10720	1			T1	21		T2	8		T4	147
valid_sources[0x3b]	10286	1			T1	21		T4	139		T12	5
valid_sources[0x3c]	10447	1			T1	18		T4	171		T12	2
valid_sources[0x3d]	10283	1			T1	24		T2	2		T4	170
valid_sources[0x3e]	10549	1			T1	18		T4	179		T12	9
valid_sources[0x3f]	10016	1			T1	18		T4	169		T12	6
valid_sources[0x40]	10641	1			T1	25		T4	130		T12	10
valid_sources[0x41]	10470	1			T1	17		T2	18		T4	196
valid_sources[0x42]	10504	1			T1	21		T2	25		T4	138
valid_sources[0x43]	90053	1			T1	29		T4	148		T12	8
valid_sources[0x44]	10544	1			T1	13		T4	146		T12	4
valid_sources[0x45]	17536	1			T1	24		T4	138		T12	6
valid_sources[0x46]	11037	1			T1	24		T4	117		T12	4
valid_sources[0x47]	10380	1			T1	28		T2	11		T4	168
valid_sources[0x48]	10082	1			T1	36		T4	132		T12	2
valid_sources[0x49]	10480	1			T1	24		T4	123		T12	4
valid_sources[0x4a]	10300	1			T1	30		T2	42		T4	137
valid_sources[0x4b]	10323	1			T1	26		T4	139		T12	2
valid_sources[0x4c]	27070	1			T1	23		T4	127		T15	4
valid_sources[0x4d]	10392	1			T1	18		T4	137		T12	2
valid_sources[0x4e]	12902	1			T1	21		T2	19		T4	103
valid_sources[0x4f]	9890	1			T1	11		T4	126		T12	2
valid_sources[0x50]	11360	1			T1	29		T4	138		T12	2
valid_sources[0x51]	10046	1			T1	20		T4	148		T12	5
valid_sources[0x52]	11443	1			T1	27		T4	136		T12	1
valid_sources[0x53]	10271	1			T1	31		T4	142		T15	2
valid_sources[0x54]	10274	1			T1	28		T2	16		T4	168
valid_sources[0x55]	14182	1			T1	19		T4	117		T12	5
valid_sources[0x56]	9922	1			T1	23		T4	172		T12	2
valid_sources[0x57]	9822	1			T1	24		T4	134		T12	7
valid_sources[0x58]	10208	1			T1	24		T4	165		T12	3
valid_sources[0x59]	10291	1			T1	29		T4	159		T12	3
valid_sources[0x5a]	9945	1			T1	33		T4	168		T12	2
valid_sources[0x5b]	11282	1			T1	18		T2	23		T4	161
valid_sources[0x5c]	11214	1			T1	20		T2	37		T4	161
valid_sources[0x5d]	10569	1			T1	20		T2	26		T4	171
valid_sources[0x5e]	11657	1			T1	20		T4	146		T12	11
valid_sources[0x5f]	10762	1			T1	22		T2	24		T4	161
valid_sources[0x60]	10058	1			T1	20		T2	22		T4	163
valid_sources[0x61]	10586	1			T1	23		T4	184		T12	5
valid_sources[0x62]	11553	1			T1	18		T4	178		T12	3
valid_sources[0x63]	10485	1			T1	26		T2	47		T4	162
valid_sources[0x64]	23598	1			T1	26		T4	155		T12	7
valid_sources[0x65]	12177	1			T1	15		T4	155		T13	1
valid_sources[0x66]	12539	1			T1	21		T4	151		T12	10
valid_sources[0x67]	11121	1			T1	20		T2	39		T4	140
valid_sources[0x68]	10604	1			T1	25		T4	147		T12	1
valid_sources[0x69]	10108	1			T1	20		T4	142		T12	5
valid_sources[0x6a]	11886	1			T1	23		T2	13		T4	161
valid_sources[0x6b]	10716	1			T1	25		T2	37		T4	126
valid_sources[0x6c]	11071	1			T1	24		T2	1		T4	148
valid_sources[0x6d]	12166	1			T1	24		T2	4		T4	134
valid_sources[0x6e]	10417	1			T1	19		T2	12		T4	150
valid_sources[0x6f]	9776	1			T1	14		T4	136		T12	1
valid_sources[0x70]	10221	1			T1	30		T4	134		T13	2
valid_sources[0x71]	14329	1			T1	30		T4	156		T12	4
valid_sources[0x72]	10284	1			T1	18		T4	133		T11	1
valid_sources[0x73]	11137	1			T1	24		T4	141		T11	1
valid_sources[0x74]	10362	1			T1	28		T2	49		T4	146
valid_sources[0x75]	10417	1			T1	19		T4	128		T12	4
valid_sources[0x76]	10472	1			T1	32		T4	165		T12	3
valid_sources[0x77]	10213	1			T1	23		T4	135		T12	6
valid_sources[0x78]	9796	1			T1	25		T4	141		T12	1
valid_sources[0x79]	11212	1			T1	25		T4	146		T12	9
valid_sources[0x7a]	9860	1			T1	18		T4	147		T12	1
valid_sources[0x7b]	10686	1			T1	21		T4	131		T12	7
valid_sources[0x7c]	10117	1			T1	29		T4	119		T12	3
valid_sources[0x7d]	10574	1			T1	21		T4	138		T12	6
valid_sources[0x7e]	12465	1			T1	20		T4	156		T12	3
valid_sources[0x7f]	10170	1			T1	17		T4	150		T12	5
valid_sources[0x80]	10072	1			T1	11		T2	10		T4	151

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1396841

1

T1

2459

T2

433

T3

320

values[0x0]

all_enables

biggest_size

140000

1

T1

261

T2

356

T3

254

values[0x1]

all_enables

biggest_size

140357

1

T1

226

T2

324

T3

256