Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	98717437	14333	0	0
claim_transition_if_regwen_rd_A	98717437	1284	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98717437	14333	0	0
T20	100664	9	0	0
T39	901	0	0	0
T43	22897	0	0	0
T47	29108	0	0	0
T68	5512	0	0	0
T83	8333	0	0	0
T85	1125	0	0	0
T88	0	2	0	0
T95	0	3	0	0
T104	0	13	0	0
T136	0	1	0	0
T138	0	4	0	0
T139	0	7	0	0
T140	0	4	0	0
T141	0	14	0	0
T142	0	12	0	0
T143	31632	0	0	0
T144	3461	0	0	0
T145	38792	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98717437	1284	0	0
T41	1233	0	0	0
T51	197645	0	0	0
T62	29530	0	0	0
T88	370409	2	0	0
T110	0	22	0	0
T123	0	55	0	0
T140	0	3	0	0
T146	0	10	0	0
T147	0	2	0	0
T148	0	3	0	0
T149	0	4	0	0
T150	0	6	0	0
T151	0	67	0	0
T152	133873	0	0	0
T153	115924	0	0	0
T154	35054	0	0	0
T155	54470	0	0	0
T156	925	0	0	0
T157	29237	0	0	0