Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107360582

1

T1

17986

T2

66040

T3

27529

auto[1]

1376258

1

T1

2475

T2

1881

T3

3762

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107386399

1

T1

18184

T2

66733

T3

28915

auto[1]

1350441

1

T1

2277

T2

1188

T3

2376

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7562383	1			T1	6207		T2	7830		T3	9086
auto[IdleSt]	24321931	1			T1	978		T2	2499		T3	1846
auto[ClkMuxSt]	37789	1			T2	75		T4	5		T5	64
auto[CntIncrSt]	37408	1			T2	75		T4	5		T5	64
auto[CntProgSt]	1866291	1			T2	299		T4	185		T5	1417
auto[TransCheckSt]	29201	1			T2	55		T4	5		T5	50
auto[TokenHashSt]	38794380	1			T2	42374		T4	54952		T5	3443
auto[FlashRmaSt]	37493	1			T2	188		T4	28		T5	36
auto[TokenCheck0St]	13329	1			T2	51		T4	5		T5	14
auto[TokenCheck1St]	9767	1			T2	32		T4	5		T5	5
auto[TransProgSt]	531106	1			T2	151		T4	107		T5	129
auto[PostTransSt]	15481998	1			T2	9546		T4	1438		T5	95280
auto[ScrapSt]	216124	1			T4	2583		T6	2292		T14	3
auto[EscalateSt]	7246937	1			T1	6565		T2	3908		T3	8968
auto[InvalidSt]	12548869	1			T1	6707		T2	838		T3	11385

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1834	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12548869	1			T1	6707		T2	838		T3	11385
EscalateSt	7246937	1			T1	6565		T2	3908		T3	8968
ScrapSt	216124	1			T4	2583		T6	2292		T14	3
PostTransSt	15481998	1			T2	9546		T4	1438		T5	95280
TransProgSt	531106	1			T2	151		T4	107		T5	129
TokenCheck1St	9767	1			T2	32		T4	5		T5	5
TokenCheck0St	13329	1			T2	51		T4	5		T5	14
FlashRmaSt	37493	1			T2	188		T4	28		T5	36
TokenHashSt	38794380	1			T2	42374		T4	54952		T5	3443
TransCheckSt	29201	1			T2	55		T4	5		T5	50
CntProgSt	1866291	1			T2	299		T4	185		T5	1417
CntIncrSt	37408	1			T2	75		T4	5		T5	64
ClkMuxSt	37789	1			T2	75		T4	5		T5	64
IdleSt	24321931	1			T1	978		T2	2499		T3	1846
ResetSt	7562383	1			T1	6207		T2	7830		T3	9086
arcs[ResetSt=>IdleSt]	55427	1			T1	54		T2	87		T3	76
arcs[IdleSt=>ScrapSt]	292	1			T4	1		T6	1		T14	1
arcs[IdleSt=>ClkMuxSt]	37460	1			T2	75		T4	5		T5	64
arcs[ClkMuxSt=>CntIncrSt]	37408	1			T2	75		T4	5		T5	64
arcs[CntIncrSt=>PostTransSt]	2114	1			T5	8		T17	37		T18	11
arcs[CntIncrSt=>CntProgSt]	35237	1			T2	75		T4	5		T5	56
arcs[CntProgSt=>PostTransSt]	5040	1			T2	20		T5	6		T12	9
arcs[CntProgSt=>TransCheckSt]	29201	1			T2	55		T4	5		T5	50
arcs[TransCheckSt=>PostTransSt]	4097	1			T5	8		T17	30		T18	7
arcs[TransCheckSt=>TokenHashSt]	24960	1			T2	55		T4	5		T5	42
arcs[TokenHashSt=>PostTransSt]	10872	1			T2	4		T5	28		T12	5
arcs[TokenHashSt=>FlashRmaSt]	13421	1			T2	51		T4	5		T5	14
arcs[FlashRmaSt=>TokenCheck0St]	13329	1			T2	51		T4	5		T5	14
arcs[TokenCheck0St=>PostTransSt]	3533	1			T2	19		T5	9		T12	12
arcs[TokenCheck0St=>TokenCheck1St]	9767	1			T2	32		T4	5		T5	5
arcs[TokenCheck1St=>PostTransSt]	642	1			T2	2		T12	1		T17	1
arcs[TransProgSt=>PostTransSt]	8240	1			T2	30		T4	5		T5	5
arcs[IdleSt=>EscalateSt]	175	1			T53	5		T56	7		T54	7
arcs[ClkMuxSt=>EscalateSt]	52	1			T53	1		T54	3		T55	3
arcs[CntIncrSt=>EscalateSt]	57	1			T14	1		T53	1		T56	1
arcs[CntProgSt=>EscalateSt]	996	1			T14	11		T53	7		T56	29
arcs[TransCheckSt=>EscalateSt]	144	1			T14	2		T53	5		T54	1
arcs[TokenHashSt=>EscalateSt]	667	1			T14	18		T18	1		T53	13
arcs[FlashRmaSt=>EscalateSt]	92	1			T14	2		T53	4		T54	3
arcs[TokenCheck0St=>EscalateSt]	29	1			T14	2		T53	1		T56	2
arcs[TokenCheck1St=>EscalateSt]	140	1			T14	2		T53	4		T54	7
arcs[TransProgSt=>EscalateSt]	745	1			T14	6		T53	6		T56	24
arcs[PostTransSt=>EscalateSt]	5310	1			T2	20		T5	6		T12	9
arcs[InvalidSt=>EscalateSt]	13303	1			T1	48		T2	11		T3	62

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7562201	1			T1	6207		T2	7830		T3	9086
auto[0]	auto[IdleSt]	24321814	1			T1	978		T2	2499		T3	1846
auto[0]	auto[ClkMuxSt]	37758	1			T2	75		T4	5		T5	64
auto[0]	auto[CntIncrSt]	37371	1			T2	75		T4	5		T5	64
auto[0]	auto[CntProgSt]	1865623	1			T2	299		T4	185		T5	1417
auto[0]	auto[TransCheckSt]	29100	1			T2	55		T4	5		T5	50
auto[0]	auto[TokenHashSt]	38793930	1			T2	42374		T4	54952		T5	3443
auto[0]	auto[FlashRmaSt]	37422	1			T2	188		T4	28		T5	36
auto[0]	auto[TokenCheck0St]	13308	1			T2	51		T4	5		T5	14
auto[0]	auto[TokenCheck1St]	9677	1			T2	32		T4	5		T5	5
auto[0]	auto[TransProgSt]	530604	1			T2	151		T4	107		T5	129
auto[0]	auto[PostTransSt]	15479256	1			T2	9535		T4	1438		T5	95277
auto[0]	auto[ScrapSt]	216076	1			T4	2583		T6	2292		T14	2
auto[0]	auto[EscalateSt]	5882439	1			T1	4115		T2	2046		T3	5244
auto[0]	auto[InvalidSt]	12542169	1			T1	6682		T2	830		T3	11347
auto[1]	auto[ResetSt]	182	1			T14	4		T53	5		T56	5
auto[1]	auto[IdleSt]	117	1			T53	4		T56	5		T54	4
auto[1]	auto[ClkMuxSt]	31	1			T53	1		T54	1		T55	3
auto[1]	auto[CntIncrSt]	37	1			T56	1		T54	1		T150	2
auto[1]	auto[CntProgSt]	668	1			T14	7		T53	3		T56	19
auto[1]	auto[TransCheckSt]	101	1			T14	2		T53	3		T150	4
auto[1]	auto[TokenHashSt]	450	1			T14	12		T18	1		T53	7
auto[1]	auto[FlashRmaSt]	71	1			T14	2		T53	4		T54	2
auto[1]	auto[TokenCheck0St]	21	1			T56	2		T207	1		T208	1
auto[1]	auto[TokenCheck1St]	90	1			T14	1		T53	4		T54	2
auto[1]	auto[TransProgSt]	502	1			T14	2		T53	4		T56	20
auto[1]	auto[PostTransSt]	2742	1			T2	11		T5	3		T12	7
auto[1]	auto[ScrapSt]	48	1			T14	1		T53	2		T56	2
auto[1]	auto[EscalateSt]	1364498	1			T1	2450		T2	1862		T3	3724
auto[1]	auto[InvalidSt]	6700	1			T1	25		T2	8		T3	38

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7562208	1			T1	6207		T2	7830		T3	9086
auto[0]	auto[IdleSt]	24321820	1			T1	978		T2	2499		T3	1846
auto[0]	auto[ClkMuxSt]	37753	1			T2	75		T4	5		T5	64
auto[0]	auto[CntIncrSt]	37369	1			T2	75		T4	5		T5	64
auto[0]	auto[CntProgSt]	1865618	1			T2	299		T4	185		T5	1417
auto[0]	auto[TransCheckSt]	29110	1			T2	55		T4	5		T5	50
auto[0]	auto[TokenHashSt]	38793933	1			T2	42374		T4	54952		T5	3443
auto[0]	auto[FlashRmaSt]	37429	1			T2	188		T4	28		T5	36
auto[0]	auto[TokenCheck0St]	13314	1			T2	51		T4	5		T5	14
auto[0]	auto[TokenCheck1St]	9674	1			T2	32		T4	5		T5	5
auto[0]	auto[TransProgSt]	530603	1			T2	151		T4	107		T5	129
auto[0]	auto[PostTransSt]	15479346	1			T2	9537		T4	1438		T5	95277
auto[0]	auto[ScrapSt]	216081	1			T4	2583		T6	2292		T14	2
auto[0]	auto[EscalateSt]	5908041	1			T1	4311		T2	2732		T3	6616
auto[0]	auto[InvalidSt]	12542266	1			T1	6684		T2	835		T3	11361
auto[1]	auto[ResetSt]	175	1			T14	2		T53	4		T56	5
auto[1]	auto[IdleSt]	111	1			T53	3		T56	5		T54	4
auto[1]	auto[ClkMuxSt]	36	1			T53	1		T54	3		T55	1
auto[1]	auto[CntIncrSt]	39	1			T14	1		T53	1		T56	1
auto[1]	auto[CntProgSt]	673	1			T14	10		T53	4		T56	24
auto[1]	auto[TransCheckSt]	91	1			T53	4		T54	1		T150	4
auto[1]	auto[TokenHashSt]	447	1			T14	11		T53	9		T56	9
auto[1]	auto[FlashRmaSt]	64	1			T14	2		T53	3		T54	2
auto[1]	auto[TokenCheck0St]	15	1			T14	2		T53	1		T54	1
auto[1]	auto[TokenCheck1St]	93	1			T14	1		T53	1		T54	7
auto[1]	auto[TransProgSt]	503	1			T14	5		T53	3		T56	12
auto[1]	auto[PostTransSt]	2652	1			T2	9		T5	3		T12	2
auto[1]	auto[ScrapSt]	43	1			T14	1		T53	2		T56	1
auto[1]	auto[EscalateSt]	1338896	1			T1	2254		T2	1176		T3	2352
auto[1]	auto[InvalidSt]	6603	1			T1	23		T2	3		T3	24